JPS6271749U - - Google Patents

Info

Publication number
JPS6271749U
JPS6271749U JP16275385U JP16275385U JPS6271749U JP S6271749 U JPS6271749 U JP S6271749U JP 16275385 U JP16275385 U JP 16275385U JP 16275385 U JP16275385 U JP 16275385U JP S6271749 U JPS6271749 U JP S6271749U
Authority
JP
Japan
Prior art keywords
buses
enable signal
gates
bus
bus enable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16275385U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16275385U priority Critical patent/JPS6271749U/ja
Publication of JPS6271749U publication Critical patent/JPS6271749U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示す回路構成図
、第2図は同実施例を説明するためのタイムチヤ
ート、第3図は従来のバス制御回路の一例を示す
回図構成図、第4図は同回路を説明するためのタ
イムチヤートである。 11〜14…バス、15〜17…ゲート、18
〜20…ノア回路、21…ナンド回路、22,2
3…インバータ。
Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a time chart for explaining the embodiment, and Fig. 3 is a circuit diagram showing an example of a conventional bus control circuit. Figure 4 is a time chart for explaining the circuit. 11-14...Bus, 15-17...Gate, 18
~20...NOR circuit, 21...NAND circuit, 22,2
3...Inverter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ゲートを介して接続されたデータ情報などを伝
送する複数のバスを、適宜ゲートにバスイネーブ
ル信号を印加することにより所望のバス同士を切
換接続するようにした小形電子式計算機において
、バス切換時に各ゲートに与えられるバスイネー
ブル信号を所定時間マスクする手段を設けバス切
換時に全てのバスをデスエーブル状態にさせるよ
うにしたことを特徴とするバス制御回路。
In a small electronic calculator, multiple buses that transmit data information, etc. connected via gates are switched and connected to each other by applying a bus enable signal to the gates as appropriate. 1. A bus control circuit comprising means for masking a bus enable signal applied to a gate for a predetermined period of time so that all buses are brought into a disabled state when switching buses.
JP16275385U 1985-10-23 1985-10-23 Pending JPS6271749U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16275385U JPS6271749U (en) 1985-10-23 1985-10-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16275385U JPS6271749U (en) 1985-10-23 1985-10-23

Publications (1)

Publication Number Publication Date
JPS6271749U true JPS6271749U (en) 1987-05-08

Family

ID=31090316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16275385U Pending JPS6271749U (en) 1985-10-23 1985-10-23

Country Status (1)

Country Link
JP (1) JPS6271749U (en)

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