JPS6283261U - - Google Patents
Info
- Publication number
- JPS6283261U JPS6283261U JP17464885U JP17464885U JPS6283261U JP S6283261 U JPS6283261 U JP S6283261U JP 17464885 U JP17464885 U JP 17464885U JP 17464885 U JP17464885 U JP 17464885U JP S6283261 U JPS6283261 U JP S6283261U
- Authority
- JP
- Japan
- Prior art keywords
- floppy disk
- circuit
- crc
- control circuit
- additional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
第１図は本考案に係るＦＤＣの一実施例を示す
構成図、第２図は付加ＣＲＣ回路２０の詳細を示
す構成図、第３図は付加ＣＲＣ回路２０の概念図
、第４図は動作を説明するためのタイミングチヤ
ート、第５図は従来のＦＤＣの一例を示す図であ
る。
２……データバス、１０……８×３３０ＦＤＣ
、２０……付加ＣＲＣ回路、３０……制御回路、
２１……シフトレジスタ、２２……ＣＲＣ発生器
、２３……カウンタ、２４……フリツプフロツプ
。
FIG. 1 is a block diagram showing an embodiment of the FDC according to the present invention, FIG. 2 is a block diagram showing details of the additional CRC circuit 20, FIG. 3 is a conceptual diagram of the additional CRC circuit 20, and FIG. 4 is the operation. FIG. 5 is a timing chart for explaining an example of a conventional FDC. 2...Data bus, 10...8x330FDC
, 20...Additional CRC circuit, 30...Control circuit,
21...Shift register, 22...CRC generator, 23...Counter, 24...Flip-flop.
Claims (1)
ロール回路と、 シフトレジスタとＣＲＣ発生器とをリング状に
接続し、８パルスのシフトクロツクを自動生成す
るカウンタを組合せ、ＣＲＣ演算及びチエツクを
行うことができるようにした付加ＣＲＣ回路と、 前記フロツピーデイスクコントロール回路と付
加ＣＲＣ回路を制御する制御回路と を具備し、前記フロツピーデイスクコントロール
回路と付加ＣＲＣ回路をデータバス上に共通に接
続し、Ｍ２ＦＭ記録方式を対象とする場合には付
加ＣＲＣ回路にもデータを転送することによつて
ＣＲＣ演算及びチエツクを行い得るようにしたこ
とを特徴とするフロツピーデイスク・コントロー
ラ。[Claims for Utility Model Registration] A floppy disk control circuit for M2 FM recording system, a shift register and a CRC generator are connected in a ring, and a counter that automatically generates an 8-pulse shift clock is combined to perform CRC calculation and An additional CRC circuit capable of performing a check, and a control circuit for controlling the floppy disk control circuit and the additional CRC circuit, and the floppy disk control circuit and the additional CRC circuit are commonly connected on a data bus. A floppy disk controller characterized in that it is connected to a floppy disk controller and is capable of performing CRC calculation and checking by transferring data to an additional CRC circuit when the M 2 FM recording method is to be used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17464885U JPS6283261U (en) | 1985-11-13 | 1985-11-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17464885U JPS6283261U (en) | 1985-11-13 | 1985-11-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6283261U true JPS6283261U (en) | 1987-05-27 |
Family
ID=31113229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17464885U Pending JPS6283261U (en) | 1985-11-13 | 1985-11-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6283261U (en) |
-
1985
- 1985-11-13 JP JP17464885U patent/JPS6283261U/ja active Pending
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