JPH01151641U - - Google Patents
Info
- Publication number
- JPH01151641U JPH01151641U JP1988049041U JP4904188U JPH01151641U JP H01151641 U JPH01151641 U JP H01151641U JP 1988049041 U JP1988049041 U JP 1988049041U JP 4904188 U JP4904188 U JP 4904188U JP H01151641 U JPH01151641 U JP H01151641U
- Authority
- JP
- Japan
- Prior art keywords
- data
- buffers
- buses
- receiving
- anomaly detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 5
- 230000005856 abnormality Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は、本考案の一実施例を示すブロツク図
、第２図は従来の入出力制御装置の一例を示すブ
ロツク図である。
１〜４……ドライバ、５，６……バツフア、７
……データ異常検出部、９……受信部、１１，１
２……バス、１３……コリジヨン検出部、２０，
２０ａ……入出力制御装置。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional input/output control device. 1-4...driver, 5,6...buffer, 7
...Data abnormality detection section, 9...Receiving section, 11,1
2...Bus, 13...Collision detection section, 20,
20a...Input/output control device.
Claims (1)
スシステムの入出力制御装置において、前記複数
のバスからのそれぞれのデータを受信して収納す
る複数のバツフアと、この複数のバツフアへ収納
する前の前記それぞれのデータの異常の有無を同
時に監視するデータ異常検出部と、前記複数のバ
ツフアからの出力の選択が前記データ異常検出部
からの異常検出信号によつて正常なデータを収納
しているバツフアからの出力に切替える切替部と
、この切替部からのデータを受信する受信部とを
有することを特徴とする入出力制御装置。 In an input/output control device for a common bus system that transmits and receives data from a plurality of buses, there are a plurality of buffers for receiving and storing data from the plurality of buses, and a plurality of buffers for receiving and storing data from the plurality of buses, and a plurality of buffers for receiving and storing data from the plurality of buses; a data anomaly detection unit that simultaneously monitors the presence or absence of an abnormality in each data; and selection of outputs from the plurality of buffers from buffers storing normal data in response to an anomaly detection signal from the data anomaly detection unit; An input/output control device comprising: a switching section that switches to an output of the switching section; and a receiving section that receives data from the switching section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988049041U JPH01151641U (en) | 1988-04-11 | 1988-04-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988049041U JPH01151641U (en) | 1988-04-11 | 1988-04-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01151641U true JPH01151641U (en) | 1989-10-19 |
Family
ID=31275161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988049041U Pending JPH01151641U (en) | 1988-04-11 | 1988-04-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01151641U (en) |
-
1988
- 1988-04-11 JP JP1988049041U patent/JPH01151641U/ja active Pending
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