JPH0164753U - - Google Patents
Info
- Publication number
- JPH0164753U JPH0164753U JP1987158039U JP15803987U JPH0164753U JP H0164753 U JPH0164753 U JP H0164753U JP 1987158039 U JP1987158039 U JP 1987158039U JP 15803987 U JP15803987 U JP 15803987U JP H0164753 U JPH0164753 U JP H0164753U
- Authority
- JP
- Japan
- Prior art keywords
- host computer
- bus
- relay
- signal
- switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案を実施したバス二重化制御装置
の構成を表わす図、第２図は本考案装置の動作の
一例を表わすタイムチヤート、第３図は本考案装
置を用いたシステムを表わす図、第４図は従来の
システムを表わす図である。
１……第１のホスト計算機、２……第２のホス
ト計算機、３……周辺装置、３１……第１のＳＣ
ＳＩ装置、３２……第２のＳＣＳＩ装置、３３…
…ＳＣＳＩ装置、４０……バス二重化制御装置、
４１……リレー制御部、ｒ１，ｒ２……リレー、
Ｒ１，Ｒ２……終端抵抗、ＳＢ……ＳＣＳＩバス
。
FIG. 1 is a diagram showing the configuration of a bus duplex control device implementing the present invention, FIG. 2 is a time chart showing an example of the operation of the device of the present invention, and FIG. 3 is a diagram showing a system using the device of the present invention. FIG. 4 is a diagram showing a conventional system. 1... First host computer, 2... Second host computer, 3... Peripheral device, 31... First SC
SI device, 32... Second SCSI device, 33...
...SCSI device, 40...Bus duplex control device,
41...Relay control unit, r1, r2...Relay,
R1, R2...Terminal resistor, SB...SCSI bus.
Claims (1)
バスを切り換え制御するバス二重化制御装置にお
いて、各々のホスト計算機に対応して設けた終端
抵抗と、各々のホスト計算機について前記周辺装
置に接続されるバスを当該ホスト計算機または前
記終端抵抗のいずれかに接続するリレーと、前記
各々のホスト計算機から電源オン信号とバス上の
信号を無効とするリセツト信号とにより前記リレ
ーを切り換えるリレー制御部とを備えたことを特
徴とするバス二重化制御装置。 In a bus duplex control device that switches and controls buses connecting two or more host computers and peripheral devices, a terminal resistor provided corresponding to each host computer and a bus connected to the peripheral device for each host computer are provided. a relay that connects the terminal to either the host computer or the terminating resistor, and a relay control unit that switches the relay in response to a power-on signal from each host computer and a reset signal that invalidates the signal on the bus. A bus duplex control device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987158039U JPH0164753U (en) | 1987-10-15 | 1987-10-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987158039U JPH0164753U (en) | 1987-10-15 | 1987-10-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0164753U true JPH0164753U (en) | 1989-04-25 |
Family
ID=31438007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987158039U Pending JPH0164753U (en) | 1987-10-15 | 1987-10-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0164753U (en) |
-
1987
- 1987-10-15 JP JP1987158039U patent/JPH0164753U/ja active Pending
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