JPS63159436U - - Google Patents
Info
- Publication number
- JPS63159436U JPS63159436U JP5064587U JP5064587U JPS63159436U JP S63159436 U JPS63159436 U JP S63159436U JP 5064587 U JP5064587 U JP 5064587U JP 5064587 U JP5064587 U JP 5064587U JP S63159436 U JPS63159436 U JP S63159436U
- Authority
- JP
- Japan
- Prior art keywords
- management
- signal
- computer
- signal line
- station
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001052 transient effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は、本考案の一実施例を示す構成ブロツ
ク図、第２図は従来装置の構成ブロツク図である
。
１０……計算機、１１……セツト端子、１２…
…リセツト端子、１３……Ｑ端子、１４……ＲＳ
フリツプフロツプ、１５……プルアツプ電源。２
０……二重化管理部、２１……スイツチ部、２２
……信号ドライバ。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional device. 10...Calculator, 11...Set terminal, 12...
...Reset terminal, 13...Q terminal, 14...RS
Flip-flop, 15...Pull-up power supply. 2
0... Duplex management section, 21... Switch section, 22
...Signal driver.
Claims (1)
を主系とする第１の信号線、第２の管理信号がＬ
であるときは第２の計算機を主系とする第２の信
号線、第１又は第２の管理信号のいずれか一方は
Ｌとし他方はＨとする二重化管理部、 とを備えた二重化制御システムにおいて、 各計算機の自局の管理信号を入力するセツト端
子、自局と対になる他局の管理信号を入力するリ
セツト端子、これらセツト端子とリセツト端子の
信号を論理演算し当該計算機に管理信号として出
力するＱ端子、とよりなるＲＳフリツプフロツプ
と、 これらセツト端子とリセツト端子に入力される
管理信号を論理Ｈにプルアツプするプルアツプ電
源と、 を各計算機に設けると共に、 二重化管理部を第１及び第２の信号線と離脱も
しくは装着する際に、少なくともその過渡状態に
おいてＬを出力するスイツチ部と、 このスイツチ部の出力がＬであるとき二重化管
理部と各計算機とを接続する第１及び第２の管理
信号を全てオフする信号ドライバと、 を二重化管理部若しくは第１及び第２の信号線
に設けたこと、 を特徴とする二重化制御システム。[Claims for Utility Model Registration] Duplicated computers, when the first management signal is L, the first signal line with the first computer as the main system, and the second management signal is L
, a redundant control system comprising: a second signal line with the second computer as the main system; a redundant management unit that sets one of the first or second management signals to L and the other to H; In each computer, there is a set terminal for inputting the management signal of its own station, a reset terminal for inputting the management signal of the other station paired with the own station, and a logical operation is performed on the signals of these set and reset terminals to send the management signal to the computer concerned. Each computer is provided with an RS flip-flop consisting of a Q terminal that outputs a a switch section that outputs L at least in a transient state when the signal line of No. 2 is disconnected from or attached to the second signal line; and first and second switches that connect the redundancy management section and each computer when the output of this switch section is L; A redundant control system comprising: a signal driver that turns off all management signals;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5064587U JPS63159436U (en) | 1987-04-03 | 1987-04-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5064587U JPS63159436U (en) | 1987-04-03 | 1987-04-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63159436U true JPS63159436U (en) | 1988-10-19 |
Family
ID=30874192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5064587U Pending JPS63159436U (en) | 1987-04-03 | 1987-04-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63159436U (en) |
-
1987
- 1987-04-03 JP JP5064587U patent/JPS63159436U/ja active Pending
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