JPH0172649U - - Google Patents
Info
- Publication number
- JPH0172649U JPH0172649U JP1987167834U JP16783487U JPH0172649U JP H0172649 U JPH0172649 U JP H0172649U JP 1987167834 U JP1987167834 U JP 1987167834U JP 16783487 U JP16783487 U JP 16783487U JP H0172649 U JPH0172649 U JP H0172649U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- expansion port
- failure
- output
- reset signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 239000013256 coordination polymer Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案の構成を示すブロツク図、第２
図は本考案の一実施例を示すブロツク回路図、第
３図は同上実施例におけるＣＰＵの故障検出を示
すタイムチヤート、第４図は同上実施例における
フエイルセーフ制御を示すフローチヤート、第５
図及び第６図は従来例を示すブロツク回路図であ
る。
１……ＣＰＵ、２……拡張ポート、３……ＣＰ
Ｕ故障検出回路、Ａ，Ｂ……外部装置、Ｒ１……
プルアツプ抵抗、Ｒ２……プルダウン抵抗。
Figure 1 is a block diagram showing the configuration of the present invention;
The figure is a block circuit diagram showing one embodiment of the present invention, FIG. 3 is a time chart showing failure detection of the CPU in the same embodiment, FIG. 4 is a flow chart showing fail-safe control in the above embodiment, and FIG.
6 are block circuit diagrams showing a conventional example. 1...CPU, 2...Expansion port, 3...CP
U failure detection circuit, A, B... external device, R 1 ...
Pull-up resistor, R2 ...Pull-down resistor.
Claims (1)
ＣＰＵ拡張ポートを高インピーダンス状態にする
リセツト制御手段を備える一方、ＣＰＵの故障を
検出する故障検出部を備えかつ該故障検出部によ
る故障検出時に前記リセツト制御手段のリセツト
信号ラインを絶つて前記リセツト信号を前記ＣＰ
Ｕ拡張ポートに独立して出力するＣＰＵ故障時リ
セツト制御手段を設けると共に、高インピーダン
ス状態における前記ＣＰＵ拡張ポートの出力を、
該ＣＰＵ拡張ポートの出力で制御される外部装置
の安全側に固定するプルアツプ或いはプルダウン
抵抗を設けたことを特徴とするＣＰＵ拡張ポート
のフエイルセーフ装置。 The device includes a reset control means that outputs a reset signal to the CPU expansion port to put the CPU expansion port in a high impedance state, and also includes a failure detection section that detects a failure of the CPU, and performs the reset control when the failure detection section detects a failure. The reset signal line of the means is cut off and the reset signal is transferred to the CP.
A CPU failure reset control means is provided to independently output to the U expansion port, and the output of the CPU expansion port in a high impedance state is
1. A fail-safe device for a CPU expansion port, characterized in that a pull-up or pull-down resistor is provided for fixing an external device controlled by the output of the CPU expansion port on the safe side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987167834U JPH0172649U (en) | 1987-11-04 | 1987-11-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987167834U JPH0172649U (en) | 1987-11-04 | 1987-11-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0172649U true JPH0172649U (en) | 1989-05-16 |
Family
ID=31456483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987167834U Pending JPH0172649U (en) | 1987-11-04 | 1987-11-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0172649U (en) |
-
1987
- 1987-11-04 JP JP1987167834U patent/JPH0172649U/ja active Pending