JPH0172649U - - Google Patents

Info

Publication number
JPH0172649U
JPH0172649U JP1987167834U JP16783487U JPH0172649U JP H0172649 U JPH0172649 U JP H0172649U JP 1987167834 U JP1987167834 U JP 1987167834U JP 16783487 U JP16783487 U JP 16783487U JP H0172649 U JPH0172649 U JP H0172649U
Authority
JP
Japan
Prior art keywords
cpu
expansion port
failure
output
reset signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987167834U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987167834U priority Critical patent/JPH0172649U/ja
Publication of JPH0172649U publication Critical patent/JPH0172649U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の構成を示すブロツク図、第2
図は本考案の一実施例を示すブロツク回路図、第
3図は同上実施例におけるCPUの故障検出を示
すタイムチヤート、第4図は同上実施例における
フエイルセーフ制御を示すフローチヤート、第5
図及び第6図は従来例を示すブロツク回路図であ
る。 1……CPU、2……拡張ポート、3……CP
U故障検出回路、A,B……外部装置、R……
プルアツプ抵抗、R……プルダウン抵抗。
Figure 1 is a block diagram showing the configuration of the present invention;
The figure is a block circuit diagram showing one embodiment of the present invention, FIG. 3 is a time chart showing failure detection of the CPU in the same embodiment, FIG. 4 is a flow chart showing fail-safe control in the above embodiment, and FIG.
6 are block circuit diagrams showing a conventional example. 1...CPU, 2...Expansion port, 3...CP
U failure detection circuit, A, B... external device, R 1 ...
Pull-up resistor, R2 ...Pull-down resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] CPU拡張ポートにリセツト信号を出力して該
CPU拡張ポートを高インピーダンス状態にする
リセツト制御手段を備える一方、CPUの故障を
検出する故障検出部を備えかつ該故障検出部によ
る故障検出時に前記リセツト制御手段のリセツト
信号ラインを絶つて前記リセツト信号を前記CP
U拡張ポートに独立して出力するCPU故障時リ
セツト制御手段を設けると共に、高インピーダン
ス状態における前記CPU拡張ポートの出力を、
該CPU拡張ポートの出力で制御される外部装置
の安全側に固定するプルアツプ或いはプルダウン
抵抗を設けたことを特徴とするCPU拡張ポート
のフエイルセーフ装置。
The device includes a reset control means that outputs a reset signal to the CPU expansion port to put the CPU expansion port in a high impedance state, and also includes a failure detection section that detects a failure of the CPU, and performs the reset control when the failure detection section detects a failure. The reset signal line of the means is cut off and the reset signal is transferred to the CP.
A CPU failure reset control means is provided to independently output to the U expansion port, and the output of the CPU expansion port in a high impedance state is
1. A fail-safe device for a CPU expansion port, characterized in that a pull-up or pull-down resistor is provided for fixing an external device controlled by the output of the CPU expansion port on the safe side.
JP1987167834U 1987-11-04 1987-11-04 Pending JPH0172649U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987167834U JPH0172649U (en) 1987-11-04 1987-11-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987167834U JPH0172649U (en) 1987-11-04 1987-11-04

Publications (1)

Publication Number Publication Date
JPH0172649U true JPH0172649U (en) 1989-05-16

Family

ID=31456483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987167834U Pending JPH0172649U (en) 1987-11-04 1987-11-04

Country Status (1)

Country Link
JP (1) JPH0172649U (en)

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