JPS639601U - - Google Patents
Info
- Publication number
- JPS639601U JPS639601U JP10304186U JP10304186U JPS639601U JP S639601 U JPS639601 U JP S639601U JP 10304186 U JP10304186 U JP 10304186U JP 10304186 U JP10304186 U JP 10304186U JP S639601 U JPS639601 U JP S639601U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- command
- load
- receives
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例の回路構成を示す図
、第２図は従来例の回路構成を示す図である。
１……ＡＮＤ要素、２，３，７……ＯＲ要素、
４，８……第１、第２のフリツプフロツプ要素、
５，９……第１、第２の出力ドライバー、６……
負荷。
FIG. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing the circuit configuration of a conventional example. 1...AND element, 2, 3, 7...OR element,
4, 8...first and second flip-flop elements,
5, 9...first and second output drivers, 6...
load.
Claims (1)
を受けるＯＲ要素と、このＯＲ要素の出力信号と
ＯＮ許可条件信号との一致をとるＡＮＤ要素と、
このＡＮＤ要素の出力信号による自動／手動指令
と保護動作によるＯＮ要求を受けるＯＲ要素と、
このＯＲ要素のＯＮ指令を記憶する第１のフリツ
プフロツプ要素と、この第１のフリツプフロツプ
要素にて記憶されたＯＮ指令を負荷に伝達する第
１の出力ドライバーと、自動／手動／保護動作に
よるＯＮ，ＯＰＥＮ要求を受けるＯＲ要素と、こ
のＯＲ要素のＯＮ指令を記憶する第２のフリツプ
フロツプ要素と、この第２のフリツプフロツプ要
素にて記憶されたＯＮ指令を負荷に伝達する第２
の出力ドライバーとを具備し、第１、第２の出力
ドライバーの出力で前記負荷を作動させるように
したことを特徴とするシーケンス制御装置。 An OR element that receives an ON or OPEN request due to automatic/manual operation, and an AND element that matches the output signal of this OR element with the ON permission condition signal;
an OR element that receives an automatic/manual command from the output signal of the AND element and an ON request from the protective operation;
A first flip-flop element that stores the ON command of the OR element; a first output driver that transmits the ON command stored in the first flip-flop element to the load; An OR element that receives an OPEN request, a second flip-flop element that stores the ON command of this OR element, and a second flip-flop element that transmits the ON command stored in the second flip-flop element to the load.
A sequence control device comprising: an output driver, and the load is operated by the outputs of the first and second output drivers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10304186U JPS639601U (en) | 1986-07-04 | 1986-07-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10304186U JPS639601U (en) | 1986-07-04 | 1986-07-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639601U true JPS639601U (en) | 1988-01-22 |
Family
ID=30975232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10304186U Pending JPS639601U (en) | 1986-07-04 | 1986-07-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639601U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4843147A (en) * | 1971-10-06 | 1973-06-22 |
-
1986
- 1986-07-04 JP JP10304186U patent/JPS639601U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4843147A (en) * | 1971-10-06 | 1973-06-22 |
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