JPS63129314U - - Google Patents

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Publication number
JPS63129314U
JPS63129314U JP2071287U JP2071287U JPS63129314U JP S63129314 U JPS63129314 U JP S63129314U JP 2071287 U JP2071287 U JP 2071287U JP 2071287 U JP2071287 U JP 2071287U JP S63129314 U JPS63129314 U JP S63129314U
Authority
JP
Japan
Prior art keywords
emitter follower
subtracts
utility
operational amplifier
scope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2071287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2071287U priority Critical patent/JPS63129314U/ja
Publication of JPS63129314U publication Critical patent/JPS63129314U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の第1実施例の構成を示す回路
図、第2図は本考案の第2実施例の構成を示す回
路図、第3図は本考案の第1実施例の変形例を示
す回路図、第4図は本考案の第2実施例の変形例
を示す回路図、第5図および第6図は従来例を示
す回路図である。 10……バツフア増幅器、11A……PNPト
ランジスタ、11B……NPNトランジスタ、1
3……定電流源、14……演算増幅器からなる差
動増幅器。
FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the second embodiment of the present invention, and FIG. 3 is a modification of the first embodiment of the present invention. FIG. 4 is a circuit diagram showing a modification of the second embodiment of the present invention, and FIGS. 5 and 6 are circuit diagrams showing a conventional example. 10...Buffer amplifier, 11A...PNP transistor, 11B...NPN transistor, 1
3... A differential amplifier consisting of a constant current source and 14... an operational amplifier.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] エミツタホロワと、該エミツタホロワの入力信
号と前記エミツタホロワの出力信号とを減算する
演算増幅器とを備えたことを特徴とする増幅回路
An amplifier circuit comprising: an emitter follower; and an operational amplifier that subtracts an input signal of the emitter follower and an output signal of the emitter follower.
JP2071287U 1987-02-17 1987-02-17 Pending JPS63129314U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2071287U JPS63129314U (en) 1987-02-17 1987-02-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2071287U JPS63129314U (en) 1987-02-17 1987-02-17

Publications (1)

Publication Number Publication Date
JPS63129314U true JPS63129314U (en) 1988-08-24

Family

ID=30816477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2071287U Pending JPS63129314U (en) 1987-02-17 1987-02-17

Country Status (1)

Country Link
JP (1) JPS63129314U (en)

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