JPH0290541U - - Google Patents
Info
- Publication number
- JPH0290541U JPH0290541U JP16953288U JP16953288U JPH0290541U JP H0290541 U JPH0290541 U JP H0290541U JP 16953288 U JP16953288 U JP 16953288U JP 16953288 U JP16953288 U JP 16953288U JP H0290541 U JPH0290541 U JP H0290541U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- ecl circuit
- ecl
- diagram showing
- interstage coupling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Amplifiers (AREA)
Description
第１図は本考案の第１の実施例のＥＣＬ回路の
段間結合回路を示す回路図、第２図は本考案の第
２の実施例のＥＣＬ回路の段間結合回路を示す回
路図、第３図は本考案の第３の実施例のＥＣＬ回
路の段間結合回路を示す回路図、第４図は従来の
ＥＣＬ回路の段間結合回路を示す回路図、第５図
は第４図のＥＣＬ回路を構成するフリツプフロツ
プ回路の回路図、第６図は従来と本考案との効果
を示す特性図である。
１……入力信号（パルス信号源）、２，３……
定電流源、４……バイアス源、５，６，１１，１
２，３３，３４，３５，３６，３７，３８，３９
，４０，５１，５２，５３，５４，５５，５６…
…ｎｐｎトランジスタ、２１，２２，２３，２１
′，２２′，２３′，６４，６５，６６，６７，
６８，６９……抵抗、７，８，９……フリツプフ
ロツプ。
FIG. 1 is a circuit diagram showing an inter-stage coupling circuit of an ECL circuit according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing an inter-stage coupling circuit of an ECL circuit according to a second embodiment of the present invention. 3 is a circuit diagram showing an interstage coupling circuit of an ECL circuit according to a third embodiment of the present invention, FIG. 4 is a circuit diagram showing an interstage coupling circuit of a conventional ECL circuit, and FIG. 5 is a circuit diagram showing an interstage coupling circuit of a conventional ECL circuit. FIG. 6 is a circuit diagram of a flip-flop circuit constituting the ECL circuit, and FIG. 6 is a characteristic diagram showing the effects of the conventional method and the present invention. 1...Input signal (pulse signal source), 2, 3...
Constant current source, 4...Bias source, 5, 6, 11, 1
2, 33, 34, 35, 36, 37, 38, 39
,40,51,52,53,54,55,56...
...npn transistor, 21, 22, 23, 21
', 22', 23', 64, 65, 66, 67,
68, 69...Resistance, 7,8,9...Flip-flop.
Claims (1)
ジスタを備え、前記エミツタに電流源が接続され
、前記第１、第２のトランジスタのベースにそれ
ぞれ前段のＥＣＬ回路の出力が接続され、前記第
１、第２のトランジスタのコレクタに、それぞれ
第１、第２の負荷抵抗が接続されるとともに次段
のＥＣＬ回路の入力に接続されていることを特徴
とするＥＣＬ回路の段間結合回路。 A current source is connected to the emitters, and the output of the ECL circuit at the previous stage is connected to the bases of the first and second transistors, respectively. An interstage coupling circuit for an ECL circuit, characterized in that first and second load resistors are connected to the collector of the second transistor, respectively, and are also connected to the input of the next stage ECL circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988169532U JP2526542Y2 (en) | 1988-12-28 | 1988-12-28 | Interstage coupling circuit of ECL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988169532U JP2526542Y2 (en) | 1988-12-28 | 1988-12-28 | Interstage coupling circuit of ECL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0290541U true JPH0290541U (en) | 1990-07-18 |
| JP2526542Y2 JP2526542Y2 (en) | 1997-02-19 |
Family
ID=31459680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988169532U Expired - Lifetime JP2526542Y2 (en) | 1988-12-28 | 1988-12-28 | Interstage coupling circuit of ECL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2526542Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629832A (en) * | 1992-05-13 | 1994-02-04 | Mitsubishi Electric Corp | Ecl circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164706A (en) * | 1986-12-26 | 1988-07-08 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1988
- 1988-12-28 JP JP1988169532U patent/JP2526542Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164706A (en) * | 1986-12-26 | 1988-07-08 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629832A (en) * | 1992-05-13 | 1994-02-04 | Mitsubishi Electric Corp | Ecl circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2526542Y2 (en) | 1997-02-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |