JPS611911U - Amplifier input bias adjustment circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the basic configuration of the circuit of FIG. 1, and FIG. 3 is a diagram illustrating an example of a conventional input bias adjustment circuit. Explanation of symbols of main parts, 1, 2...Current mirror circuit, Q1-Q6...NPN} transistor, Q
7~Q20...PNP }Ran resistor.

Claims (1)

[Scope of utility model registration request] An input bias adjustment circuit in a feedback amplifier whose input stage has a differential amplification circuit configuration, the input bias adjusting circuit comprising: a current mirror circuit constituting a constant current source of the amplifier circuit; current converting means that derives a current from a current mirror circuit and converts the derived current into a desired value; the current converting means has a base and an emitter connected in common, and converts the current at the base common connection point into the current of the current mirror circuit. a pair of transistors that serve as a base bias current for a common base connection transistor; and a pair of transistors each having a collector output applied to each emitter to divide the collector output of one of the pair of transistors into two;
An input bias adjustment circuit for an amplifier, characterized in that each base current of the latter pair of transistors is supplied to each base of the pair of differential transistors of the differential amplifier circuit.