JPS63128646A - Manufacture of multilayer interconnection structure - Google Patents
Manufacture of multilayer interconnection structureInfo
- Publication number
- JPS63128646A JPS63128646A JP27591186A JP27591186A JPS63128646A JP S63128646 A JPS63128646 A JP S63128646A JP 27591186 A JP27591186 A JP 27591186A JP 27591186 A JP27591186 A JP 27591186A JP S63128646 A JPS63128646 A JP S63128646A
- Authority
- JP
- Japan
- Prior art keywords
- film
- titanium
- titanium nitride
- nitride film
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000010936 titanium Substances 0.000 claims abstract description 23
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 23
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 10
- 239000004020 conductor Substances 0.000 abstract description 8
- 239000007789 gas Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 238000001953 recrystallisation Methods 0.000 abstract description 2
- 238000001552 radio frequency sputter deposition Methods 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 3
- -1 nitrogen ions Chemical class 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の多層配線構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a multilayer wiring structure of a semiconductor device.
ＬＳＩ配線材料としては、主としてアルミニウムが用い
られているが、多層配線構造のスルーホール部では、熱
処理等によシヒロツク々どが発生しやすい。そこで信頼
性確保のため、スルーホール部にバリアメタルとして窒
化チタン膜を配置しておくことが多い。この窒化チタン
膜の形成は、窒素ふんい気中でプラズマスパッタを行な
う高周波（ＲＦ）スパッタ法、あるいはチタン膜成長後
に窒素ふんい気中でアニールを行なう方法によっている
。Aluminum is mainly used as an LSI wiring material, but cracks are likely to occur in through-hole portions of multilayer wiring structures due to heat treatment and the like. Therefore, in order to ensure reliability, a titanium nitride film is often placed as a barrier metal in the through-hole portion. The titanium nitride film is formed by a radio frequency (RF) sputtering method in which plasma sputtering is performed in a nitrogen atmosphere, or by annealing in a nitrogen atmosphere after the titanium film is grown.
上記窒化チタン膜は、多層配線構造のバリアメタルとし
ては、前記ヒロックなどの防止に対しては極めて有益で
ある。しかし、従来の方法によって形成した窒化チタン
膜は、現実には膜質が不安定であシ、半導体装置の製造
過程において、その耐熱性がなくなシ、アルミ配線導体
と反応し、配線導体を変質または消失させるなど信頼性
上きわめて重大な障害をしばしば起こす欠点をもってい
た。これは、ＲＦスパッタ法による場合に、残留ガス（
酸素）と窒素のバランスによシ膜質が決定されるため、
チタンの窒化が均一に進まず、比抵抗値を測定するとバ
ラツ中が非常に大きく、膜質が不安定なものが生ずるか
らである。チタン膜形成後、輩索中にてアニールして形
成する後者の方法でも、同様である。The titanium nitride film is extremely useful as a barrier metal in a multilayer wiring structure in preventing the hillocks and the like. However, in reality, titanium nitride films formed by conventional methods are unstable in film quality, lose their heat resistance during the manufacturing process of semiconductor devices, and react with aluminum wiring conductors, changing the quality of the wiring conductors. It had the disadvantage of often causing extremely serious failures in terms of reliability, such as failure or disappearance. This is because residual gas (
The film quality is determined by the balance between oxygen) and nitrogen.
This is because the nitridation of titanium does not proceed uniformly, and when measuring the specific resistance value, there is a very large variation, resulting in unstable film quality. The same applies to the latter method in which the titanium film is formed by annealing in a tube after the titanium film is formed.
本発明の目的は、上記の欠点を除去し、半導体装置とし
て、信頼性の高いバリア層を有する多層配線構造の製造
方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a method for manufacturing a multilayer wiring structure having a highly reliable barrier layer as a semiconductor device.
本発明における多層配線構造の製造方法は、半導体装置
の主面上に形成された、下部配線層上にチタン膜を形成
する工程と、該チタン膜に窒素をイオン注入後、瞬間ア
ニール法によって該チタン膜の少なくとも表面に窒化チ
タン膜を形成する工程と、該窒化チタン膜上の層間絶縁
膜のスルーホールを介して該窒化チタン膜に接触する上
部配線層を形成する工程とを含むものである。The method for manufacturing a multilayer wiring structure according to the present invention includes the steps of forming a titanium film on a lower wiring layer formed on the main surface of a semiconductor device, and after implanting nitrogen ions into the titanium film, an instantaneous annealing method is used. The method includes a step of forming a titanium nitride film on at least the surface of the titanium film, and a step of forming an upper wiring layer in contact with the titanium nitride film through a through hole in an interlayer insulating film on the titanium nitride film.
以下、図面を参照して本発明の実施例につき説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は、第１実施例につき、工程順に示したものであ
る。この実施例は、眉間絶縁膜を、バリアメタル形成後
形成する場合である。第１図（１りは、半導体基板ｌ上
のフィールド酸化Ｊ１ｇ２に下部配線層としてアルミ配
線導体３が形成されていて、その上に、先ずＢＦスパッ
タ法で厚さ１００ＯＡのチタン膜４を形成した状態を示
すものである。次に第１図伽）で、窒素をチタン膜４の
中にイオン注入（ドーズ量２Ｘ１０１５／ｃｍ” 、
１０ ｋ ｅ Ｖ ）を行なう。イオン注入ハ、Ｒ，
（ピーク値を示す深さ） ＝ ２２５λ、ＳＤ（標準偏
差値） ＝ １２ＯＡと、深さに対する正規分布の状態
で打込まれる。FIG. 1 shows the steps of the first embodiment in order. In this example, the glabellar insulating film is formed after the barrier metal is formed. In Figure 1, an aluminum wiring conductor 3 is formed as a lower wiring layer on a field oxidation J1g2 on a semiconductor substrate l, and a titanium film 4 with a thickness of 100 OA is first formed on it by BF sputtering. Next, in Fig. 1(a), nitrogen ions are implanted into the titanium film 4 (dose amount: 2 x 1015/cm").
10 ke V). Ion implantation C, R,
(Depth showing peak value) = 225λ, SD (standard deviation value) = 12OA, and is implanted in a state of normal distribution with respect to depth.
次に第１図（ｅ）で、アニールを行ない、窒化チタンｌ
Ｉ５を形成する。アニールは、アニール炉中の残留ガス
（空気）によシ、チタンが酸化しないように、瞬間アニ
ール法を用いる。通常瞬間アニール法は３秒〜５０秒で
あるが、この実施例では赤外線照射によｐ温度５５０Ｃ
，時間１０秒で行なった。Next, as shown in FIG. 1(e), annealing is performed and titanium nitride l
Form I5. For annealing, an instantaneous annealing method is used to prevent titanium from oxidizing due to residual gas (air) in the annealing furnace. Normally instantaneous annealing is performed for 3 seconds to 50 seconds, but in this example, infrared irradiation was used at a p temperature of 550C.
, the time was 10 seconds.
以下、第１図（ｄ）に示すように、上部配線層を周知の
方法で行なう。窒化チタン膜５をホトレジスト法（ＰＲ
法）を用いてバターニングを行ないバリアメタル部１０
を形成してから、ＣＶＤ法で層間絶縁膜６を堆積する。Thereafter, as shown in FIG. 1(d), the upper wiring layer is formed by a well-known method. The titanium nitride film 5 is coated with a photoresist method (PR).
The barrier metal part 10 is patterned using
After forming, an interlayer insulating film 6 is deposited by the CVD method.
次にスルーホール７を開孔し、上部配線層としてアルミ
配線導体８を、スルーホール７を介してバリアメタル部
１０に接触させることで多層配線構造が形成される。Next, a through hole 7 is opened, and an aluminum wiring conductor 8 as an upper wiring layer is brought into contact with the barrier metal part 10 via the through hole 7, thereby forming a multilayer wiring structure.
第２実施例として、層間絶縁膜をイオン注入のマスクと
して利用した実施例を２図で説明する。第２図（ａ）に
示すように、半導体基板ｌ上のフィールド酸化膜２に、
下部配線層としてアルミ配線導体３が形成されていて、
その上に先ずチタン膜（厚さ１００ＯＡ ） ４を形成
する。そして、さらに層間絶縁膜６を形成しスルーホー
ル７を開孔しておく。As a second embodiment, an embodiment in which an interlayer insulating film is used as a mask for ion implantation will be described with reference to FIG. As shown in FIG. 2(a), on the field oxide film 2 on the semiconductor substrate l,
An aluminum wiring conductor 3 is formed as a lower wiring layer,
First, a titanium film (thickness: 100 OA) 4 is formed thereon. Then, an interlayer insulating film 6 is further formed and a through hole 7 is opened.
次に第２図（ｂ）に示すように、層間絶縁１１６をマス
クとしてスルーホール７の部分にあたるチタン膜４の中
に窒素をイオン注入（ドーズ量２Ｘ １０１Ｓ／ｃｍ”
１０ ｋｅｙ）する。注入された状態は第１実施例
と同じ＜Ｒ，＝２２５人、 ＳＤ＝ １２ＯＡの正規分
布である。Next, as shown in FIG. 2(b), using the interlayer insulation 116 as a mask, nitrogen ions are implanted into the titanium film 4 corresponding to the through hole 7 (dose amount: 2X 101S/cm").
10 key). The injected state is the same as the first example, with a normal distribution of <R, = 225 people, SD = 12OA.
次に、第２図（ｃ） において、瞬間アニール法を用い
、アニールを行なう。アニール条件は、第１実施例と同
じにする。これによシ窒化チタン膜５′がスルーホール
７のチタン膜４に形成され、この窒化チタン族５′とそ
の下部のチタン膜４とでバリアメタル部１σとなってい
る。以下、第２図（ｄｉに示すように、上部配線層とし
てアルミ配線導体８をスルーホール７を介してバリアメ
タル部１０′に接触させることで多層配線構造が形成さ
れる。Next, in FIG. 2(c), annealing is performed using the instantaneous annealing method. The annealing conditions are the same as in the first example. As a result, a titanium nitride film 5' is formed on the titanium film 4 of the through hole 7, and this titanium nitride group 5' and the titanium film 4 below form a barrier metal portion 1σ. Thereafter, as shown in FIG. 2 (di), a multilayer wiring structure is formed by bringing aluminum wiring conductor 8 as an upper wiring layer into contact with barrier metal portion 10' via through hole 7.
以上、説明したように、多層配線間の接続部分に、窒化
チタン膜をバリアメタルとして設けた多層構造において
、本発明は特に窒化チタン膜として緻密で、しかも耐熱
性で化学的に安定な膜を形成するようにしたものである
。窒化チタン膜の形成には、イオン注入によシ均一に所
定量だけ、チタン膜中に窒素原子を入れ、かつ瞬間アニ
ールにより、残留ガス（空気）の影響をうけないように
している。このように組成が一定であって、局所的な欠
陥のない窒化チタン膜は化学的・物理的に安定であって
、半導体装置のそれ以降の生産工程における熱処理によ
シ、従来生じていたスルーホール部のヒロツクトカ、ア
ルミ再結晶化は完全に防止できる。As explained above, in a multilayer structure in which a titanium nitride film is provided as a barrier metal at the connection portion between multilayer interconnections, the present invention particularly aims at providing a dense, heat-resistant, and chemically stable titanium nitride film. It was designed so that it could be formed. To form a titanium nitride film, nitrogen atoms are uniformly introduced into the titanium film in a predetermined amount by ion implantation, and instantaneous annealing is performed to prevent the film from being affected by residual gas (air). A titanium nitride film with a constant composition and no local defects is chemically and physically stable, and does not suffer from the through-through that conventionally occurs during heat treatment in the subsequent production process of semiconductor devices. It is possible to completely prevent cracks in the hole and aluminum recrystallization.
第１図、第２図は本発明の実施例を製造工程順に示す縦
断面図である。
１・・・半導体基板、 ２・・・フィールド酸化膜、
３．８・・・アルミ配線導体、 ４・・・チタン膜、
５．５′・・・窒化チタン膜、６・・・層間絶縁膜、７
・・・スルーホール、１０．１０’・・・バリアメタル
部。FIGS. 1 and 2 are longitudinal sectional views showing an embodiment of the present invention in the order of manufacturing steps. 1... Semiconductor substrate, 2... Field oxide film,
3.8...Aluminum wiring conductor, 4...Titanium film,
5.5'...Titanium nitride film, 6...Interlayer insulating film, 7
...Through hole, 10.10'...Barrier metal part.
Claims (1)
タン膜を形成する工程と、該チタン膜に窒素をイオン注
入後、瞬間アニール法によつて該チタン膜の少なくとも
表面に窒化チタン膜を形成する工程と、該窒化チタン膜
上の層間絶縁膜のスルーホールを介して該窒化チタン膜
に接触する上部配線層を形成する工程とを含むことを特
徴とする半導体装置の多層配線構造の製造方法。A step of forming a titanium film on the lower wiring layer formed on the main surface of the semiconductor device, and after ion-implanting nitrogen into the titanium film, a titanium nitride film is formed on at least the surface of the titanium film by an instantaneous annealing method. and a step of forming an upper wiring layer in contact with the titanium nitride film through a through hole in an interlayer insulating film on the titanium nitride film. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61275911A JPH0642514B2 (en) | 1986-11-18 | 1986-11-18 | Method for manufacturing multilayer wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61275911A JPH0642514B2 (en) | 1986-11-18 | 1986-11-18 | Method for manufacturing multilayer wiring structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63128646A true JPS63128646A (en) | 1988-06-01 |
| JPH0642514B2 JPH0642514B2 (en) | 1994-06-01 |
Family
ID=17562145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61275911A Expired - Lifetime JPH0642514B2 (en) | 1986-11-18 | 1986-11-18 | Method for manufacturing multilayer wiring structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642514B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05190551A (en) * | 1992-01-17 | 1993-07-30 | Yamaha Corp | Semiconductor device |
| US5880526A (en) * | 1996-04-15 | 1999-03-09 | Tokyo Electron Limited | Barrier metal layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59119854A (en) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | Semiconductor device |
| JPS60153121A (en) * | 1984-01-20 | 1985-08-12 | Nec Corp | Fabrication of semiconductor device |
| JPS61242039A (en) * | 1985-04-19 | 1986-10-28 | Nec Corp | Semiconductor device |
-
1986
- 1986-11-18 JP JP61275911A patent/JPH0642514B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59119854A (en) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | Semiconductor device |
| JPS60153121A (en) * | 1984-01-20 | 1985-08-12 | Nec Corp | Fabrication of semiconductor device |
| JPS61242039A (en) * | 1985-04-19 | 1986-10-28 | Nec Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05190551A (en) * | 1992-01-17 | 1993-07-30 | Yamaha Corp | Semiconductor device |
| US5880526A (en) * | 1996-04-15 | 1999-03-09 | Tokyo Electron Limited | Barrier metal layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0642514B2 (en) | 1994-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0631308B1 (en) | Method of controlling gate oxide thickness in the fabrication of semiconductor devices | |
| JPS63301548A (en) | Manufacture of semiconductor device | |
| US3918149A (en) | Al/Si metallization process | |
| JPH02235358A (en) | Connection method of multilayer wiring | |
| JPH01199456A (en) | Manufacture of semiconductor integrated circuit | |
| JPS63128646A (en) | Manufacture of multilayer interconnection structure | |
| JP2639052B2 (en) | Method for manufacturing semiconductor device | |
| JPH0740587B2 (en) | Method for manufacturing semiconductor device | |
| JPH0456453B2 (en) | ||
| JPH04196122A (en) | Manufacture of semiconductor device | |
| JPS6197825A (en) | Manufacture of semiconductor device | |
| JP2579993B2 (en) | Method for manufacturing semiconductor device | |
| JPH03185823A (en) | Manufacture of semiconductor device | |
| RU2198451C2 (en) | Method for insulating integrated-circuit components | |
| JPH07263447A (en) | Semiconductor device and its manufacture | |
| JPS61166143A (en) | Manufacture of semiconductor device | |
| JPS59152644A (en) | Forming method of multilayer interconnection | |
| JPH02215131A (en) | Manufacture of semiconductor device | |
| JP3315252B2 (en) | Method for manufacturing semiconductor device | |
| JPH0666312B2 (en) | Method for manufacturing semiconductor device | |
| JPS59108317A (en) | Forming method of electrode wiring | |
| JPH0337857B2 (en) | ||
| JPH07273114A (en) | Fabrication and planarization of semiconductor device | |
| JPH0527275B2 (en) | ||
| JPH0786395A (en) | Manufacture of semiconductor device |