JPH07273114A - Fabrication and planarization of semiconductor device - Google Patents

Abstract

PURPOSE:To achieve a desired planarization by forming a layer of fusible material and introducing impurities selectively into the fusible material layer thereby controlling the flow selectively. CONSTITUTION:A reflow retardation part B is formed within a reflow part A by differentiating the ion implantation. Only one kind of boron or phosphorus tons are implanted into the part A or no ion is implanted there. Selection between boron and phosphorus depends on the type, i.e., N type or P type, of a diffusion layer being formed thereat while contacting. On the other hand, both boron and phosphorus ions are implanted at the part B. A normal resist is employed in the masking for partitioning the A and B regions. This method realizes a desired planarization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method and a semiconductor device manufacturing method. INDUSTRIAL APPLICABILITY The present invention can be used for smoothing a base having a step using an impurity-containing meltable material, and can be used, for example, in the field of manufacturing various electronic materials. In addition, the method for manufacturing a semiconductor device of the present invention can be used for a manufacturing process of various semiconductor devices including an LSI having fine wiring and advanced integration.

[0002]

2. Description of the Related Art A planarization technique for forming an impurity-containing fusible material layer on a base having a step and heating it for planarization is
It is used in the field of semiconductor device manufacturing.

For example, in the case of using a multi-layer wiring technique in the manufacture of an LSI, flattening the underlying step to smooth the underlying area of the wiring as much as possible to prevent deterioration of the wiring coverage (coverage) at the step, and It realizes the ease of fine processing of wiring.

Conventionally, as this surface flattening technique, for example, B
Impurity-containing fusible material such as PSG (boron / phosphorus-containing silicate glass) film or AsSG (hisso-containing silicate glass) film is used, and the film is made to flow by softening by heat treatment to achieve flatness, thereby achieving the above-mentioned object. Has achieved. This process is generally called a reflow process.

However, the conventional surface smoothing technique using the impurity-containing meltable material as described above has a problem that desired flatness cannot always be achieved well.

That is, as shown in FIG. 3, B is formed on the base on which a step is formed by the lower layer wiring 2 formed on the substrate 1.
When the reflow process of forming the meltable material layer 3 of PSG or the like and flowing it is performed, the flowable meltable material flows too much, and the film thickness becomes thin at the shoulder portion of the wiring 2, that is, the portion C in the drawing.
As shown in the figure, in the C portion, the fusible material layer 3 becomes too thin as an interlayer insulating film, and a short circuit with the upper wiring is likely to occur. That is, when forming the upper wiring (for example, Al), Al-RI
When E is performed, the underlying wiring in this portion is exposed by a slight overetching, which causes a problem that a short circuit with the upper wiring is likely to occur. (In the figure, 1'is a LOCOS region for element isolation).

[0007]

SUMMARY OF THE INVENTION The present invention solves the above problems and prevents the desired flattening from being realized, for example, the occurrence of non-uniformity such as thinning of the impurity-containing meltable material in the shoulder portion of the underlying step. In addition, it is an object of the present invention to provide a planarization method capable of achieving desired desired planarization and a semiconductor device manufacturing method using the same.

[0008]

According to the invention of claim 1 of the present application, there is provided a step of forming an impurity-containing meltable material layer on a base having a step and heating the meltable material layer to flow. In the planarizing method, the method comprises the step of selectively controlling the flow by selectively introducing impurities into the fusible material layer after forming the fusible material layer. Therefore, this achieves the above object.

The invention according to claim 2 of the present application is the flattening method according to claim 1, wherein the selective introduction of the impurities is carried out simultaneously with the introduction of the impurities for the purpose of lowering the resistance. Thus, the above object is achieved.

The invention according to claim 3 of the present application is the flattening method according to claim 1 or 2, characterized in that the introduction of impurities is performed by ion implantation of impurities. Is achieved.

The invention according to claim 4 of the present application is the flattening method according to any one of claims 1 to 3, characterized in that the impurity-containing fusible material is glass containing impurities. The above object is achieved.

According to a fifth aspect of the present invention, there is provided a semiconductor device including a step of forming an impurity-containing meltable material layer on a base having a step, heating the meltable material layer, and flattening the meltable material layer. The method of manufacturing a semiconductor device according to claim 1, wherein after the meltable material layer is formed, the flow is selectively controlled by selectively introducing impurities into the meltable material layer. Therefore, the above object is achieved thereby.

In the invention of the present application, it is possible to separately introduce impurities such as ion implantation into the portion where the fluidity is desired to be used and the portion where the fluidity is desired to be controlled. As a result, the desired flattening can be achieved.

The present invention has been made based on the following findings by the present inventor. That is, the BP forming the fusible material layer 3
Boron (eg BF ₂ ⁺ , 50 keV, 3 × 10) in SG
¹⁵ cm ^{- 2)} and phosphorus (e.g. Phos ^+, 70ke
^{V, 1 × 10 15 cm -} 2) BPSG both (as-deposited)
Ion implantation into the flow (900 ° C, N ₂ in 20 mi
n), as shown in FIG. 4, the LOCOS region 1 ',
At the 1'shoulder, one or both BPSG
Compared to the case where no ion implantation is performed, the same heat treatment tends to make it difficult to flow and the surface flatness tends to deteriorate.
(Note that in such a case, the BPSG forming the fusible material layer 3
There is a problem that the side wall shape of the contact hole portion formed in the above becomes difficult to flow into the N ⁺ diffusion layer 5 and becomes nearly vertical, and the corner of the upper portion of the contact hole is apt to be sharp. )

As described above, when boron and phosphorus ions are simultaneously implanted on the doped fusible material layer such as silicon dioxide, a phenomenon may occur in which reflow does not flow.

When the reflow becomes difficult to flow as described above,
As shown in FIG. 4, when, for example, an Al wiring is formed as the upper wiring 4, the coverage (coverage) of the Al wiring in the contact portion is insufficient. (In this case, the problem is that Al in the contact portion is easily broken due to electromigration, which is a reliability problem.)

Therefore, if the above-mentioned knowledge that the fluidity of the meltable material can be controlled by the ion implantation, the fluidity can be suppressed by performing the ion implantation simultaneously as described above, and based on this. Then, by selectively controlling the introduction of impurities, the fluidity can be controlled as desired.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. However, it should be understood that the present invention is not limited to the illustrated embodiments.

Example 1 This example embodies the present invention in a manufacturing process of a semiconductor device, and in particular, a step formed by a base wiring is flattened by using BPSG as an impurity-containing meltable material. Then, it is applied when an upper layer wiring is formed thereon to form a contact portion or the like.

The impurity-containing meltable material BPSG used in this embodiment is formed by atmospheric pressure CVD at 380 ° C. and has a phosphorus concentration of 6.6 to 7.2 wt% and a boron concentration of 2.2 to 2. 0.8 wt%.

Referring to FIG. In this embodiment, the substrate 1
Lower layer wiring 2 (for example, poly-Si) on (here, Si substrate)
Layer, or a wiring portion such as a polycide layer) is formed to form an underlayer having a step, and the impurity-containing meltable material layer 3 (BPSG layer) is formed on this underlayer,
In the case of heating to flow the molten material layer 3,
After forming the meltable material layer 3, selectively introducing impurities into the meltable material layer 3 (here, ion implantation)
To selectively control the flow.

This embodiment will be described in more detail with reference to FIG. 1. In this embodiment, as shown in FIG. 1, a portion A where reflow is desired to flow and a portion B where reflow is suppressed to make flow difficult. Regions are created using ion implantation. That is,
In the portion A shown in the drawing, the ion implantation is made of only one type of boron or phosphorus, or no ion implantation is performed at all. This ensures liquidity.

The proper use of boron or phosphorus is
It is determined depending on whether the diffusion layer is N-type or P-type when a contact is formed in this portion.

On the other hand, in the portion B shown in the drawing, ion implantation is carried out for both types of boron and phosphorus.

The areas A and B are separately formed by masking using a normal photoresist.

In the present embodiment, the selective introduction of impurities is performed at the same time as the introduction of impurities, which is generally performed for the purpose of lowering the resistance during the reflow process, and the process is simplified.

In the present embodiment, the ion implantation was performed separately by combining boron and phosphorus, but the type of ion implantation is not limited to the combination of boron and phosphorus, and other elements may be appropriately used. Good. Impurity introducing means other than ion implantation may be used.

The dose of ion implantation should be optimized according to the desired fluidity and the suppression of fluidity. Generally, the dose of ion implantation should be 10 ¹¹ cm ^-2 or more. , More practically, 10 ¹⁴ to 10 ¹⁶ cm ^-2
It is preferable to set the dose amount to

As described above, according to this embodiment, in the surface smoothing process using the impurity-containing silicon dioxide (impurity-containing glass or the like) as the meltable material, the meltable material is desired not to flow in the desired region. Area (A and B in the figure)
Part) can be set freely, and thus the degree of use of the smoothing process using a meltable material can be expanded.

Further, in such a smoothing step, it is possible to prevent thinning of the shoulder portion of the underlying step (wiring portion or the like).

Further, in this embodiment, since the ion implantation specifically performed for controlling the fluidity is carried out at the same time as the ion implantation process of boron, phosphorus or the like which is usually used for reducing the contact resistance at the time of reflow, the ion implantation region is used. It only changes the setting of and does not increase the number of processes.

Embodiment 2 This embodiment is an example in which ion implantation implantation is optimized in order to be most effective. Reference is made to FIG. 2 (corresponding to the portion indicated by reference numeral II in FIG. 1).

In the description of the first embodiment, the areas A and B are separated as described above. In this embodiment, x and x in FIG.
Requires adjustment of the length of x '. x and x ′ are portions corresponding to the shoulders of the lower layer wiring 2 forming the underlying step, and b ′.
Is a portion corresponding to the central portion of the lower layer wiring 2. That is, it is necessary to adjust where to set the boundary between A and B with respect to the position of the shoulder portion of the wiring. This is because the shape after reflow is such that the step (thickness) of the wiring and the proximity to the wiring. This is because it depends on the pattern shape in the lateral direction, such as the distance from the wiring to be formed, the shape of other underlying layers, and the like.

That is, in the present embodiment, the region B, which is the region where reflow is controlled, is set to b or b when b = b '+ x + x' as shown in the figure, where x and x'are shoulders of the step. b'is optimized and set.

In this embodiment, the flattening could be further improved.

[0036]

According to the flattening method and the semiconductor device manufacturing method of the present invention, it becomes possible to selectively control the meltability of the impurity-containing meltable material layer, so that nonuniformity occurs. Can be prevented, and the desired good planarization can be achieved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram illustrating a first embodiment with a sectional view.

FIG. 2 is an explanatory diagram illustrating a second embodiment with a sectional view.

FIG. 3 is a diagram showing a conventional technique and its problems.

FIG. 4 is a diagram showing background art.

[Explanation of symbols]

 1 Substrate (base) 2 Lower layer wiring (base) 3 Impurity-containing meltable material layer (BPSG layer)

Claims (5)

[Claims] 1. A flattening method comprising a step of forming an impurity-containing fusible material layer on a base having a step and heating the fusible material layer to flow therethrough, after forming the fusible material layer. A planarization method characterized in that the flow is selectively controlled by selectively introducing impurities into the meltable material layer. 2. The planarization method according to claim 1, wherein the selective introduction of the impurities is performed simultaneously with the introduction of the impurities for the purpose of lowering the resistance. 3. The planarization method according to claim 1, wherein the impurity is introduced by ion implantation of the impurity. 4. The flattening method according to claim 1, wherein the impurity-containing meltable material is impurity-containing glass. 5. A method of manufacturing a semiconductor device, comprising: a step of forming an impurity-containing fusible material layer on a base having a step and heating the meltable material layer to flatten the fusible material layer. A method for manufacturing a semiconductor device, characterized in that after the material layer is formed, impurities are selectively introduced into the meltable material layer to selectively control the flow.