JPH07202011A - Dual gate cmos type semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize high level of integration, and restrain diffusion of impurities in a gate electrode without increasing the number of steps of manufacturing. CONSTITUTION:After N-type impurities 17 are introduced into a polysilicon film 6 in a region which turns to the gate of an NMOSFET, and P-type impurities 18 are introduced into the polysilicon film 6 in a region which turns to the gate of a PMOSFET, a titanium silicide film 27 is formed. Nitrogen atoms 21 are introduced into the titanium silicide film 27, and annealing is performed for activating the nitrogen atoms 21. After that, the titanium silicide film 27, the polysilicon film 6, and a gate oxide film 5 are patterned and turned into polycide gate electrodes 31N, 31P.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a PMOS 0FET having a P-type polysilicon gate electrode as a gate electrode and an NMOS.
A dual-gate CMOS semiconductor device having an N-type polysilicon gate electrode as a gate electrode of 0FET, and a refractory metal silicide film for connecting both polysilicon gate electrodes is laminated on both polysilicon gate electrodes and the same. The present invention relates to a manufacturing method.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional dual gate CMOS type semiconductor device together with its manufacturing method. (A) A P-type well 2 and an N-type well 3 are formed on one main surface of a silicon substrate 1, and a field oxide film 4 is formed in an element isolation region.
To form.

(B) A gate oxide film 5 is formed on the surfaces of the P-type well 2 and the N-type well 3. A polysilicon film 6 is formed on the gate oxide film 5 and the field oxide film 4. A resist pattern having an opening in a region to be the gate of the NMOSFET is formed thereon, and the N-type impurity 17 is introduced into the polysilicon film 6 by the ion implantation method using the resist pattern as a mask. After removing the resist pattern, a resist pattern having an opening in a region to be the gate of the PMOSFET is formed again by the lithography method, and the P-type impurity 18 is introduced into the polysilicon film 6 by the ion implantation method using the resist pattern as a mask. . After removing the resist pattern, a refractory metal silicide film 7 such as a titanium silicide film is formed on the polysilicon film 6.

(C) A resist pattern is formed by a lithography method, and a refractory metal silicide pattern 8, polysilicon gate electrode patterns 9N and 9P, and a gate oxide film pattern 10 are formed by a dry etching method using the resist pattern as a mask. Gate electrodes 11N, 11P
And Ions are implanted so that the NMOSFET and the PMOSFET have the LDD structure, and the N-type low-concentration impurity region 12 and the P-type low-concentration impurity region 13 are formed.

(D) A silicon oxide film is formed on the entire surface, and the silicon oxide film is etched back by an anisotropic dry etching method to form sidewalls 14 on the side surfaces of the polycide gate electrode. Sidewall 14
Ion implantation is performed to form a source region and a drain region using the gate electrode formed with
Type high concentration impurity region 15 and P type high concentration impurity region 16
To form. Then, heat treatment is performed to activate the implanted ions. After that, an interlayer insulating film is formed according to a normal process, a contact hole is opened, and a metal wiring is formed.

[0006]

FIG. 2 (D) shows the problem to be solved by the invention.
2 shows a state in which the semiconductor device of (3) is cut in the direction perpendicular to the plane of the drawing at the gate electrode position. (A) is the state before heat treatment, and NMO
The N-type impurity 17 is introduced into the polysilicon gate electrode 9N of the SFET, and the P-type impurity 18 is introduced into the polysilicon gate electrode 9P of the PMOSFET.
The N-type impurity 17 is diffused into the refractory metal silicide layer 8 by the thermal process after the impurities are introduced into the polysilicon gate electrodes 9N and 9P, and diffuses inside the refractory metal silicide layer 8 toward the PMOSFET. The P-type impurity 18 also moves and diffuses into the refractory metal silicide layer 8 and diffuses inside the refractory metal silicide layer 8 to form an NMOSFET.
Direction, and as shown in FIG. 2B, the NMO
P-type impurity 1 is added to the polysilicon gate electrode 9N of the SFET.
8 is mixed, and the N-type impurity 17 is mixed into the polysilicon gate electrode 9P of the PMOSFET. As a result, the work functions of the polysilicon gate electrodes 9N and 9P change and the MOS
There arises a problem that the threshold voltage of the FET fluctuates.

As described above, in order to prevent impurities from diffusing in the refractory metal silicide layer and mutually diffusing, the distance S between the PMOSFET and the NMOSFET shown in FIG.
Is longer than the diffusion length of the impurities 17 and 18. In FIG. 3, 19 represents the active region of the NMOSFET and 20 represents the active region of the PMOSFET. However, if the distance S between both MOSFETs is increased, high integration cannot be realized.

As another method for avoiding diffusion of impurities into the refractory metal silicide layer and mutual diffusion, a refractory metal silicide layer formed on the polysilicon gate electrode is physically formed between the PMOSFET and the NMOSFET. A method of selectively separating is also proposed (Japanese Patent Laid-Open No. 23965/1990).
No. 6, gazette and 3-203366 gazette). However, that method increases the steps of lithography and etching,
There is a problem that the number of steps becomes long as a manufacturing process.

The present invention provides an element structure and a manufacturing method which prevent impurities from diffusing in a refractory metal silicide layer and mutually diffusing, achieve high integration, and do not significantly increase the manufacturing process. It is intended.

[0010]

In the dual gate CMOS type semiconductor device of the present invention, the refractory metal silicide layer formed on the upper layer of the gate electrode contains atoms that hinder the diffusion of impurities. The refractory metal silicide layer is one of titanium silicide, tungsten silicide, molybdenum silicide or tantalum silicide.

Atoms contained in the refractory metal silicide layer and preventing diffusion of impurities are electrically inactive atoms. A preferred example of the electrically inactive atom is a nitrogen atom or an indium atom. In a preferred example, the region in the refractory metal silicide layer where the atoms that prevent diffusion of impurities are present is in contact with the interface between the refractory metal silicide layer and the polysilicon gate electrode and has a thickness of at least 300Å. The concentration of the atoms that hinder the diffusion of impurities in the region where the atoms that hinder the diffusion of impurities exist in the refractory metal silicide layer is 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ .

In the manufacturing method of the present invention, the element region is formed, the gate oxide film is formed, the polysilicon film is deposited, and the P-type impurity is introduced into the polysilicon film in the region to be the gate of the PMOSFET. A step of introducing an N-type impurity into the polysilicon film in the region to be the gate of the NMOSFET, a step of forming a refractory metal silicide film on the polysilicon film thereafter, and an ion implantation method for the refractory metal silicide film. A step of introducing a nitrogen atom or an indium atom, a heat treatment step for activating the introduced nitrogen atom or an indium atom, and then patterning the refractory metal silicide film and the underlying polysilicon film into a gate electrode shape. And a process. In a preferred example of this manufacturing method, the heat treatment step for activating the introduced nitrogen atom or indium atom is RTA (Rapid
Thermal Anealing) method.

[0013]

In the CMOS type semiconductor device of the present invention, since electrically inactive atoms such as nitrogen atoms and indium atoms are introduced into the refractory metal silicide layer formed on the polysilicon gate electrode, Impurities such as boron and boron are suppressed from mutually diffusing into the polysilicon gate electrode through the refractory metal silicide layer, and as a result, changes in the work function of the polysilicon gate electrode are suppressed, and threshold fluctuations are suppressed. To be

[0014]

【Example】

(Embodiment 1) FIG. 4 shows a first embodiment together with a manufacturing method. (A) A P-type well 2 and an N-type well 3 are formed on one main surface of a silicon substrate 1 by an ion implantation method and a thermal diffusion method, and a field oxidation having a thickness of about 5000Å is formed in an element isolation region by a local oxidation method. The film 4 is formed.

(B) A gate oxide film 5 having a thickness of about 75 Å is formed on the surfaces of the P-type well 2 and the N-type well 3 by a thermal oxidation method. A polysilicon film 6 is formed on the gate oxide film 5 and the field oxide film 4 by the LPCVD method by about 1000 Å.
To a film thickness. Then, by the lithography method, N
A resist pattern having an opening in a region which will be a gate of the MOSFET is formed, and the N-type impurity 1 is used as a mask.
Arsenic or phosphorus is introduced into the polysilicon film 6 as an ion implantation method 7. After removing the resist pattern, the PMOSFET is again formed by the lithography method.
A resist pattern having an opening in a region to be a gate is formed, and using it as a mask, boron or BF ₂ as a P-type impurity 18 is introduced into the polysilicon film 6 by an ion implantation method.

After removing the resist pattern, a refractory metal silicide film of any one of a titanium silicide film, a tungsten silicide film, a molybdenum silicide film or a tantalum silicide film is formed on the polysilicon film 6 by a sputtering method or an LPCVD method. 27 to 600-1500
Form a film with a thickness of Å. When this film formation is a sputtering method, nitrogen gas is mixed in the sputtering atmosphere and the nitrogen atoms 21 are introduced into the refractory metal silicide film 27 by a reactive sputtering method, or in the case of the LPCVD method, nitrogen is added to the process gas. Nitrogen atoms 21 are introduced into the refractory metal silicide film 27 by mixing gas. Then, in order to activate the nitrogen atoms 21 introduced into the refractory metal silicide film 27, annealing is performed at 850 ° C. for 30 minutes by a furnace annealing method.

(C) A resist pattern is formed by a lithography method, and the refractory metal silicide pattern 28, polysilicon gate electrode patterns 9N and 9P, and gate oxide film pattern 10 are formed by a dry etching method using the resist pattern as a mask. Gate electrodes 31N, 31
Let P. Ions are implanted so that the NMOSFET and the PMOSFET have the LDD structure, and the N-type low-concentration impurity region 12 and the P-type low-concentration impurity region 13 are formed.

(D) LPCVD of silicon oxide film on the entire surface
Film is formed to a thickness of about 1200 Å by the method, and the silicon oxide film is etched back by the anisotropic dry etching method to form the sidewall 14 on the side surface of the polycide gate electrode. Ion implantation is performed to form the N-type high-concentration impurity region 15 and the P-type high-concentration impurity region 16 in order to form the source region and the drain region using the gate electrode with the sidewalls 14 as a mask. Then, heat treatment is performed to activate the implanted ions. After that, an interlayer insulating film is formed according to a normal process, a contact hole is opened, and a metal wiring is formed.

As shown in FIG. 4D, one embodiment of the semiconductor device is one in which nitrogen atoms are introduced into the refractory metal silicide layer 28 formed on the polysilicon gate electrodes 9N and 9P. is there.

When the titanium silicide film is used as the refractory metal silicide film, the tungsten silicide film is used, the molybdenum silicide film is used, and the tantalum silicide film is used, the NMOSFET and the PMOSFET are used. NMOSFET and PMOSFE within the range where the threshold voltage does not fluctuate
The results of comparing the distance S between T (see FIG. 3) between the embodiment in which nitrogen atoms are introduced into the refractory metal silicide and the conventional CMOS which does not contain atoms such as nitrogen that prevent diffusion of impurities are shown in Table 1. Shown in.

[0021]

[Table 1] Nitrogen is mixed in the refractory metal silicide layer From the results in Table 1, NMOSFET and PMO according to the present invention
The distance S between the SFETs can be shortened.

(Embodiment 2) Nitrogen atoms are used in Embodiment 1 as atoms that hinder the diffusion of impurities. In the second embodiment, the nitrogen atoms are replaced with indium atoms. This example is different in that the refractory metal silicide layer 28 shown in FIG. 4D contains indium atoms.

The manufacturing method is the same as that shown in FIG. 4, but in order to introduce indium into the refractory metal silicide layer 28, ion implantation is used to indium atoms at an acceleration energy of 30 to 200 KeV and a dose. Amount 1 × 10
¹³ to 1 × 10 ¹⁵ / cm ^{2 is} introduced. In order to activate the introduced indium atoms, annealing in a furnace is performed at 850 ° C. for 30 minutes as in the first embodiment. The other steps are the same as those of the first embodiment.

In this embodiment, indium atoms are introduced into the refractory metal silicide, a titanium silicide film is used as the refractory metal silicide, a tungsten silicide film is used, a molybdenum silicide film is used, and For each of the cases where the tantalum silicide film is used, NMOSFET and P
The distance S (see FIG. 3) between the MOSFETs is compared between the embodiment in which indium atoms are introduced into the refractory metal silicide and the conventional CMOS which does not contain atoms such as indium that prevent diffusion of impurities. Shown in.

[0025]

[Table 2] Indium mixed in the refractory metal silicide layer

From the results shown in Table 2, the distance S between the NMOSFET and the PMOSFET can be shortened even when indium atoms are introduced into the refractory metal silicide layer.

(Embodiment 3) FIG. 4D shows that the refractory metal silicide layer 28 has nitrogen or indium atoms distributed throughout the film thickness direction. On the other hand, in the third embodiment, the refractory metal silicide layer 28
Over the thickness direction of the polysilicon gate electrode 9N,
An example is shown in which the thickness of the region into which nitrogen or indium is introduced is changed from the boundary with 9P.

Explaining the manufacturing method with reference to FIG. 4, the step of introducing nitrogen or indium atoms into the refractory metal silicide layer 27 in the step (B) is different from that of the first and second embodiments. In the third embodiment, when the tungsten silicide layer 27 is formed by using the LPCVD method, nitrogen gas is mixed so that the concentration of nitrogen atoms 21 in the tungsten silicide layer becomes 1 × 10 ¹⁷ to 1 × 10 ²¹ / cm ³ . While adjusting so that the film thickness of the region where the nitrogen atoms 21 are mixed is 1
The film is formed to have a thickness of 00 to 800Å. After that, the introduction of nitrogen gas is stopped and the tungsten silicide layer 27 is formed so that the total film thickness becomes about 1000 Å.

In the other method of the step (B), when indium atoms are introduced as atoms for suppressing the diffusion of impurities, the tungsten silicide layer 27 has a thickness of about 1000 Å.
After the film is formed to a thickness of 1, the ion implantation method is used to introduce indium atoms with an acceleration energy of 30 to 200 KeV and a dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² . At this time, the acceleration energy and the dose amount are set so that the thickness of the region where the indium atoms exist becomes a desired thickness from the boundary with the polysilicon layer 6. Also in this case, in order to activate the nitrogen atoms or the indium atoms introduced into the tungsten silicide layer 27, annealing is performed at 850 ° C. for 30 minutes by the furnace annealing method.

In the third embodiment, when the thickness of the nitrogen atom-containing layer in the tungsten silicide layer 27 is changed in the range of 100 to 800 Å, the NMOS FE and the NMOSFET are not changed in the threshold voltage in the range.
The result of measuring the minimum distance S between T and PMOSFET is shown in FIG. The concentration of nitrogen atoms in the nitrogen atom-containing layer in Example 3 was set to 1 × 10 ¹⁹ / cm ³ . From the result of FIG. 5, when the thickness of the nitrogen atom-containing layer becomes 300 Å or more, N
The distance S between the MOSFET and the PMOSFET can be shortened.

In this embodiment, when the atoms introduced into the tungsten silicide layer are changed to nitrogen atoms to become indium atoms, the thickness of the indium atom-containing layer is 100-.
NMOSFET and PMO when changed in the range of 800Å
Within the range where the threshold voltage of the SFET does not change, N
The result of measuring the minimum distance S between the MOSFET and the PMOSFET is shown in FIG. The concentration of indium atoms in the indium atom-containing layer in this example was also set to 1 × 10 ¹⁹ / cm ³ .

From the result of FIG. 6, when the thickness of the indium atom-containing layer becomes 300 Å or more, the NMOSFET and the PMO are
The distance S between the SFETs can be shortened. The same results as in FIGS. 5 and 6 were obtained when titanium silicide, molybdenum silicide or tantalum silicide was used instead of the tungsten silicide in the refractory metal silicide layer.

(Embodiment 4) As in Embodiment 3, except that the thickness of the nitrogen atom-containing layer in the tungsten silicide layer 1000Å is set to 500Å and the concentration of nitrogen atoms is 1 × 10.
NMO when changing in the range of ¹⁷ to 1 × 10 ²¹ / cm ^3.
FIG. 7 shows the minimum distance S between the NMOSFET and the PMOSFET and the sheet resistance of the polycide gate electrode when the threshold voltages of the SFET and the PMOSFET do not change. From the result of FIG. 7, the concentration of nitrogen atoms is 1 × 1.
By setting 0 ¹⁸ to 1 × 10 ²⁰ / cm ³ , the NMOS
The minimum distance S between the FET and the PMOSFET can be shortened, and the sheet resistance of the polycide gate electrode can be lowered.

The thickness of the layer containing the atoms in the tungsten silicide layer 1000Å which prevents the diffusion of impurities from the boundary with the polysilicon layer is set to 500Å, and indium atoms are used instead of nitrogen as the contained atoms. FIG. 8 shows the result in the case of performing the same as above. FIG. 8 also shows the same results as in FIG. 7, in which the concentration of indium atoms is 1 × 1.
By setting 0 ¹⁸ to 1 × 10 ²⁰ / cm ³ , the NMOS
The minimum distance S between the FET and the PMOSFET can be shortened, and the sheet resistance of the polycide gate electrode can be lowered. Even when the refractory metal silicide layer is changed to tungsten silicide to be titanium silicide, molybdenum silicide or tantalum silicide,
The same results as in FIGS. 7 and 8 were obtained.

(Embodiment 5) Nitrogen atoms are introduced into the refractory metal silicide layer 27 in the same manner as the embodiment of FIG. 4, but a case where an ion implantation method is used as the introduction method will be described. In the process corresponding to FIG. 4B, the sputtering method or the LP
A tungsten silicide film of 600 to
Form a film with a thickness of 1500Å. Nitrogen atoms are accelerated into the tungsten silicide film by an ion implantation method at an acceleration energy of 30 to 200 KeV and a dose amount of 1 × 10 ¹³ to 1 × 1.
0 ¹⁵ / cm ^{2 is} introduced. In order to activate the introduced nitrogen atoms, annealing is performed in a furnace at 850 ° C. for 30 minutes, or more preferably by RTA at 1050 ° C. for 20 seconds in a nitrogen or argon atmosphere.
As described above, the sheet resistance of the polycide gate electrode is compared between the case where nitrogen atoms are introduced into the tungsten silicide film by using the ion implantation method and the case where nitrogen gas is mixed into the tungsten silicide film by mixing the film formation atmosphere. FIG. 9 shows the result of evaluation of the variation and the variation.

From the results shown in FIG. 9, it can be seen that the use of the ion implantation method results in a smaller variation in sheet resistance and is a more preferable fabrication method. When titanium silicide, molybdenum silicide, or tantalum silicide was used instead of tungsten silicide, the same results as in FIG. 9 were obtained.

NMOSFETs were prepared by annealing nitrogen atoms introduced by the ion implantation method in a furnace annealing method at 850 ° C. for 30 minutes and by RTA method in a nitrogen atmosphere at 1050 ° C. for 20 seconds. And the minimum distance S between the NMOSFET and the PMOSFET when the threshold voltage of the PMOSFET does not change.
As a result of the comparison of S in the furnace annealing method, S = 0.6 μm,
In the case of the RTA method, S = 0.5 μm. RTA
It is considered that the annealing is performed at a higher temperature and in a shorter time, so that diffusion of impurities can be suppressed and S can be shortened.

[0038]

According to the present invention, nitrogen atoms or indium atoms are introduced into the refractory metal silicide layer formed on the polysilicon gate electrode as atoms that hinder the diffusion of impurities. NMOSFET
The distance between PNOSFET and PNOSFET can be further shortened, which is advantageous for high integration. In the manufacturing method of the present invention, if the atoms to be introduced into the refractory metal silicide film are introduced by the ion implantation method, variations in the sheet resistance of the polycide gate electrode can be suppressed, and the uniformity can be improved. Further, according to the manufacturing method of the present invention, if the atoms introduced into the refractory metal silicide film are activated by the RTA method, the diffusion of impurities can be suppressed. The minimum distance S between the PMOSFET and the PMOSFET can be shortened, which is more advantageous for high integration.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing a method of manufacturing a conventional semiconductor device having a polycide gate electrode, which is taken along line AA ′ of FIG.
It corresponds to the state of cutting at the line position.

FIG. 2 is a cross-sectional view illustrating a problem of a conventional semiconductor device, which corresponds to a state cut along the line BB ′ in FIG.

FIG. 3 is a schematic plan view showing a CMOS semiconductor device.

FIG. 4 is a cross-sectional view showing an embodiment of the present invention together with a manufacturing method, and corresponds to a state cut along the line AA ′ in FIG.

FIG. 5 shows NMOSFET and PM within a range in which the thickness of the nitrogen atom-containing layer in the tungsten silicide layer and the threshold voltage of NMOSFET and PMOSFET do not change.
It is a figure which shows the relationship of the minimum distance S between OSFETs.

FIG. 6 is an NMOSFET in a range in which the thickness of the indium atom-containing layer in the tungsten silicide layer and the threshold voltage of the NMOSFET and PMOSFET do not change.
It is a figure which shows the relationship of the minimum distance S between PMOSFET and PMOSFET.

FIG. 7 shows the concentration of nitrogen atoms in the tungsten silicide layer and the minimum distance S between NMOSFET and PMOSFET.
FIG. 3 is a diagram showing the relationship between the sheet resistance of the polycide gate electrode and FIG.

FIG. 8 is a diagram showing the relationship between the concentration of indium atoms in the tungsten silicide layer, the minimum distance S between the NMOSFET and the PMOSFET, and the sheet resistance of the polycide gate electrode.

FIG. 9 is a diagram in which variations in sheet resistance are measured by comparing an ion implantation method as a method of introducing nitrogen atoms into a tungsten silicide layer and a method of introducing nitrogen atoms during film formation.

[Explanation of symbols]

 1 Silicon substrate 5 Gate oxide film 6 Polysilicon film 9N, 9P Polysilicon gate electrode 27 Refractory metal silicide film 21 Nitrogen atom 28 Refractory metal silicide layer 31N, 31P Polycide gate electrode

Claims (9)

[Claims] 1. A PMOS0FET has a P-type polysilicon gate electrode as a gate electrode, an NMOS0FET has a N-type polysilicon gate electrode as a gate electrode, and both polysilicon gate electrodes have both polysilicon gate electrodes. C in which a refractory metal silicide layer for connection is laminated
A CMOS type semiconductor device, wherein the refractory metal silicide layer contains atoms that prevent diffusion of impurities. 2. The CMOS semiconductor device according to claim 1, wherein the refractory metal silicide layer is any one of titanium silicide, tungsten silicide, molybdenum silicide, and tantalum silicide. 3. The CMOS semiconductor device according to claim 1, wherein the atoms that prevent diffusion of impurities are electrically inactive atoms. 4. The CMOS semiconductor device according to claim 3, wherein the electrically inactive atom is a nitrogen atom. 5. The CMOS type semiconductor device according to claim 3, wherein the electrically inactive atom is an indium atom. 6. A region of the refractory metal silicide layer in which atoms that prevent diffusion of impurities are present is in contact with the interface between the refractory metal silicide layer and the polysilicon gate electrode, and has a thickness of at least 300Å. The CMOS semiconductor device according to 3, 4, or 5. 7. The concentration of the atoms that prevent the diffusion of impurities in the region where the atoms that prevent the diffusion of impurities exist in the refractory metal silicide layer is 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. 6. The CMOS semiconductor device according to item 6. 8. A device region is formed, a gate oxide film is formed, and then a polysilicon film is deposited. A P-type impurity is introduced into the polysilicon film in the region to be the gate of the PMOSFET to form the gate of the NMOSFET. Of the N-type impurity into the polysilicon film in the region to be formed, a step of forming a refractory metal silicide film on the polysilicon film thereafter, and a step of forming nitrogen atoms or nitrogen atoms in the refractory metal silicide film by an ion implantation method. Introducing an indium atom,
A heat treatment step for activating the introduced nitrogen atoms or indium atoms, and thereafter, patterning the refractory metal silicide film and the polysilicon film thereunder into a gate electrode shape. Method of manufacturing CMOS semiconductor device. 9. The method for manufacturing a CMOS semiconductor device according to claim 8, wherein the heat treatment step is an RTA method.