JPS62188245A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the improvement in quality and yield of semiconductor devices by forming openings for electrical connection of a wiring region of a semiconductor device and a wiring material shallowly by eliminating conventional deep openings which reach a semiconductor substrate. CONSTITUTION:An intermediate wiring material 9 is formed on a connection window part 8, i.e., a connection part of a source 3 and a drain 4 and on a surface of an interlaminar insulating film 2 formed on the source 3 and drain 4 side to the same thickness as that of a gate material, i.e., polysilicon in this embodiment. Next, an interlaminar insulating film 10 is formed on the surface of the interlaminar insulating film 2 and the intermediate wiring material 9 and the surface is made even. To electrically connect the source 3 and the drain 4 to a wiring material through the intermediate wiring material 9, a part of the interlaminar insulating film 10 is removed to form openings 11 down to the intermediate wiring material 9. Similarly, a part of the interlaminar insulating films 2 and 10 is removed to form openings 12 down to the surface of a gate 5 in order to connect the gate 5 to the wiring material and the depths of the openings 11 and 12 are roughly the same. Then, the wiring material is formed in the openings 11 and 12.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Application The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure.

(b) Prior Art Conventionally, in the manufacture of semiconductor integrated circuits (engineering G) having a multilayer wiring structure, the presence of steep step portions would lead to disconnections when upper wiring was applied to the step portions, so field effect transistors A planarization technique that smoothes out the unevenness of the underlying surface caused by the formation of wires, wiring, etc. is indispensable.

FIG. 2 shows a cross-sectional structure of a MOS type field effect transistor. In FIG. 2, a field oxide film 22 is formed on a Si substrate 21. As shown in FIG. Then, impurities are implanted into the surface of the Si substrate 11 to form a source 23 and a drain 24, and a gate 25 made of polycrystalline Si is formed on the field oxide film 22 in the center of FIG.
is formed. Thereafter, an interlayer insulating film 26 is formed over the entire surface in order to insulate the source, gate, and drain, and to flatten the surface unevenness that occurred during the manufacturing of the field effect transistor.

(Problems to be Solved by this Invention) After manufacturing the above-described field effect transistor and planarizing it with the interlayer insulating film 26, the connections between the source 23, drain 24, and gate 25 of the field effect transistor and the wiring material are In order to do this, it is necessary to open a hole in the interlayer insulating film 26. By the way, as shown in FIG.
depth A of the opening leading to the drain 24, depth A'n 1t of the opening leading to the drain 24, and depth hG of the opening leading to the gate 25.
becomes deeper than When the depths A, , and AD of the openings are deep, the slope of the walls of the openings becomes steep. The wiring material is not formed well, and as a result, the coverage of the wiring material in the opening portion of the Si substrate 1 may be poor, leading to a risk of wire breakage, resulting in a problem of deterioration of the quality of the integrated circuit and a reduction in yield. Furthermore, the thickness of the interlayer insulating film 26, that is, the depth of the opening, hD, does not change much even as the integrated circuit becomes finer, so the more finely integrated the circuit becomes, the more difficult it is for wiring material to form on the wall of the hole. Therefore, there was a drawback that the above-mentioned problem of coverage became more serious.

An object of the present invention is to provide a method for manufacturing a semiconductor device in which when a hole is formed for connecting a wiring area of a semiconductor device and a wiring material, the wiring material covers the opening with good coverage. .

B) Means for Solving the Problems This invention provides a step of forming a first interlayer insulating film on a wiring region formed on a semiconductor substrate, and a step of forming a first interlayer insulating film on a portion corresponding to the wiring region. forming a connection window by removing an interlayer insulating film; forming an intermediate wiring material in a wiring area where the connection window is formed and a part of the first interlayer insulating film; A second layer is formed on the surface of the interlayer insulating film and the intermediate wiring material.
forming and planarizing an interlayer insulating film, in order to electrically connect the wiring region to a wiring material via the intermediate wiring material, a part of the second interlayer insulating film is removed; The method includes the following steps: a step of opening a hole to the surface of the intermediate wiring material;

(E) The hole made in the interlayer insulating film to electrically connect the wiring area of the functional semiconductor device and the wiring material may be deep enough to reach the intermediate wiring material, and the connection is made through the intermediate wiring material. It is done. Therefore, since the depth of the opening can be made shallow, when the wiring material is formed in the opening, the coverage of the wiring material is improved.

(F) Embodiment Hereinafter, a preferred embodiment in which the present invention is applied to a MOS field effect transistor will be described. FIGS. 1A to 6) show the manufacturing process of the field effect transistor of the present invention. In FIG. 1 (8), the Si substrate 1
There is a field oxide film 2 on the top to prevent parasitic effects.
,000 thick, source 3 and drain 4
Each surface is etched and impurities (ions) are implanted. Then, at ℃, polycrystalline St is formed on the central field oxide film 2.
As shown in FIG.
0 surface, that is, the surfaces of the source 3, drain 4 and gate 5, and the surface of the field oxide film 2.
is deposited to a thickness of approximately 2,000 mm. Next, as shown in FIG. 1C, in order to form connection windows in the source 3 and drain 4 by photolithography, a resist pattern of a resist film 7 is formed on the interlayer insulating film 2, and mask alignment is performed. Perform exposure.

Next, as shown in FIG. 1(D), a connection window 8 is formed by etching, and the resist film 7 is removed. Next, the first
As shown in Figure (E), an intermediate wiring material 9 is formed on the connection window 8 portion, in other words, on the connection portion between the source 3 and drain 4 and on the surface of the interlayer insulating film 2 formed on the source 3 and drain 4 side. Gate material, in this example approximately 5,000 ml, same as polycrystalline S1
It is formed with a thickness of 0. This intermediate wiring material 9 is made of the same material as the gate material or a silicon side such as TiSi2. Next, as shown in FIG. 1F, an interlayer insulating film 10 is formed on the surfaces of the intermediate wiring material 9 and the interlayer insulating film 20, and the surfaces are planarized. The interlayer insulating film IO may be made of the same material as the interlayer insulating film 2, for example, SiO2, or may be made of a different material. Next, as shown in FIG. 1(G), in order to electrically connect the source 3 and drain 4 to a wiring material (not shown) via an intermediate wiring material 9, an interlayer insulating film 10 is formed. A portion is removed and a hole 11 is made up to the intermediate wiring material 9.

Similarly, in order to connect the gate 5 and the wiring material, a part of the interlayer insulating film 2,100 is removed and an opening 12 is formed up to the surface of the gate 50.
do. The depths of the openings 11 and 12 are approximately equal. Next, wiring material is formed in the openings 11.12.

According to the method for manufacturing a field effect transistor described above, the opening 11 for connecting the wiring material to the source 3 and the drain 4 is formed.
Is the depth of intermediate wiring material 9? : The depth of the hole 12 can be made shallow to connect the wiring material to the gate.

(g) Effects This invention provides a semiconductor device having a multilayer wiring structure such as an integrated circuit, in which an opening formed for electrical connection between a wiring area of the semiconductor device and a wiring material is replaced with a conventional semiconductor substrate. Because it eliminates deep holes that lead to
The coverage of the wiring material in the opening can be greatly improved, and therefore the quality and yield of semiconductor devices can be improved.

[Brief explanation of drawings]

FIGS. 1A to 1G are cross-sectional views showing the manufacturing process of an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing an example of a conventional semiconductor device. 1... Si substrate, 3... Source, 4
・・・ Drain, 5... Gate, 6
．． 10... Interlayer insulating film, 8... Connection window, 9... Intermediate wiring material, 11.12...
Open hole. (C)

Claims (1)

[Claims] 1) Forming a first interlayer insulating film on a wiring region formed on a semiconductor substrate, and removing the first interlayer insulating film at a portion corresponding to the wiring region. forming an intermediate wiring material in the wiring region in which the wiring window is formed and a part of the first interlayer insulating film; further forming and planarizing a second interlayer insulating film on the surface of the film and the intermediate wiring material; A method of manufacturing a semiconductor device, comprising: removing a part of the second interlayer insulating film to open a hole to the intermediate wiring material. 2) The semiconductor device is a field effect transistor, the semiconductor substrate is a Si substrate, the wiring regions are source and drain regions, and the depth of the opening leading to the intermediate wiring material is equal to the field effect transistor. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the opening is formed to have a depth approximately equal to the depth of the opening leading to the gate region of the transistor. 3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the intermediate wiring material is silicide or polysilicon.