JPH08236474A - Formation of connecting section of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method for manufacturing connecting section of semiconductor device by which a semiconductor device in which circuits are made to operate stably can be obtained by preventing the occurrence of a leak current between adjacent transistors. CONSTITUTION: A resist pattern 23 having an opening 24 for contact hole which is positioned above a source impurity-diffused area 13 and reaches part of an element separating section 12 is formed by applying a photoresist material to the surface of an interlayer insulating layer and exposing and developing the material. The contact hole corresponding to the opening 24 is formed by etching the substrate 11 under such a condition that the etching rate of an silicon oxide can become higher than that of P-SiN. Then a P-SiN film 20 exposed in the contact hole is removed by etching the film 20 under such a condition that the etching rate of P-SiN can become higher than that of the silicon oxide.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a connecting portion of a semiconductor device.

[0002]

2. Description of the Related Art In a transistor of a semiconductor device, an interlayer insulating layer is formed on the main surface of a semiconductor substrate including a gate electrode, a source impurity diffusion region and a drain impurity diffusion region. An upper wiring layer is formed on the surface of this interlayer insulating layer. A connection is formed to obtain electrical contact between the upper wiring layer and the source impurity diffusion region, for example. For example, a contact hole exposing at least a part of the source impurity diffusion region is formed in the interlayer insulating layer by a photolithography technique. The upper wiring layer is formed in a desired plane pattern so as to include the surface of the source impurity diffusion region exposed inside the contact hole.

On the other hand, in order to secure a so-called photo margin in the photolithography process and to reduce the residue of photoresist, the interlayer insulating layer is flattened. The planarization of the interlayer insulating layer is performed, for example, by using a SOG film by a spin coating method and a silicon oxide film formed by plasma CVD together, and by reflowing a low melting point glass such as BPSG.

[0004]

When a contact hole having an ideal diameter d is to be formed in a photolithography process, the opening portion having a diameter d + 2x actually depends on the accuracy of the step projection exposure apparatus (stepper). Are known to be formed in the resist pattern.

In recent years, with the miniaturization and higher integration of semiconductor devices, transistors have become finer, and the distance between the gate electrode and the element isolation region, in other words, the width of the source / drain impurity diffusion region (SD region), has become narrower. Tends to become. Therefore, the opening of the resist pattern may reach the element isolation region.

When the interlayer insulating layer is etched by using the resist pattern having such an opening as a mask, a part of the element isolation region made of silicon oxide of the same quality as the interlayer insulating layer is etched. .

Usually, over-etching is performed to remove all the interlayer insulating layer on the source impurity diffusion region. Therefore, the semiconductor substrate having an etching rate lower than that of the interlayer insulating layer cannot be removed, but the element isolation region having substantially the same etching rate as the interlayer insulating layer is removed. As a result, the distance between the adjacent transistors, which is separated by the element isolation region, becomes narrower, a leak current is generated between the two, and malfunction of the circuit is caused.

The present invention has been made in view of the above points, and it is possible to provide a semiconductor device in which a leak current is prevented from being generated between adjacent transistors and a circuit operation is stable. There is provided a method of manufacturing a connection part of the above.

[0009]

According to the present invention, firstly, an element isolation region formed on a main surface of a semiconductor substrate and an element formation region defined by the element isolation region are formed at a predetermined interval. A barrier layer on the main surface of the semiconductor substrate including the source impurity diffusion region and the drain impurity diffusion region, and the gate electrode formed through the gate oxide film between the source impurity diffusion region and the drain impurity diffusion region. A step of forming an interlayer insulating layer having a substantially flat surface on the surface of the barrier layer, applying a photoresist material on the surface of the interlayer insulating layer, and
Exposing and developing to form a resist pattern having an opening located above at least one of the source impurity diffusion region and the drain impurity diffusion region and having at least a portion of the element isolation region formed therein. Etching the semiconductor substrate under conditions such that the etching rate of the interlayer insulating layer is higher than the etching rate of the barrier layer, and forming holes corresponding to the openings formed in the resist pattern. First etching step for forming an interlayer insulating layer, the semiconductor substrate is etched under conditions such that the etching rate of the barrier layer is higher than the etching rate of the element isolation region, and exposed in the hole. The second etching step for removing the barrier layer and the upper wiring layer formed on the surface of the interlayer insulating layer. A method for forming a connection portion of a semiconductor device, comprising the step of forming the connection portion to be electrically connected to at least one of the source impurity diffusion region and the drain impurity diffusion region through the hole. To do.

Secondly, according to the present invention, an element isolation region made of silicon oxide formed on the main surface of a silicon substrate and an element formation region defined by the element isolation region are provided with a predetermined interval. Silicon is formed on the main surface of the silicon substrate including the formed source impurity diffusion region and drain impurity diffusion region, and the gate electrode formed through the gate oxide film between the source impurity diffusion region and drain impurity diffusion region. A step of forming a barrier layer made of a nitride, a step of forming an interlayer insulating layer having a substantially flat surface and made of silicon oxide on the surface of the barrier layer, a photoresist material on the surface of the interlayer insulating layer And then exposing and developing to form a layer above at least one of the source impurity diffusion region and the drain impurity diffusion region. And forming a resist pattern in which an opening extending over at least a part of the element isolation region is formed, the etching rate of the silicon oxide is higher than that of the silicon nitride with respect to the silicon substrate. A first etching step of forming a hole corresponding to the opening formed in the resist pattern in the interlayer insulating layer by performing etching under a condition such that the silicon nitride of the silicon nitride Second etching is performed under conditions such that the etching rate is higher than the etching rate of the silicon oxide to remove the barrier layer exposed in the holes.
An etching step and a step of forming an upper wiring layer on the surface of the interlayer insulating layer so as to be electrically connected to at least one of the source impurity diffusion region and the drain impurity diffusion region through the hole. A method for forming a connection portion of a semiconductor device is provided.

The present invention will be described in more detail below.

In the method of forming the connection portion of the semiconductor device of the present invention, first, a barrier layer is formed on the main surface of the semiconductor substrate including the element isolation region, the source impurity diffusion region, the drain impurity diffusion region, and the gate electrode. . The barrier layer is made of an insulating material. Further, the barrier layer is preferably made of a high melting point material in order to maintain stability in the heat treatment process. Specifically, the barrier layer is made of, for example, silicon nitride.

The barrier layer is formed by using a known thin film forming technique. For example, a silicon nitride film is a plasma C
It can be formed by the VD method.

Transistors formed on the main surface of a semiconductor substrate are well known to those skilled in the art. For example, the element isolation region is a field oxide film (SiO ₂ ) formed on the main surface of the silicon substrate according to the LOCOS method.

For the gate electrode, a gate oxide film is formed on the surface of the element formation region defined by the element isolation region, and then a polysilicon film is deposited on the gate oxide film to form phosphorus (P). To reduce the resistance, and then selectively etched by a photolithography technique to remove the polysilicon film and the gate oxide film in a portion other than the gate electrode. Further, the gate electrode may have a multi-layer structure other than a single layer of a polysilicon film. For example, when viewed from the semiconductor substrate side, the polysilicon film and the low voltage C
It may be a stack of silicon nitride (LP-SiN) films formed by VD.

The source impurity diffusion region and the drain impurity diffusion region are formed by implanting and diffusing impurities of the opposite conductivity type to the semiconductor substrate using the gate electrode as a mask.

Further, the above transistor may have an LDD structure. In this case, on the side wall of the gate electrode,
LD serving as a mask when forming a high-concentration impurity diffusion region
D spacers are formed. The LDD spacer is, for example,
It is formed of silicon oxide.

Next, an interlayer insulating layer having a substantially flat surface is formed on the surface of the above-mentioned barrier layer. The interlayer insulating layer is made of, for example, silicon oxide such as SOG, BPSG, and PSG. This interlayer insulating layer is formed by applying a planarization technique well known to those skilled in the art. For example, the interlayer insulating layer is formed by the spin coating method of SOG or the reflow of low melting glass such as BPSG or PSG. Another CVD film may be used in combination with the silicon oxide film formed by spin coating of SOG.

Next, a resist pattern is formed on the surface of this interlayer insulating layer by a conventional method. First, a photoresist material is applied on the surface of the interlayer insulating layer. Next, the photoresist material is exposed using a stepper, and the pattern of the mask is transferred to the photoresist material. After that, when the photoresist material is developed, openings are formed in the photoresist material according to the transferred pattern. Hereinafter, the photoresist material having the openings formed in this way is referred to as a resist pattern.

In the step of forming the resist pattern described above, an opening for forming a contact hole is formed in the resist pattern in an etching step described later. The openings 71 and 71 are the element isolation regions 73 and the gate electrodes 7.
4 can be exceeded. For example, in order to form an opening for forming a contact hole in the resist pattern,
It is necessary to form a pattern corresponding to the opening of the resist pattern on the mask. Generally, in order to form a contact hole having a diameter of d, a substantially square pattern whose one side length is an arbitrary multiple of d is formed on a mask. When exposure and development are performed using this mask to form a resist pattern, the diameter d + depends on the accuracy of the stepper.
A 2x opening is formed in the resist pattern.

Therefore, as shown in FIG. 7, the ideal diameter d
When trying to form the contact hole, the resist pattern 72 in which the opening 71 having the diameter d + 2x is formed is actually obtained. When the distance between the element isolation region 73 and the gate electrode 74, in other words, when the width W of the SD region 75 is narrow, the opening 71 extends over the element isolation region 73 and the gate electrode 74.

Next, a first etching process is performed by using the above resist pattern as a mask to form a contact hole in the interlayer insulating layer. The first etching step is performed under conditions such that the etching rate of the interlayer insulating layer is higher than the etching rate of the barrier layer. Here, the etching rate can be controlled by, for example, appropriately selecting the chemical species of the etching gas.
For example, when the interlayer insulating layer is SOG and the barrier layer is a silicon nitride (P-SiN) film formed by plasma CVD, etching with a hydrofluoric acid (HF) aqueous solution can be performed. In this case, SOG is etched, but P-SiN is hardly etched. Therefore, the interlayer insulating layer in the region corresponding to the opening formed in the above resist pattern is removed, but the barrier layer remains.

Then, the semiconductor substrate is etched to remove the barrier layer exposed in the contact hole. This second etching step is performed under conditions such that the etching rate of the barrier layer is higher than the etching rate of the interlayer insulating layer. For example, the interlayer insulating layer is S
When OG is used and the barrier layer is P-SiN, etching with hot phosphoric acid can be performed. In this case, P-SiN is etched, but SOG is hardly etched. Therefore, the P-SiN exposed in the contact hole is removed, but the element isolation region made of silicon oxide of the same quality as the interlayer insulating layer made of SOG is left. As a result, a contact hole exposing a part of the surface of the SD area is formed. Note that the resist pattern is removed after the above second etching process is completed.

Appropriate etching conditions in the first and second etching steps described above depend on the materials of the interlayer insulating layer and the barrier layer. That is, the chemical species of the etching gas should be selected according to the materials used for the interlayer insulating layer and the barrier layer.

When the opening of the resist pattern extends over the gate electrode, the material of the gate electrode should be taken into consideration when determining the etching conditions for the second etching process. For example, the uppermost layer of the gate electrode is L
When the barrier layer is a P-SiN film and the barrier layer is a P-SiN film, the etching rate of the P-SiN film is much higher than that of the LP-SiN film according to the etching with hot phosphoric acid. The film is hardly etched. Further, when the LDD spacer made of silicon oxide is provided on the side wall of the gate electrode, since the silicon oxide has the same quality as SOG, it is hardly etched by the hot phosphoric acid.

Next, the upper wiring layer is formed on the surface of the interlayer insulating layer through the contact hole formed as described above.
It is formed so as to be electrically connected to the D region. More specifically, for example, a wiring metal such as aluminum is deposited on the surface of the interlayer insulating layer including the contact hole, and then patterned with a desired wiring pattern including at least the opening portion of the contact hole. As a result, a connection structure for electrically connecting the upper wiring layer and the SD region is formed.

[0027]

In the method of forming the connection portion of the semiconductor device according to the first aspect of the present invention, the barrier layer is formed on the main surface of the semiconductor substrate including the element isolation region, the gate electrode and the SD region. Then the first
In the etching process, etching is performed under the condition that the etching rate of the interlayer insulating layer is higher than the etching rate of the barrier layer. As a result, the interlayer insulating layer in the region corresponding to the opening formed in the resist pattern is removed to form the hole, but the barrier layer remains in the hole.
Next, in the second etching step, etching is performed under the condition that the etching rate of the barrier layer is higher than the etching rate of the element isolation region. This removes the barrier layer exposed in the holes. However, since the element isolation region has a lower etching rate than the barrier layer,
Hardly etched.

Further, in the second method of forming the connecting portion of the semiconductor device of the present invention, the barrier made of silicon nitride is formed on the main surface of the semiconductor substrate including the element isolation region made of silicon oxide, the gate electrode and the SD region. Form the layers. Next, in the first etching step, etching is performed under conditions such that the etching rate of silicon oxide is higher than the etching rate of silicon nitride. As a result, the interlayer insulating layer made of silicon oxide in the region corresponding to the opening formed in the resist pattern is removed to form a hole, but the barrier layer made of silicon nitride remains in the hole. . Next, in the second etching step, etching is performed under the condition that the etching rate of silicon nitride is higher than the etching rate of silicon oxide. As a result, the barrier layer made of silicon nitride exposed in the hole is removed. However, the element isolation region made of silicon oxide having an etching rate lower than that of silicon nitride is hardly etched.

[0029]

The present invention will be described in detail below with reference to the drawings.

As shown in FIG. 1, an element isolation region 12 is formed on the main surface of a silicon substrate 11 according to the LOCOS method. In the element formation region A defined by the element isolation region 12, a source impurity diffusion region 13 and a drain impurity diffusion region 14 are formed at a predetermined interval. A gate electrode 15 is formed between the source impurity diffusion region 13 and the drain impurity diffusion region 14.

The source impurity diffusion region 13 and the drain impurity diffusion region 14 have an LDD structure. On the other hand, the gate electrode 15 is formed on the main surface of the silicon substrate 11 by the gate electrode 1.
6, a polysilicon film 17 and a silicon nitride (LP-SiN) film 18 formed by low pressure CVD are laminated. An LDD spacer 19 made of silicon oxide is formed on the side surface of the gate electrode 15.

On the main surface of the silicon substrate 11 including the element isolation region 12, the source impurity diffusion region 13, the drain impurity diffusion region 14 and the gate electrode 15 as described above, a silicon nitride (P-
A SiN) film 20 was formed. Next, as shown in FIG.
An interlayer insulating layer 21 having a substantially flat surface was formed on the surface of the P-SiN film 20. Specifically, SOG dissolved in an organic solvent was spin-coated on the surface of the P-SiN film 20 and then baked to obtain an interlayer insulating layer 21.

Thereafter, as shown in FIG. 3, the interlayer insulating layer 2
Photoresist material 22 was applied onto the surface of No. 1. Then, after the photoresist material 22 was pre-baked, a stepper was used to irradiate the mask on which a predetermined pattern was drawn for a certain period of time to transfer the mask pattern to the photoresist material 22. Next, development is performed using a developing solution,
The photoresist material 22 was post-baked. As a result,
As shown in FIG. 3, a resist pattern 23 having openings formed in a predetermined pattern on the surface of the interlayer insulating layer 21 was obtained.

Here, the mask used for the exposure of the photoresist material 22 has a pattern corresponding to the opening formed in the resist pattern 23. Therefore, in order to form an opening (hereinafter, referred to as a contact hole opening) for forming a contact hole that exposes a part of the source impurity diffusion region 13 in the resist pattern 23, this contact hole opening is formed in the mask. A pattern corresponding to the parts is required. That is, in order to form a contact hole having a diameter d, the length of one side is d.
The mask is formed with a substantially square pattern that is n times the number. Using this mask, a stepper performs reduction projection exposure to 1 / n to form a contact hole opening in the resist pattern 23. However, in reality, the diameter of the contact hole opening 24 was d + 2x depending on the accuracy of the stepper, as shown in FIG. Therefore, the contact hole opening 24 also extends above the element isolation region 12 and the gate electrode 15.

Next, the silicon substrate 11 was subjected to the first etching using a hydrofluoric acid aqueous solution (20: 1).
In this first etching, the interlayer insulating layer 2 made of SOG is used.
The etching rate of 1 is 700 angstrom (A) / min, while the barrier layer is P-Si.
The etching rate of the N film 20 was 120 A / min, and the etching rate of the LP-SiN film 18, which was the uppermost layer of the gate electrode 15, was 60 A / min. Therefore, in this first etching process, as shown in FIG. 5, the interlayer insulating layer 21 in the region corresponding to the contact hole opening 24 of the resist pattern 23 is removed by etching, and the contact hole 25 is formed. It was On the other hand, the P-SiN film 20 having a low etching rate was hardly etched. As a result, the element isolation regions 12 and LP under the barrier layer P-SiN film 20 are formed.
-SiN film 18 and LDD spacer 19 were not affected by etching at all.

Next, the silicon substrate 11 is heated to 80 ° C.
Etching was performed with hot phosphoric acid. In this etching with hot phosphoric acid, the etching rate of the P-SiN film 20 was 150 A / min. On the other hand, the etching rate of the silicon oxide including the interlayer insulating layer 21 made of SOG, the element isolation region 12, and the LDD spacer 19 is 10%.
It was A / min or less. The etching rate of the LP-SiN film 18 was 80 A / min. Therefore, as shown in FIG. 6, the PS exposed in the contact hole 25 is exposed.
The iN film 20 was removed by etching. However, the element isolation region 12, the LP-SiN film 18 and the LDD spacer 19 below the P-SiN film 20 in the contact hole 25 were hardly etched.

After that, the resist pattern 23 is removed,
Aluminum was deposited on the surface of the interlayer insulating layer 21 including the contact holes 25. Then, aluminum was patterned by a conventional method. As a result, as shown in FIG. 6, the upper wiring layer 26 was formed so as to be electrically connected to the source impurity diffusion region 13 through the contact hole 25.

In the method of forming the connection portion of the semiconductor device described above, the element isolation region 12 made of silicon oxide is
The etching with the first hydrofluoric acid aqueous solution does not undergo any etching because it is protected by the P-SiN film 20 which is the barrier layer. In the second etching with hot phosphoric acid, the etching rate of silicon oxide is PS.
Since it is much lower than the iN film 20, the element isolation region 12
Is hardly etched. Therefore, the element isolation region 12 is hardly etched when the contact hole 25 is formed. Therefore, the element isolation region 12 is removed by the etching process, and a leak current flows between the source impurity diffusion region 13 of one transistor 30 and the drain impurity diffusion region 14 of the other transistor 31 separated by the element isolation region 12. It was possible to prevent the occurrence of the noise and always obtain good circuit characteristics.

Further, similarly to the element isolation region 12, the LP-SiN film 18 and the LDD spacer 19 which are the uppermost layer of the gate electrode 15 exposed in the contact hole 25 are almost etched when the contact hole 25 is formed. Absent.

The P-SiN film 20 which is a barrier layer is also used.
Plays a role of protecting the transistors 30 and 31 from moisture generated from the interlayer insulating layer when the interlayer insulating layer 21 made of SOG is formed, and at the same time, the interlayer insulating layer 21 is planarized by chemical mechanical polishing (CMP). In this case, it plays a role of protecting the transistors 30 and 31 from ion contamination such as sodium ions.

Further, as shown in FIG. 6, when the wiring layer 41 is formed on the surface of the element isolation region 12 formed on the main surface of the silicon substrate 11, the element isolation region 12 is formed in the same manner as described above. The P-SiN film 20 is formed as a barrier layer on the main surface of the silicon substrate 11 including the source impurity diffusion region 13, the drain impurity diffusion region (not shown), the gate electrode (not shown) and the wiring layer 41, and As described above, the first contact hole 25 corresponding to the source impurity diffusion region 13 is formed, and at the same time, the second contact hole 25 corresponding to the wiring layer 41 is formed.
The contact hole 42 can be formed. At this time, although the depth of the second contact hole 42 is shallower than that of the first contact hole 25, the wiring layer 41 is formed of P-Si.
Since it is protected by the N film 20, when the interlayer insulating layer 21 is etched in the above-described first etching step, damage that the wiring layer 41 suffers due to etching such as overetching of the wiring layer 41 can be reduced.

[0042]

As described above, according to the method for forming the connection portion of the semiconductor device of the first aspect of the present invention, the opening formed in the resist pattern extends over at least a part of the element isolation region. Even in the first etching step,
Since etching is performed under the condition that the etching rate of the interlayer insulating layer is higher than the etching rate of the barrier layer,
The barrier layer is hardly etched and can protect the element isolation region thereunder. Then, in the second etching step, since the etching is performed under the condition that the etching rate of the barrier layer is higher than the etching rate of the element isolation region, the element isolation region is hardly etched. As a result, in the formation of the connection portion of the semiconductor device, it is possible to prevent the element isolation region from being shaved and generating a leak current between the adjacent transistors, and it is possible to always obtain good circuit characteristics.

Further, according to the second method of forming the connection portion of the semiconductor device of the present invention, even when the opening formed in the resist pattern extends over at least a part of the element isolation region, In one etching step, the etching rate is higher than that of silicon oxide and the etching rate of silicon nitride is higher than that of silicon nitride. The element isolation region made of oxide can be protected. In the second etching step, since the etching is performed under the condition that the etching rate of silicon nitride is higher than the etching rate of silicon oxide, the element isolation region made of silicon oxide is hardly etched. As a result, in the formation of the connection portion of the semiconductor device, it is possible to prevent the element isolation region from being shaved and generating a leak current between the adjacent transistors, and it is possible to always obtain good circuit characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view showing a step of a method of forming a connection portion of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a step in the method of forming the connection portion of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing a step in the method of forming the connection portion of the semiconductor device of the present invention.

FIG. 4 is a cross-sectional view showing a step in the method of forming the connection portion of the semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing a step in the method of forming the connection portion of the semiconductor device of the present invention.

FIG. 6 is a cross-sectional view showing another embodiment of the method for forming the connection portion of the semiconductor device of the present invention.

FIG. 7 is a cross-sectional view for explaining an opening formed in a resist pattern in the method for forming a connecting portion of a semiconductor device according to the present invention.

[Explanation of symbols]

11 ... Silicon substrate, 12 ... Element isolation region, 13 ... Source impurity diffusion region, 14 ... Drain impurity diffusion region, 1
5 ... Source electrode, 16 ... Gate oxide film, 17 ... Polysilicon film, 18 ... LP-SiN film, 19 ... LDD spacer, 20 ... P-SiN film, 21 ... Interlayer insulating layer, 22 ... Photoresist material, 23 ... Resist pattern, 24 ... Contact hole opening, 25 ... Contact hole, 26
... upper wiring layer, 30, 31 ... transistors.

Claims (2)

[Claims] 1. An element isolation region formed on a main surface of a semiconductor substrate, a source impurity diffusion region and a drain impurity diffusion region formed at predetermined intervals in an element formation region defined by the element isolation region, And a step of forming a barrier layer on the main surface of the semiconductor substrate including a gate electrode formed between the source impurity diffusion region and the drain impurity diffusion region via a gate oxide film, on the surface of the barrier layer A step of forming an interlayer insulating layer having a substantially flat surface, applying a photoresist material on the surface of the interlayer insulating layer,
Next, exposure and development are performed to form a resist pattern having an opening located above at least one of the source impurity diffusion region and the drain impurity diffusion region and having at least a part of the element isolation region formed therein. Etching the semiconductor substrate under conditions such that the etching rate of the interlayer insulating layer is higher than the etching rate of the barrier layer, and holes corresponding to the openings formed in the resist pattern. A first etching step of forming in the interlayer insulating layer, the semiconductor substrate is etched under conditions such that the etching rate of the barrier layer is higher than the etching rate of the element isolation region, A second etching step for removing the barrier layer exposed at the upper surface, and an upper wiring layer for the interlayer A connecting portion of the semiconductor device, which is formed on the surface of the edge layer so as to be electrically connected to at least one of the source impurity diffusion region and the drain impurity diffusion region through the hole. Forming method. 2. An element isolation region made of silicon oxide formed on a main surface of a silicon substrate, a source impurity diffusion region formed at a predetermined interval in an element formation region defined by the element isolation region, and A barrier layer made of silicon nitride is formed on the main surface of the silicon substrate including a drain impurity diffusion region and a gate electrode formed between the source impurity diffusion region and the drain impurity diffusion region via a gate oxide film. A step of forming an interlayer insulating layer having a substantially flat surface and made of silicon oxide on the surface of the barrier layer, applying a photoresist material on the surface of the interlayer insulating layer,
Then, exposure and development are performed to form a resist pattern having an opening located above at least one of the source impurity diffusion region and the drain impurity diffusion region and having at least a part of the element isolation region formed therein. Etching the silicon substrate under conditions such that the etching rate of the silicon oxide is higher than the etching rate of the silicon nitride, to correspond to the openings formed in the resist pattern. A first etching step of forming a hole in the interlayer insulating layer, etching the silicon substrate under conditions such that the etching rate of the silicon nitride is higher than the etching rate of the silicon oxide, A second etching step for removing the barrier layer exposed in the hole, and A step of forming an upper wiring layer on the surface of the interlayer insulating layer so as to be electrically connected to at least one of the source impurity diffusion region and the drain impurity diffusion region through the hole. A method for forming a connection portion of a semiconductor device.