JPH01187872A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a semiconductor device which has a gate electrode made of high melting point metal with a precision structure and high quality by a method wherein, in order to remove a silicon nitride film with a thickness A and a silicon oxide film with a thickness B simultaneously by etching, a process in which etching is carried out with reactive gas whose pressure is adjusted in accordance with the film thickness ratio A:B is provided. CONSTITUTION:In a process of forming a semiconductor device, a resist film mask 15 is so formed as to expose wiring parts for contacts with a gate electrode and a drain region and a PSG film 7 is vertically etched by a RIE method. At that time, mixed gas of CF4+O2 is used as etching reactive gas. Then, while the mask is left as it is, an SiO2 film 20 with a thickness of 500Angstrom and an Si3N4 film 4 with a thickness of 1000Angstrom are etched simultaneously with the same reactive gas. If the gas pressure is selected to be 0.3Torr at that time, the SiO2 film 20 and the Si3N4 film 4 can be removed simultaneously so that the contact wiring part of the gate electrode and the contact wiring part of the drain region can be opened simultaneously.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a field effect transistor having a high melting point metal film gate, the purpose is to form it finely and with high quality, and the film thickness A provided on a semiconductor substrate is A silicon nitride film having a thickness of B and a silicon oxide film having a thickness of B are etched with a reaction gas, and the reaction is performed according to the film thickness ratio A:B so that the silicon nitride film and the silicon oxide film are etched and removed at the same time. The method is characterized in that it includes a step of adjusting the gas pressure to perform etching.

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a field effect transistor having a high melting point metal film gate.

A typical field effect transistor is a MOS transistor, and a semiconductor integrated circuit (MO3rC) made of the MOS t-transistor is widely used in logic circuits such as memory and arithmetic circuits. Such MOSIGs are becoming increasingly finer, and therefore have higher resistance, and the use of electrode wiring materials with even lower resistance is being promoted to lower the resistance.

[Prior art] Fig. 4(a), (bl is a cross-sectional view of a MOS l-transistor having a tungsten gate (a type of high-melting point metal gate), ■ is a p-type silicon substrate, 2 is a gate insulating film, 3 is a gate electrode made of tungsten (W), 4 is a silicon nitride (Si3 Na) film, and 5 is a silicon oxide (Si02) film such as a field insulating film.

6 is an n+ type source or drain region, 7 is a phosphorous silicate glass (PSG) film, 8 is an aluminum (AI) wiring led out from the drain region, and 9 is an aluminum (AI) wiring led out from the gate electrode.

In addition, FIG. 4(a) shows a cross-sectional view of a MOS transistor, and FIG. 4(b) is a cross-sectional view (cross-sectional view taken along a polygonal line) showing the drain region and gate electrode portion. However, this is for explaining the subsequent formation steps using the cross section of FIG. 2(b). Note that the Si3N4 film 4 also surrounds the gate electrode 3, since the drawing shows an LDD structure in which the sidewalls are formed of the Si3N4 film.

By the way, as is well known, the method for forming a MOS (MOS) transistor is to first form a gate insulating film and a gate electrode, and then use the gate electrode and field insulating film as a mask to form the source and drain regions by self-alignment. A method of forming by ion implantation is adopted.

Therefore, since the wiring 1IA8.9 is formed in a relatively later process, it is possible to lower the resistance by using aluminum with a low melting point, but the gate electrode 3 is formed in an early process. It is difficult to use aluminum, which has a low melting point, and therefore, conventionally, a conductive polycrystalline silicon film has been used as the gate electrode.

However, there was a desire to lower the resistance of the gate electrode,
Instead of a conductive polycrystalline silicon film, tungsten silicide (WSi2) or molybdenum silicide (MoSi
Metal silicide films with high melting points such as 2) came into use, and this had the effect of lowering resistance to some extent. However, as ICs have recently become more highly integrated and miniaturized, it has become desirable for gate electrodes to have even lower resistance. I've started using it. This high melting point metal film is a material that can lower the resistance value by about one order of magnitude compared to a silicide film.

However, tungsten or molybdenum is deposited as a gate electrode film, and 5i is deposited on top of it by chemical vapor deposition (CVD).
If the gate electrode is formed by depositing and covering the 5i02 film and patterning both at the same time, there is a problem that side etching of the gate electrode progresses. It has been found that if the gate electrode is formed by depositing and covering the gate electrode by the CVD method and patterning the gate electrode at the same time, side etching does not proceed and undercuts do not occur. Figures 5(a) and 5(b) are diagrams showing the problems of the previous version, and Figure 5(a) is 5i02
In the case where the film 5 is coated, the figure (b) shows the case where the Si3N4 film 4 is coated, 10 is a resist film mask, and the symbols of other members are the same as in FIG.

The reason why the 5i02 film 5 and the Si3N4 film 4 are coated on the gate electrode made of tungsten or molybdenum and patterned at the same time is that after the gate electrode is formed, ion implantation is performed to define the source and drain regions. This is because tungsten or molybdenum alone cannot serve as an ion implantation shielding film (mask), and implanted ions channel (transmit), making it impossible to form source and drain regions in a self-aligned manner.

[Problems to be Solved by the Invention] Therefore, a conventional method for forming a MOS transistor having a high melting point metal gate in which such Si8N4 films are laminated (
I) will be explained with reference to step-by-step sectional views of FIGS. 6(a) to (d+), and the problems thereof will be explained at the same time.

FIG. 6 (see al; First, a field insulating film consisting of a SiO2 film 5 is formed on a p-type silicon substrate l by a known manufacturing method, and a field insulating film consisting of a SiO2 film 5 is formed by a gate insulating film 2, a tungsten gate electrode 3, and a S'i3N4 film. A Si3 N4 film 4 is deposited and patterned at the same time, and a Si3 N4 film 4 is formed as a side wall on the sidewalls of the gate electrode.Next, using these as a mask, arsenic ions are implanted to form the n+ type source and drain. A region 6 is defined, and the entire surface is further covered with a PSG film 7 (cover film).

The MOS) transistor element is completed above, but next,
AI wiring led out from this element is formed.

6 (see BL; therefore, the surface is covered with a resist film mask 11 that exposes the connection wiring portion, and the PSG film 7 is subjected to vertical reactive ion etching (RIE) using a fluorine (F)-based gas.

Figure 6 (see C1; Next, with the mask as it is, 5i
The 02 film 5 is etched to complete the opening of the n+ type drain region 6.

FIG. 6 (see dl; however, even if the drain region is opened, the Si3N4 film 4 on the tungsten gate electrode 3 is difficult to be etched, so the etching may be continued as it is, or the etching gas may be changed, e.g. Then, etching the Si3N4 film with sulfur hexafluoride (SFs) completes the opening of the connection with the gate electrode.

However, because the etching ratio of the 5i02 film and the Si3N4 film with the same gas is different, the surface of the drain region may be over-etched, or, depending on the type of etching reaction gas, the gate electrode may be over-etched. Something happens.

For this reason, currently, these connection wirings are fabricated by using two photo processes in which separate resist film masks are provided and two windows are opened, instead of using the photo process described above in which two windows are opened at the same time using one resist film mask. is formed.

'Figures 7(al) and 7(b) show step-by-step cross-sectional views of the formation method (I[), and the formation of the MOS transistor element is the same as the method explained in Figure 6(al), so it is omitted. Only the method of forming the wiring will be explained.The same parts as in FIG. 4 are given the same symbols.

Refer to FIG. 7(a); First, a resist film mask 12 is formed that exposes only the wiring portion connected to the drain region, and R
Etch using the IE method to open a window in the drain wiring area.

FIG. 7 (see BL; see FIG. 7) Next, a resist film mask 13 is formed which exposes the wiring portion to be connected to the tungsten gate electrode, and etched by the RIE method to open a window in the wiring portion to be connected to the gate electrode.

According to the forming method that applies these two photo steps, there is no fear of over-etching the connection surface, and the connection surface can be opened smoothly and accurately. However, since patterning is performed twice, it is necessary to take alignment errors into account, which has the disadvantage that miniaturization of ICs is hindered and the number of processing steps increases accordingly.

The present invention proposes a manufacturing method aimed at solving these problems and forming a semiconductor device having a gate electrode made of a high-melting point metal film in a fine structure and with high quality. .

[Means for Solving the Problems] The purpose is, as shown in the principle diagrams shown in FIGS. A silicon oxide film 25 having a thickness B,
etching with a reactive gas so that the silicon nitride film and the silicon oxide film are etched away at the same time;
This is achieved by a method of manufacturing a semiconductor device including a step of adjusting the gas pressure of the reaction gas according to the film thickness ratio A:B. FIG. 1(a) shows the state before etching, and FIG. 1tb) shows the state after etching.

[Function] That is, the present invention provides Si3N on a high melting point metal film gate electrode.
Etching is performed by adjusting the gas pressure of the reaction gas so that the 5i02 film on the drain region and the 5i02 film on the drain region can be etched at the same time.

Then, by one photo process, the window surface between the high-melting point metal film gate electrode surface and the drain region surface can be formed flat and accurately without being over-etched.

[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

Figure 2 shows the etching rate of the Si3N4 film and the 5i02 film with respect to changes in gas pressure.
This data is obtained when a reaction is performed at an output of 250 watts using a mixed gas of 20 sec. The horizontal axis is the gas pressure changed from Ool to I Torr, and the left vertical axis is the etching rate (people/min).
4 film), line n (Si02 film), line I [[(Si),
'fiA■(W). In the case of the Si3N4 film, the etching rate becomes thicker as the gas pressure increases, as shown by the line (2), but in the case of the 5i02 film, the etching rate decreases as the gas pressure increases, as shown in the line (2).

From this figure, if the film thickness of the Si3N4 film and the 5i02 film are the same, if the gas pressure is set to 0.1 Torr, the Si3
The N4 film and the 5i02 film are etched away, and
It can be seen that if the Si3N4 film is twice as thick as the 5i02 film, it will be etched away at the same time when the gas pressure is set to about 0.3 Torr. Therefore, a condition is required that allows etching to be removed at the same time even if the film thickness ratio changes to some extent, and this selectivity can be expressed as a line V. Note that this line ■ corresponds to the scale of the right vertical axis.

Therefore, depending on the selectivity of line V, the Si3N4 film and 310
It becomes possible to determine the gas pressure conditions under which the two films are etched away at the same time, and to select those conditions for etching.

Step-by-step sectional views of the forming method according to the present invention using this selection ratio are shown in FIGS. 3(a) to 3(C).

Refer to FIG. 3(a); similarly to the conventional example, a field insulating film consisting of a 5i02 film 5 is formed on a p-type silicon substrate 1, and a gate insulating film 2 (thickness: 100 to 200) and a tungsten film 3 ( film thickness of about 2,000 people), and 5t3
An N4 film 4 (about 1,000 layers thick) is deposited and patterned at the same time to form a gate electrode portion, and an Si3N4 film 4 serving as a sidewall is also formed on the side surfaces of the gate electrode. Next, using these as a mask, arsenic ions are implanted to define n+ type source and drain regions 6, and then the entire surface is covered with a PSG film 7 (thickness: 5000 mm).

At this time, a 5i02 film 20 having a thickness of about 500 nm is formed on the source and drain regions by heat treatment for defining the source and drain regions. Note that this cross-sectional view does not show the source region.

Refer to FIG. 3(b); Next, the resist film mask 1 exposes the wiring portion connected to the gate electrode and drain region.
5, and PSG II 7 is vertically etched by RIE. At this time, a mixed gas of CF4+02 gas is used as the etching reaction gas.

See Figure 3(C); then, leaving the mask in place,
5i02 film 20 and Si3N4 film 4 using the same reaction gas.
However, when the gas pressure at that time is set to 0.3 Torr, the 5i02 film 20 with a thickness of 500 and the Si3N4 film with a thickness of 1000 are etched at the same time, and the connection wiring portion of the gate electrode is also etched as a drain. The connection wiring portion of the area is also opened at the same time, and its surface is not over-etched.

Thereafter, wiring connected to the gate electrode and the drain region is formed, and the shape shown in FIG. 4 is finished.

The above is an overview of the forming method according to the present invention. According to this forming method, windows can be formed simultaneously in one photo process, and the connecting surface is not over-etched, which prevents miniaturization of the IC. Furthermore, the quality can be improved and the number of processing steps can be reduced.

Although this embodiment uses CF and +O□ gases as reaction gases, other fluorine (F)-based gases can be similarly used to form windows with high precision in one photo process.

Further, although the above example uses a gate electrode made of tungsten, the same etching can be performed when a molybdenum gate electrode or other high melting point metal film gate electrode is used by selecting the etching gas.

[Effects of the Invention] As is clear from the above description, the formation method according to the present invention is useful for miniaturizing and improving the quality of MO3ICs consisting of MOS transistors having high melting point metal film gates, and Processing man-hours.

It is also possible to obtain the effect of reducing the

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention; FIG. 2 is a diagram showing the etching rate with respect to changes in gas pressure; FIGS. Figure + aL (b) M with tungsten gate
A cross-sectional view of an OS transistor. FIG. 5 is a diagram showing the problems of the conventional method. FIG. ) are step-by-step sectional views of the conventional forming method (II). In the figure, ■ is a p-type silicon substrate, 2 is a gate insulating film, 3 is a tungsten gate electrode or tungsten film, 4.24 is a Si3N4 film, 5, 20.25 is a 5i02 film, 6 is an n+ type source and drain region , 7 is PSG film, 8.9 is aluminum (8L) self-wire, 10, 11.1
2.13.15 is a resist film mask, 21 is a mask for semiconductor device control.

Claims (1)

[Claims] Etching a silicon nitride film having a thickness A and a silicon oxide film having a thickness B provided on a semiconductor substrate with a reactive gas so that the silicon nitride film and the silicon oxide film are etched away at the same time. A method of manufacturing a semiconductor device, comprising a step of adjusting the gas pressure of the reaction gas according to the film thickness ratio A:B.