JP2002110790A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the same, where the thickness of a sidewall can be formed thinner, while avoiding increase in leakage current between a conductive plug and a gate electrode. SOLUTION: The semiconductor device comprises a first conductive film 14 formed on a substrate 10, an interconnection layer 20 having a second conductive film 18 formed on the first conductive film, a capping film 22 formed on the interconnection layer, an insulation film 26 formed at least on the side surface of the interconnection layer, and a conductive plug 34 being adjacent to the interconnection layer separated by the insulation film. The side surface of the second conductive film is located further toward the inside than that the first conductive film and the capping film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a fine semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the increase in the scale of LSIs, miniaturization of elements has been pursued.

In order to realize a semiconductor integrated circuit having gates, wirings and contact holes of finer dimensions, it has been conventionally practiced to shorten the exposure wavelength in photolithography to improve the resolution.

While the minimum resolution size is reduced in this way, various device structures for reducing the alignment margin between lithography steps have been studied. The device size can be reduced without reducing the size of the pattern to be formed. Attempts have been made to make it smaller.

[0005] Such a device structure includes, for example, a self-aligned contact (Self-Aligned Contact).
t: hereinafter, referred to as SAC).

A proposed method of manufacturing a semiconductor device using the SAC technique will be described with reference to FIGS.
18 and 19 are process cross-sectional views illustrating a proposed method for manufacturing a semiconductor device.

First, as shown in FIG. 18A, a gate insulating film 112, a polysilicon film 114, a buffer film 116, a metal film 118, and a cap film 122 are sequentially formed on a silicon substrate 110.

Next, the cap film 12 is formed using a photoresist mask 136 for forming a gate electrode as a mask.
2. The metal film 118, the buffer film 116 and the polysilicon film 114 are anisotropically etched, and the upper surface is
2, the polysilicon film 114 and the buffer film 11
6, and a gate electrode 120 having a polymetal structure composed of a metal film 118 is formed (see FIG. 18B).

Next, a silicon oxide film 115 is formed on the exposed surface of the polysilicon film 114. Next, source / drain diffusion layers 128 and 129 are formed by performing ion implantation in a self-aligned manner on the gate electrode 120 whose upper surface is covered with the cap film 122. Next, a silicon nitride film 124 is formed on the entire surface.
4 is anisotropically etched. Next, a silicon nitride film 125 is formed on the entire surface. Thus, the top surface is the cap film 1
On the side surface of the gate electrode 120 covered by the gate insulating film 22, a sidewall insulating film 126 made of a silicon nitride film 124 and a silicon nitride film 125 is formed.

Next, heat treatment is performed in a nitrogen atmosphere to activate the ions introduced into the source / drain diffusion layers 128 and 129. Thus, a MOS transistor having a polymetal structure gate electrode 120 is formed.
8 (c)).

Next, a BPSG film 130 is formed on the entire surface. Thereafter, BPSG is used until the cap film 122 is exposed.
The film 130 is polished (see FIG. 19A).

Next, a photoresist mask 140 having an opening 138 for performing SAC is formed. next,
Using the photoresist mask 140 as a mask, the BPSG film 13 has a high selectivity with respect to the sidewall insulating film 126.
0, and then the silicon nitride film 125 is anisotropically etched to form the source / drain diffusion layers 1.
29 is formed (FIG. 1)
9 (b)).

Next, a polysilicon film doped with P (phosphorus) is formed on the entire surface. Thereafter, the cap film 122
The surface is polished until the surface is exposed, and a conductor plug 134 made of a polysilicon film having a planarized surface is formed in the contact hole 132 (see FIG. 19C).

In the method of manufacturing a semiconductor device proposed in this way, since the contact holes are formed by using the SAC technique, there is no need for a mask alignment allowance conventionally required, and the semiconductor device can be miniaturized. It becomes possible. Therefore, according to the proposed method of manufacturing a semiconductor device, a semiconductor device with a high degree of integration can be provided.

[0015]

However, in the proposed semiconductor device, a large leak current may flow between the conductor plug 134 and the gate electrode 120. The reason why a large leak current flows between the conductor plug 134 and the gate electrode 120 is that RIE (Reacti) when the silicon nitride film 124 is anisotropically etched.
19 (c) due to damage due to ve ion etching (reactive ion etching), damage due to RIE when forming the contact hole 132, damage due to HF pretreatment when forming the conductor plug 134, etc. It is considered that the thickness of the sidewall insulating film 126 at the shoulder of the gate electrode 120 is locally reduced.

FIG. 20 is a graph showing the measurement results of the leak current of the proposed semiconductor device. The horizontal axis indicates the leak current, and the vertical axis indicates the cumulative frequency when the samples are arranged in ascending order of the leak current. The numbers in the figure indicate the thickness of the sidewall insulating film. For convenience, in this specification, the thickness of the sidewall insulating film is indicated by the thickness when deposited on a plane.

As can be seen from FIG. 20, when the thickness of the sidewall insulating film is 30 nm or more, the leakage current is suppressed to a small value. However, when the thickness of the sidewall insulating film is reduced to 25 nm, the leakage current is reduced. The current tends to increase. For this reason, in the proposed semiconductor device,
For example, a sidewall insulating film having a thickness of 30 nm or more has to be formed.

In order to realize a further integration of the semiconductor device, it is important to further reduce the thickness of the side wall insulating film and narrow the pitch of the gate electrode. It has been difficult to reduce the thickness of the film, which has been an obstacle to the integration of semiconductor devices.

Further, when the semiconductor device is miniaturized, the contact area between the conductor plug and the source / drain diffusion layer is reduced, and the contact resistance is increased. However, in the proposed semiconductor device, the sidewall insulating film is further increased. It is difficult to reduce the film thickness, and this has been a hindrance factor in the integration of semiconductor devices.

An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can reduce the thickness of a sidewall insulating film while avoiding an increase in leakage current between a conductor plug and a gate electrode. It is in.

[0021]

The object of the present invention is to provide a wiring layer having a first conductive film formed on a substrate and a second conductive film formed on the first conductive film; A second conductive film, comprising: a cap film formed on the wiring layer; an insulating film formed at least on a side surface of the wiring layer; and a conductor plug adjacent to the wiring layer with the insulating film interposed therebetween. Is located inside the side surface of the first conductive film and the side surface of the cap film. Accordingly, since the side surface of the second conductive film is located inside the side surface of the cap film, the effective thickness of the insulating film on the side surface of the second conductive film can be ensured to be large. Therefore, it is possible to reduce the thickness of the insulating film while suppressing the leak current between the conductor plug and the wiring layer, thereby contributing to miniaturization of the semiconductor device.

The above object is also achieved by a step of forming a wiring layer on a substrate, the upper surface of which is covered by a cap layer and at least a part of the side surface is located inside the side surface of the cap layer. This is achieved by a method for manufacturing a semiconductor device, comprising: forming an insulating film on a side surface; and forming a conductor plug adjacent to the wiring layer with the insulating film interposed therebetween. Accordingly, since the side surface of the wiring layer is located inside the side surface of the cap film, it is possible to secure a large effective film thickness of the insulating film on the side surface of the wiring layer. Therefore, it is possible to reduce the thickness of the insulating film while suppressing the leak current between the conductor plug and the wiring layer, thereby contributing to miniaturization of the semiconductor device.

[0023]

[First Embodiment] The semiconductor device and the method for fabricating the same according to a first embodiment of the present invention will be explained with reference to FIGS. FIG. 1 is a sectional view of the semiconductor device according to the present embodiment. FIG. 2 is a graph showing the result of evaluating the leakage current of the semiconductor device according to the present embodiment.
3 to 6 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.

(Semiconductor Device) First, the semiconductor device according to the present embodiment will be explained with reference to FIG.

As shown in FIG. 1, a gate electrode 20 is formed on a silicon substrate 10 via a gate insulating film 12 made of a silicon oxynitride film. Gate electrode 20
Extends in the direction perpendicular to the plane of the paper, and also functions as a word line that also functions as a gate electrode of another transfer transistor.

The gate electrode 20 includes a polysilicon film 14 formed on the gate insulating film 12 and a polysilicon film 14.
It has a polymetal structure of a buffer film 16 made of WSiN formed thereon and a metal film 18 made of tungsten formed on the buffer film 16. The buffer film 16 is for preventing the reaction between the polysilicon film 14 and the metal film 18 to form tungsten silicide having high resistance.

On the side surface of the polysilicon film 14, a silicon oxide film 15 is formed. On the gate electrode 20,
A cap film 22 made of a silicon nitride film is formed. The side surfaces of the buffer film 16 and the metal film 18 are located about 15 nm inside the side surfaces of the cap film 22. Silicon nitride films 24 are formed on the side surfaces of the gate electrode 20 and the cap film 22.

On the gate insulating film 12 and the silicon nitride film 2
The silicon nitride film 25 is formed on the side surface of the substrate 4.
The silicon nitride film 24 and the silicon nitride film 25 form a sidewall insulating film 26.

On the silicon substrate 10, source / drain diffusion layers 28 and 29 are formed in self alignment with the gate electrode 20 having the side wall insulating film 26 formed on the side surface.

Thus, a MOS transistor having the gate electrode 20 and the source / drain diffusion layers 28 and 29 is formed.

On the silicon nitride film 25, BPSG (Boro
-Phospho-Silicate Glass) film 30 is formed,
The substrate surface is flattened by the BPSG film 30.

In the BPSG film 30, a contact hole 32 reaching the source / drain diffusion layer 29 is formed. In the contact hole 32, a conductor plug 34 made of polysilicon doped with P (phosphorus) is buried.

The semiconductor device according to the present embodiment is mainly characterized in that the side wall portion of the metal film 18 immediately below the cap film 22 is etched, and the side surface of the metal film 18 is located inside the side surface of the cap film 22. There are features.

In the proposed semiconductor device shown in FIGS. 18 and 19, the gate electrode 12
In some cases, the thickness of the side wall insulating film 126 at the 0 shoulder becomes locally thin, and a large leak current may flow between the conductor plug 134 and the gate electrode 120. For this reason, in the proposed semiconductor device, it is difficult to reduce the thickness of the sidewall insulating film 126 to, for example, 30 nm or less, which has been an obstacle to miniaturization of the semiconductor device.

On the other hand, in the present embodiment, the side wall portion of the metal film 18 immediately below the cap film 22 is etched, and the side surface of the metal film 18 is located inside the side surface of the cap film 22. The thickness of the silicon nitride film 24 covering the side surface of the film 18 is locally increased. Therefore, even if the side wall insulating film 26 is locally thinned at the shoulder of the gate electrode 20, the effective side wall insulating film 2 between the conductor plug 34 and the metal film 18 can be formed.
6 can be sufficiently thick. According to the present embodiment, it is possible to reduce the thickness of the sidewall insulating film 26 while avoiding an increase in leakage current between the conductor plug 34 and the gate electrode 20, so that the semiconductor device can be further miniaturized. Can be realized.

For example, the metal film 18 immediately below the cap film 22
When the side wall portion is etched by about 10 nm, the effective film thickness of the side wall insulating film 24 on the side surface of the metal film 18 is increased by about 10 nm.
The thickness of the sidewall insulating film 26 can be reduced by about 10 nm as compared with the proposed semiconductor device shown in FIG. For example, when the thickness of the sidewall insulating film 126 is required to be 30 nm in the proposed semiconductor device shown in FIGS. 18 and 19, the thickness of the sidewall insulating film 26 is reduced in the semiconductor device according to the present embodiment. 20nm
It becomes possible.

For example, if the basic design rule is 0.13 μm
In the case of a DRAM cell of m, if the thickness of the sidewall insulating film 26 is reduced by 10 nm on one side, the pitch of the cell portion can be reduced from 260 nm to 240 nm, and the area of the cell portion can be reduced by about 8%. Can be.

Further, when the side wall portion of the metal film 18 immediately below the cap film 22 is etched by about 20 nm, the effective film thickness of the side wall insulating film 26 on the side surface of the metal film 18 increases by about 20 nm. The thickness of the sidewall insulating film 26 can be reduced by about 20 nm as compared with the proposed semiconductor device shown in FIGS.

For example, if the basic design rule is 0.13 μm
m, the thickness of the sidewall insulating film 26 is 2 on one side.
If the thickness is reduced by 0 nm, the pitch of the cell portion is 260 nm.
To 220 nm, and the area of the cell portion can be reduced by about 15%. Further, when the basic design rule is reduced to, for example, 0.1 μm, the area of the cell portion can be reduced by about 20% by reducing the thickness of the sidewall insulating film 26 by about 20 nm on one side. .

When the side wall portion of the metal film 18 is simply etched, the cross-sectional area of the gate electrode decreases and the gate sheet resistance increases, but if the thickness of the metal film is increased, In addition, it is possible to avoid a reduction in the cross-sectional area of the gate electrode. For example, if the basic design rule is 0.
When a side wall portion of a metal film 18 having a thickness of 40 nm is etched by 10 μm on each side in a 13 μm semiconductor device,
Although the gate sheet resistance increases by about 15%, a decrease in the cross-sectional area of the gate electrode can be avoided by increasing the thickness of the metal film from 40 nm to 46 nm. As described above, since the increase in the gate sheet resistance can be avoided only by increasing the thickness of the metal film by only 6 nm, the influence on the manufacturing process can be almost ignored.

(Evaluation Result) Next, the evaluation result of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 2 is a graph showing the result of evaluating the leakage current of the semiconductor device according to the present embodiment. The horizontal axis in FIG. 2 indicates the leak current, and the vertical axis indicates the cumulative frequency. Example 1 shows the case of the semiconductor device according to the present embodiment, and Comparative Example 1
Shows the case of the proposed semiconductor device shown in FIG. 18 and FIG. Here, the leakage current is 1 × 10
If it is less than ^-9 A, it is regarded as a good product, and if the leak current is 1 × 10 ^-9 or more, it is a defective product. In both Example 1 and Comparative Example 1, the measurement was performed on a 256 kbit DRAM cell. The thickness of the sidewall insulating film is 15
nm. In Example 1, the side wall portion of the metal film immediately below the cap film was etched on one side by about 10 to 15 nm.

As can be seen from FIG. 2, in the case of the semiconductor device according to the present embodiment shown in Example 1, the leak current is kept extremely small, and at least 99.5% or more of the samples are non-defective. .

On the other hand, in the case of the proposed semiconductor device shown in Comparative Example 1, the non-defective product is only about 60% of the sample.

As described above, according to the present embodiment, even when the thickness of the sidewall insulating film is reduced to 15 nm, the leak current between the conductor plug and the gate electrode can be suppressed to a small value.

(The Method for Fabricating the Semiconductor Device) Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 3 to 6 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.

First, as shown in FIG. 3A, a gate insulating film 12 made of a silicon oxynitride film having a thickness of 4.5 nm is formed on a silicon substrate 10. Gate insulating film 12
Is, for example, wet oxidizing the surface of the silicon substrate 10,
After that, it can be formed by performing a heat treatment in an NO gas atmosphere.

Next, on the silicon substrate 10 on which the gate insulating film 12 has been formed, a 70-nm-thick
An m-th polysilicon film 14 is formed.

Next, an impurity is introduced into the polysilicon film 14 by ion implantation.

Next, a buffer film 16 made of WN having a thickness of 5 nm is formed on the polysilicon film 14 by, for example, a sputtering method. Here, a WN film is deposited,
By the heat treatment in the post-process, WN and Si react,
It becomes a WSiN film.

Next, a 40 nm-thick tungsten metal film 18 is formed on the buffer film 16 by, for example, a sputtering method.

Next, a cap film 22 made of a 200-nm-thick silicon nitride film is formed on the metal film 18 by, for example, a CVD method.

Next, a photoresist film is formed on the entire surface by spin coating. Thereafter, the photoresist film is patterned by using the photolithography technique, thereby forming a photoresist mask 36 for forming the gate electrode 20 (see FIG. 3B).

Next, the cap film 22 is anisotropically etched by RIE using the photoresist mask 36 as a mask. Thereafter, the photoresist mask 36 is removed by ashing (see FIG. 3C).

Next, the metal film 18 and the buffer film 16 are etched by RIE using the cap film 22 as a mask. At this time, an etching condition having an isotropic component is set. By setting the etching conditions having an isotropic component, the metal film 18 immediately below the cap film 22 can be formed.
In addition, the side wall portion of the buffer film 16 can be etched. Metal film and buffer film 1 immediately below cap film 22
6 is etched, for example, by about 15 nm. Note that the etching is not limited to using the RIE method, and acid-based or alkali-based wet etching may be used. Further, after the metal film 18 and the buffer film 16 are anisotropically etched by the RIE method, wet etching may be performed to etch the side wall portions of the metal film 18 and the buffer film 16 immediately below the cap film 22. (See FIG. 4A).

Next, the polysilicon film 14 is anisotropically etched by RIE using the cap film 22 as a mask. In this manner, a gate electrode 20 having a polymetal structure composed of the polysilicon film 14, the buffer film 16, and the metal film 18 whose upper surface is covered with the cap film 22 is formed.

Next, the exposed surface of the polysilicon film 14 is selectively oxidized by, for example, a thermal oxidation method. Thus, a silicon oxide film 15 is formed on the exposed surface of the polysilicon film 14 (see FIG. 4B).

Next, ion implantation is performed by self-alignment with the gate electrode 20 whose upper surface is covered with the cap film 22, thereby forming source / drain diffusion layers 28 and 29 on the silicon substrate 10 on both sides of the gate electrode 20. Forming (FIG. 4C)
reference).

Next, a 10 nm-thick silicon nitride film 24 is formed on the entire surface by, eg, CVD. After this,
The silicon nitride film 24 is anisotropically etched by RIE.

Next, a 10 nm-thickness silicon nitride film 25 is formed on the entire surface by, eg, CVD.

Thus, a sidewall insulating film 26 composed of the silicon nitride film 24 and the silicon nitride film 25 is formed on the side surface of the gate electrode 20 whose upper surface is covered with the cap film 22.

Next, in a nitrogen atmosphere, for example, at 950 ° C.
A heat treatment for 10 seconds is performed, and the source / drain diffusion layers 28
Activate the ions introduced into 29.

Thus, the gate electrode 2 having a polymetal structure is formed.
0 is formed (FIG. 5)
(A)).

Next, a 400 nm-thick BPSG film 30 is formed on the entire surface by, eg, CVD. Thereafter, the BPSG film 30 is flattened by performing a heat treatment in an oxygen atmosphere at 800 ° C. for 30 minutes, for example. Thereafter, for example, CMP (Chemical Mechanical Polishing: Chemical Mechanical Polishing)
Polishing), the BPSG film 30 is polished until the cap film 22 is exposed (see FIG. 5B).

Next, a photoresist film is formed on the entire surface by spin coating. Thereafter, the photoresist film is patterned by using the photolithography technique, thereby forming a photoresist mask 40 having an opening 38 for performing SAC.

Next, the BPSG film 30 is etched by the RIE method using the photoresist mask 40 as a mask, and the silicon nitride film 25 is anisotropically etched to form contact holes reaching the source / drain diffusion layers 29. 32 are formed. In the process of forming the contact hole 32, a part of the sidewall insulating film 26 at the shoulder of the gate electrode 20 and a part of the cap film 22 are locally etched (see FIG. 5C).

Next, a polysilicon film doped with, eg, P is formed on the entire surface by, eg, CVD. Thereafter, the surface of the cap film 22 is polished by, for example, a CMP method until the cap film 22 is exposed, and the conductor plug 34 made of a polysilicon film having a planarized surface is inserted into the contact hole 32.
(See FIG. 6).

Thus, the semiconductor device according to the present embodiment is manufactured.

As described above, according to the present embodiment, since the side wall portion of the metal film immediately below the cap film is etched, the side surface of the metal film is located inside the side surface of the cap film, and the side wall insulation on the side surface of the metal film is etched. An effective film thickness of the film can be ensured to be large. Therefore, according to the present embodiment, it is possible to reduce the thickness of the sidewall insulating film while suppressing the leakage current between the conductor plug and the gate electrode, and to contribute to miniaturization of the semiconductor device. it can.

[Second Embodiment] The semiconductor device and the method for fabricating the same according to a second embodiment of the present invention will be explained with reference to FIGS. FIG. 7 is a sectional view of the semiconductor device according to the present embodiment. 8 to 11 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. FIG.
The same components as those of the semiconductor device according to the first embodiment and the method of manufacturing the same shown in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

In the semiconductor device according to the present embodiment, the metal film 1
8, an amorphous silicon film is formed on the side surface, and thereafter,
The main feature is that the side wall portion of the metal film 18 is changed to a metal silicide film by performing the heat treatment, and then the metal silicide film is etched to remove the side wall portion of the metal film 18 immediately below the cap film 22. There is.

The semiconductor device according to the present embodiment is basically the same as the semiconductor device according to the first embodiment, except that a silicon oxide film 42 is formed on the side surface of the cap film 22 according to the first embodiment. It is different from a semiconductor device.
The reason why the silicon oxide film 42 is formed on the side surface of the cap film 22 is due to the method of manufacturing the semiconductor device according to the present embodiment described later.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

In the method for fabricating the semiconductor device according to the present embodiment, up to the step of etching the cap film 22,
Since the method is the same as the method for fabricating the semiconductor device according to the first embodiment shown in FIGS.

Next, using the cap film 22 as a mask, the metal film 18 and the buffer film 16 are anisotropically etched (see FIG. 8A).

Next, an amorphous silicon film 44 of, eg, a 15 nm-thickness is formed on the entire surface by, eg, CVD (see FIG. 8B).

Next, a metal silicide film 46 made of tungsten silicide is formed, for example, by performing a heat treatment at 800 ° C. for 30 minutes (see FIG. 8C).

Next, the metal silicide film 46 is etched using an HF-based etchant (see FIG. 9A).

Next, the polysilicon film 14 is anisotropically etched by RIE using the cap film 22 and the amorphous silicon film 44 as a mask. Cap film 22
The amorphous silicon film 44 will remain on the side surfaces of.

Next, the amorphous silicon film 44 remaining on the side surface of the cap film 22 is oxidized by, for example, thermal oxidation, and the exposed surface of the polysilicon film 14 is selectively oxidized. Thereby, the amorphous silicon film 44 is oxidized to become the silicon oxide film 42, and the silicon oxide film 15 is formed on the exposed surface of the polysilicon film 14 (see FIG. 9B).

Next, ion implantation is performed in a self-alignment manner with the gate electrode 20 whose upper surface is covered with the cap film 22, thereby forming the source / drain diffusion layer 2 on the silicon substrate 10.
8 and 29 are formed (see FIG. 9C).

The subsequent method of manufacturing the semiconductor device will be described with reference to FIG.
Since the method is the same as the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS.
(See (a) to FIG. 11).

Thus, the semiconductor device according to the present embodiment is manufactured.

As described above, the side wall portion of the metal film immediately below the cap film can also be removed by changing the side wall portion of the metal film to a metal silicide film and thereafter etching the metal silicide film. Therefore, according to this embodiment, a semiconductor device similar to that of the first embodiment can be provided.

[Third Embodiment] The semiconductor device and the method for fabricating the same according to a third embodiment of the present invention will be explained with reference to FIGS. FIG. 12 is a sectional view of the semiconductor device according to the present embodiment. 13 to 16 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. The same components as those of the semiconductor device according to the first embodiment or the second embodiment shown in FIGS. 1 to 11 and the method of manufacturing the same will be denoted by the same reference numerals, and description thereof will be omitted or simplified.

(Semiconductor Device) First, the semiconductor device according to the present embodiment will be explained with reference to FIG.

The semiconductor device according to the present embodiment is characterized mainly in that the principle of the present invention is applied to a multilayer wiring.

On the semiconductor substrate 48, a MOS transistor and the like (not shown) are formed. On a semiconductor substrate 48 on which MOS transistors and the like are formed, an interlayer insulating film 50 made of BPSG is formed.

On the interlayer insulating film 50, a lower wiring 52 made of, for example, tungsten is formed. Lower layer wiring 5
2 is formed on the interlayer insulating film 50 on which
Are formed. On the interlayer insulating film 54, an intermediate wiring 56 made of, for example, tungsten is formed. On the intermediate wiring 56, a cap film 58 is formed.

A side wall insulating film 59 made of a silicon nitride film is formed on the side surface of the intermediate wiring 56 and the side surface of the cap film 58.

An interlayer insulating film 60 is formed between the cap films 58 on the interlayer insulating film 54 and between the intermediate wires 56. An upper wiring 62 is formed on the interlayer insulating film 60 and the cap film 58.

In the interlayer insulating film 60, a contact hole 64 reaching the lower wiring 52 is self-aligned with the cap film 58.
Are formed. A conductor plug 66 made of, for example, tungsten is buried in the contact hole 64. The upper wiring 62 is electrically connected to the lower wiring 52 via the conductor plug 66.

The semiconductor device according to the present embodiment is characterized mainly in that the side wall portion of the intermediate wiring 56 immediately below the cap film 58 is etched, and the side wall insulating film 59 is formed in this portion. In the present embodiment, the side wall insulating film 59 is buried in the portion where the intermediate wiring 56 directly below the cap film 58 is etched, so that the side surface of the intermediate wiring 56 can be covered with the thick side wall insulating film 59. Since the side surface of the intermediate wiring 56 can be covered with the thick sidewall insulating film 59, while suppressing the leakage current between the conductor plug 66 and the intermediate wiring 56,
A semiconductor device having fine multilayer wiring can be provided.

(The Method for Fabricating the Semiconductor Device) Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, the entire surface of the semiconductor substrate 48 on which the interlayer insulating film 50 is formed is formed by, for example, sputtering.
A metal film 52 made of tungsten having a thickness of 30 nm is formed. After that, the metal film is patterned by using the photolithography technique, and thereby the lower wiring 52 is formed.

Next, an interlayer insulating film 54 of a 200 nm-thickness silicon nitride film is formed on the entire surface by, eg, CVD.
To form

Next, the entire surface is formed by, for example, a sputtering method.
A metal film 68 made of tungsten having a thickness of 30 nm is formed.

Next, a cap film 58 made of a 200-nm-thick silicon nitride film is formed on the entire surface by, eg, CVD.
Is formed (see FIG. 13A).

Next, a photoresist film is formed on the entire surface by spin coating. Thereafter, the photoresist film is patterned by using the photolithography technique, thereby forming a photoresist mask 70 for forming the intermediate wiring 56 (see FIG. 13B).

Next, the cap film 58 is anisotropically etched by RIE using the photoresist mask 70 as a mask.

Next, the metal film 68 is etched by RIE using the cap film 58 as a mask. On this occasion,
Etching conditions having isotropic components are set. Since the metal film 68 is etched under the etching condition having an isotropic component, the side wall portion of the metal film 68 immediately below the cap film 58 can be etched. The side wall portion of the metal film 68 immediately below the cap film 58 is etched, for example, by about 20 nm. Thus, the side surface of the intermediate wiring 56 is located inside the side surface of the cap film 58 (FIG. 14).
(A)). Note that not only the RIE method but also an acid-based or alkali-based wet etching may be used. Also,
After the metal film 58 is anisotropically etched by the RIE method, the metal film 58 is wet-etched,
The side wall portion of the metal film 68 immediately below the cap film 58 may be removed.

Next, a 20-nm-thick silicon nitride film is formed on the entire surface by, eg, CVD. After this, RI
The silicon nitride film is anisotropically etched by the E method, whereby the side wall insulating film 5 made of the silicon nitride film is formed on the side surfaces of the intermediate wiring 56 and the cap film 58.
9 is formed.

Next, a BPSG film having a thickness of 400 nm is formed on the entire surface by, eg, CVD. After this, CMP
The surface is polished by the method until the cap film 58 is exposed to form an interlayer insulating film 60 made of a BPSG film whose surface is flattened (see FIG. 14B).

Next, a photoresist film is formed on the entire surface by spin coating. After that, the photoresist film is patterned by using the photolithography technique, whereby the opening 72 larger than the contact hole 64 is formed.
15 is formed (FIG. 15)
(A)).

Next, a photoresist mask 74 having sidewall insulating films 59 formed on the side surfaces by RIE.
Is used as a mask, interlayer insulating film 60 is etched. Thereby, the lower wiring 52 is self-aligned with the cap film 58.
Is formed. Since the side surface of the intermediate wiring 56 is located inside the side surface of the cap film 58, the thick sidewall insulating film 59 is left on the side surface of the intermediate wiring 56. The thick sidewall insulating film 59 left on the side surface of the intermediate wiring 56 insulates the intermediate wiring 56 from the conductor plug 66 (see FIG. 15B).

Next, a film thickness of 45 was formed on the entire surface by CVD.
A 0 nm tungsten film is formed. After that, the surface is polished by the CMP method until the cap film 58 is exposed, thereby forming a conductor plug 66 made of tungsten in the contact hole 64 (see FIG. 16A).

Next, the entire surface was formed to a thickness of 5 by a sputtering method.
0 nm TiN film, 10 nm Ti film, 300 film thickness
An Al-Cu film having a thickness of 10 nm, a TiN film having a thickness of 10 nm, and a Ti film having a thickness of 10 nm are sequentially formed. Thereby, Ti
/ TiN / Al-Cu / Ti / TiN is formed as a metal film. After that, the metal film is patterned by using the photolithography technique, thereby forming the upper wiring 62.

Thus, the semiconductor device according to the present embodiment is manufactured.

[Modified Embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

For example, in the first and second embodiments, the case where the leakage current between the gate electrode and the conductor plug is reduced has been described as an example. However, the leakage current between the multilayer wiring and the conductor plug is reduced. The case can also be applied. In this case, a wiring having a polymetal structure in which a cap film is formed on the upper surface is formed, a sidewall portion of the metal film immediately below the cap film is etched, and then a side surface is formed on a side surface of the wiring having the cap film formed on the upper surface. What is necessary is just to form a wall insulating film.

Further, in the third embodiment, the side wall portion of the metal film forming the intermediate wiring is removed by setting the etching conditions having isotropic components, but the technique of the second embodiment is applied. Is also good. That is, the side wall of the metal film forming the intermediate wiring may be changed to a metal silicide film, and the metal silicide film may be etched to remove the side wall of the metal film forming the intermediate wiring.

In the first to third embodiments, the side wall portion of the metal film immediately below the cap film is uniformly etched. However, it is not always necessary to uniformly etch the side wall portion of the metal film immediately below the cap film. As shown in FIG. 17, only a part of the side wall of the metal film immediately below the cap film may be etched. Even when only a part of the side wall portion of the metal film immediately below the cap film is etched as described above, the portion of the sidewall insulating film between the metal film and the conductor plug where the current is most likely to leak. At the shoulder portion of the gate electrode, a large effective film thickness of the sidewall insulating film can be secured.

In the third embodiment, the sidewall insulating films 59 are formed on the side surfaces of the intermediate wiring. However, the sidewall insulating films 59 need not always be formed. That is,
When the material of the intermediate wiring is compatible with the material of the interlayer insulating film 60, the interlayer insulating film 60 is buried in the side wall portion of the intermediate wiring immediately below the cap film without forming the sidewall insulating film 59, and the interlayer insulating film 60 is formed. A sidewall insulating film for insulating the intermediate wiring and the conductor plug by the film 60 may be formed.

In the first embodiment, after etching the metal film 18 immediately below the cap film 22 and the side wall portions of the buffer film 16 under isotropic etching conditions, the polysilicon film 14 is etched using the cap film 22 as a mask. Although the anisotropic etching is performed, the side wall portions of the metal film 18 and the buffer film 16 immediately below the cap film 22 may be etched any time before the formation of the sidewall insulating film 24. For example, after the metal film 18, the buffer film 16, and the polysilicon film 14 are anisotropically etched by the RIE method, an acid or alkali wet etching is performed.
The side wall portions of the metal film 18 and the buffer film 16 immediately below the cap film 22 may be etched.

[0114]

As described above, according to the present invention, since the side wall portion of the metal film immediately below the cap film is etched, the side surface of the metal film is located inside the side surface of the cap film, The effective thickness of the wall insulating film can be increased. Thus, according to the present invention,
It is possible to reduce the thickness of the sidewall insulating film while suppressing the leakage current between the conductor plug and the gate electrode, and to contribute to miniaturization of the semiconductor device.

Further, according to the present invention, the side wall insulating film is formed thick in the portion where the intermediate wiring immediately below the cap film is etched, so that the leakage current between the conductor plug and the intermediate wiring can be suppressed. Thus, a semiconductor device having fine multilayer wiring can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a graph showing a result of evaluating a leakage current of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a process sectional view (part 4) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a sectional view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 8 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a process sectional view (part 4) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 13 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the third embodiment of the present invention.

FIG. 14 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the third embodiment of the present invention.

FIG. 15 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the third embodiment of the present invention.

FIG. 16 is a process sectional view (part 4) illustrating the method for fabricating the semiconductor device according to the third embodiment of the present invention.

FIG. 17 is a sectional view showing a semiconductor device according to a modified embodiment of the present invention.

FIG. 18 is a process sectional view (part 1) illustrating the proposed method for manufacturing the semiconductor device;

FIG. 19 is a process sectional view (2) showing the proposed method of manufacturing the semiconductor device;

FIG. 20 is a graph showing measurement results of a leak current of a proposed semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 12 gate insulating film 14 polysilicon film 15 silicon oxide film 16 buffer film 18 metal film 20 gate electrode 22 cap film 24 silicon nitride film 25 silicon nitride film 26 sidewall insulation Film 28 source / drain diffusion layers 28a, 28b impurity diffusion region 29 source / drain diffusion layers 29a, 29b impurity diffusion region 30 BPSG film 32 contact hole 34 conductor plug 36 photoresist mask 38 opening Reference Signs List 40 ... Photoresist mask 42 ... Silicon oxide film 44 ... Amorphous silicon film 46 ... Metal silicide film 48 ... Semiconductor substrate 50 ... Interlayer insulating film 52 ... Lower layer wiring 54 ... Interlayer insulating film 56 ... Intermediate wiring 58 ... Cap film 59 ... Sidewall Insulating film 60 ... Interlayer insulating film 62 Upper layer wiring 64 Contact hole 66 Conductor plug 68 Metal film 70 Photoresist mask 72 Opening 74 Photoresist mask 110 Silicon substrate 112 Gate insulating film 114 Polysilicon film 115 Silicon oxide film 116 Buffer Film 118 metal film 120 gate electrode 122 cap film 124 silicon nitride film 125 silicon nitride film 126 sidewall insulating film 128 source / drain diffusion layers 128a and 128b impurity diffusion regions 129 source / drain diffusion layers 129a, 129b ... impurity diffusion region 130 ... BPSG film 132 ... contact hole 134 ... conductor plug

Continued on front page F-term (reference) 4M104 AA01 BB01 BB14 BB18 BB28 BB33 CC01 CC05 DD02 DD04 DD08 DD17 DD19 DD37 DD43 DD55 DD64 DD65 DD66 DD71 DD75 DD78 DD84 DD86 DD88 EE05 EE08 EE09 EE14 EE15 EE17 FF04 GG13H18 FF13 GG13H18H 5F004 AA06 AA12 BA04 DB02 DB06 DB07 DB08 EA11 EB01 5F033 HH04 HH09 HH18 HH19 HH32 HH33 JJ04 JJ19 KK01 KK19 LL04 MM08 NN01 NN32. XX03 XX15 XX31

Claims (5)

[Claims] A wiring layer having a first conductive film formed on a substrate, a second conductive film formed on the first conductive film, and a cap formed on the wiring layer. A film, an insulating film formed on at least a side surface of the wiring layer, and a conductor plug adjacent to the wiring layer with the insulating film interposed therebetween, wherein the side surface of the second conductive film is the first conductive film. A semiconductor device, which is located inside a side surface of a conductive film and a side surface of the cap film. 2. A step of forming a wiring layer on a substrate, the upper surface of which is covered with a cap layer and at least a part of a side surface is located inside a side surface of the cap layer, and an insulating film on at least a side surface of the wiring layer. Forming a conductive plug adjacent to the wiring layer with the insulating film interposed therebetween. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the step of forming the wiring layer includes the step of forming the conductive film including a metal film on the substrate, and the step of forming a cap film on the conductive film. Forming a cap film and the conductive film, forming a silicon film on a side surface of the metal film, and reacting the metal film and the silicon film to form the metal film. Forming a metal silicide film on a side surface; and selectively removing the metal silicide film to form the wiring layer in which at least a part of the side surface is located inside the side surface of the cap film. A method for manufacturing a semiconductor device, comprising: 4. The method for manufacturing a semiconductor device according to claim 2, wherein the step of forming the wiring layer includes the step of forming a conductive film on the substrate and the step of forming the cap having a predetermined pattern on the conductive film. The step of forming a film and the etching conditions in which etching proceeds in the horizontal direction, the conductive film is etched using the cap film as a mask, and the wiring layer whose side surface is located inside the side surface of the cap film is removed. Forming the insulating film, wherein, in the step of forming the insulating film, the insulating film is formed so as to be buried between the cap film and the wiring layer, and the step of forming the conductor plug is formed on the cap film. Forming a mask having a predetermined pattern, and etching the insulating film using the mask and the cap film, and remaining on the side surface of the wiring layer Forming a contact hole separated from the wiring layer by the insulating film; and forming the conductor plug in the contact hole. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the wiring layer includes the step of forming a conductive film on the substrate and the step of forming the cap having a predetermined pattern on the conductive film. The step of forming a film and the etching conditions in which etching proceeds in the horizontal direction, the conductive film is etched using the cap film as a mask, and the wiring layer whose side surface is located inside the side surface of the cap film is removed. Forming a first insulating film on at least a side surface of the wiring layer; and forming the first insulating film so as to be embedded between the cap film and the wiring layer. Forming a second insulating film different from the first insulating film, wherein the step of forming the conductor plug forms a mask having a predetermined pattern on the cap film. And etching the second insulating film using the mask and the cap film to form a contact hole separated from the wiring layer by the first insulating film remaining on the side surface of the wiring layer. A method for manufacturing a semiconductor device, comprising: a step of forming the conductor plug in the contact hole.