JPH06208968A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method for a semiconductor device wherein, even if integration of elements further proceeds, drop of reliability resulting from a contact part and drop of products yield are prevented. CONSTITUTION:A process where an inter-layer insulation film 313 is formed on an impurities diffusion layer 312 formed on a silicon substrate 311, a process where an opening part is formed on the inter-layer insulation film 313 on the impurities diffusion layer 312, and a process where, by removing a method oxidation film on the surface of the impurities diffusion layer 312 of the opening part, a polysilicon film 315, that contacts the impurity diffusion layer 312, containing impurities of the same conductivity type as the impurities diffusion layer 312 is formed, are comprised. And further, a process, where a wiring layer 316 wherein the contact area with the polysilicon film 315 is larger than that between the impurities diffusion layer 312 and polysilicon film 315 is formed, is comprised.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a contact hole.

[0002]

2. Description of the Related Art In recent years, a large-scale integrated circuit formed by integrating a large number of transistors, resistors, etc., on one chip in an important part of a computer or communication equipment so as to achieve an electric circuit ( LSI) is frequently used. Therefore, the performance of the entire device is largely linked to the performance of the LSI alone.

Since improvement of the performance of a single LSI can be realized by increasing the degree of integration, that is, miniaturization of elements, patterning of wiring such as gate wiring is performed near the resolution limit of lithography technology.

For this reason, it is becoming difficult to pattern the contact holes according to the same design rule as the wiring pattern. In particular, in a region where the degree of integration is advanced, such as a memory cell region of a DRAM including a transistor and a capacitor, a contact margin with a wiring is very small.

Therefore, patterning has come to be performed in a self-aligned manner so that a contact hole is formed in the wiring. Such contacts are SACs (Self Alien Conta
ct). Although SAC is effective in miniaturizing the area occupied by the element, there is a problem that a short circuit easily occurs between a wiring such as a gate wiring and a contact. To solve this problem, Stopper Poli (SP)
A method called scheme was proposed.

This method will be described with reference to FIG. Figure 5
FIG. 4A is a process sectional view when the SP method is applied to the manufacture of a DRAM, in which the left side shows the memory cell region and the right side shows the peripheral circuit region.

First, as shown in FIG. 5A, a gate insulating film 132 is formed in the element formation region of the semiconductor substrate 130 divided by the field insulating film 131. Then, after depositing a polysilicon film 133 to be a gate wiring (gate electrode) on the gate insulating film 132, the surface of the polysilicon film 133 is oxidized and oxidized in order to improve the withstand voltage with respect to other wiring layers. A film 134 is formed, and then a silicon nitride film 135 is formed on the oxide film 134.

Next, as shown in FIG. 5B, after the polysilicon film 133 is processed into a gate wiring shape, an impurity diffusion layer 151 is formed by ion implantation. Next, in order to improve the reliability of the gate insulating film 132, the gate wiring 1
The side surface 33 and the surface of the semiconductor substrate 130 are oxidized to form an oxide film 136.

Next, as shown in FIG. 5C, after depositing a silicon nitride film 137 on the entire surface, the silicon nitride film 137 is left only on the side wall of the gate wiring portion by etching. Then, in order to form the LDD structure in the peripheral circuit region, the deep impurity diffusion layer 15 is formed in the shallow impurity diffusion layer 151.
Form 2.

Next, as shown in FIG. 6A, a silicon nitride film 138 is deposited on the entire surface in order to prevent the semiconductor substrate 103 from being oxidized in a later step, and then the silicon nitride film 1 is deposited.
A polycrystalline silicon film 139 is deposited on 38. Next in FIG.
As shown in (b), as an interlayer insulating film 140, B is formed on the entire surface.
A fusible insulating film such as PSG is deposited.

Next, taking advantage of the high etching selection ratio between the polycrystalline silicon film 139 and the interlayer insulating film 140, FIG.
As shown in (c), after the interlayer insulating film 140 is selectively etched until the polycrystalline silicon film 139 is exposed,
For example, the exposed polycrystalline silicon film 139 is removed by chemical dry etching. Next, the semiconductor substrate 139 is heated in an oxidizing atmosphere to planarize the interlayer insulating film 140 and oxidize the remaining polycrystalline silicon film 139 to form the insulating film 141. Next, the exposed silicon nitride film 138 in the memory cell region is selectively removed to expose the surface of the shallow impurity diffusion layer 151,
Form a contact hole.

Next, as shown in FIG. 7A, a resist pattern is formed and the insulating films 140 and 138 are selectively removed to expose the surface of the deep impurity diffusion layer 152 and form a contact hole. To do. Finally, as shown in FIG. 7B, the wiring 42 that contacts the impurity diffusion layers 151 and 152 is formed. However, the SP method has a problem that the number of steps is larger than that in the case of the conventional non-SAC and the product yield is reduced.

Further, since it is not necessary to use the SP method in the peripheral circuit region having a contact margin, it is necessary to remove the polycrystalline silicon 139 as the stopper film in the process step of FIG. 6B. This is because even if the stopper film (polycrystalline silicon 139) is heated, the insulating film 141 cannot be completely formed, and the contact conduction defect caused by the remaining polycrystalline silicon is prevented. Further, since the memory cell region using the SP method and the peripheral circuit region not using the SP method have different film structures, the etching conditions are also different. Therefore, it is necessary to perform the etching of the memory cell region and the peripheral circuit region in separate steps as in the steps of FIGS. 6C and 7A. As described above, in addition to the large number of steps in the SP method itself, there is an increase in the number of steps due to the application to the DRAM.

Furthermore, according to the conventional SP method, as shown in FIG.
Since the silicon nitride film 135 formed in the step of (a) is oxidized when the oxide film 136 is formed in the step of FIG. 5B, the side wall of the gate electrode portion is formed in the step of FIG. 5C. The adhesiveness with the silicon nitride film 137 formed on the substrate becomes low.
Since such deterioration of adhesion causes a decrease in withstand voltage, the wiring layer 142 in the contact hole and the gate wiring 1 are
This causes a short circuit with 53 and causes a decrease in manufacturing yield. FIG. 15 is a diagram showing another conventional method of forming a contact hole.

In FIG. 15A, a contact layer 222 such as an impurity diffusion layer is formed on the surface of a semiconductor substrate 221.
An interlayer insulating film 224 is formed on the contacted layer 22.
2 is an element cross-sectional view of a portion where a wiring layer 223 electrically separated from 2 is provided. FIG. In order to form a wiring layer that contacts the contacted layer 222, first, FIG.
A photoresist pattern 225 is formed as shown in FIG.

Next, as shown in FIG. 15C, the interlayer insulating film 22 is formed using the photoresist pattern 225 as a mask.
4 is etched to form a contact hole 226. Finally, as shown in FIG. 15D, a wiring layer 227 that contacts the contacted layer 222 is formed. However, this type of contact hole forming method has the following problems.

That is, in the semiconductor device with high density and high integration, since the contact hole is miniaturized, the alignment margin between the wiring layer 223 and the contact hole 226 becomes small, as shown in FIG. As shown, the wiring layer 223 is exposed by the etching of the interlayer insulating film 224 when the contact hole is opened. Therefore, as shown in FIG. 15D, the wiring layer 223 is
The contacted layer 222 is contacted via the wiring layer 227. That is, a short circuit occurs at the contact portion.

In order to prevent such problems, attempts have been made to improve the alignment accuracy of the lithographic apparatus. However, since the alignment accuracy greatly depends on the mechanical accuracy of the lithographic apparatus, it is very difficult to improve the alignment accuracy.

Although a sufficient alignment margin can be secured by increasing the distance between the contact hole and the wiring layer, in this case, there is a problem that the chip becomes large and the product yield decreases.

Further, without causing a problem such as a short circuit,
Even if a fine contact hole can be formed, the contact area will be small and the contact resistance will increase.
A new problem arises that the capacity of the semiconductor chip decreases. FIG. 16 is a device cross-sectional view of a contact hole portion obtained by a conventional method. This will be described according to the manufacturing process. First, the interlayer insulating film 353 is formed on the semiconductor substrate 351 on the surface of which the diffusion layer 352 is selectively formed. Next, after opening a contact hole in the interlayer insulating film 353 on the region of the diffusion layer 352, the first contact hole is formed in the contact hole.
The conductor layer 355 is selectively formed. Next, after depositing the second conductor layer 356 on the entire surface, the second conductor layer 356 is processed into a wiring shape.

In the case of such a method, in order to prevent an increase in contact resistance due to the miniaturization of the contact hole, a new material having a small contact resistance as the conductive material of the first conductive film 355 and the second conductive film 356. Need to be used.

However, such a new material does not match well with the conventional method, and further, in order to use the new material,
It was necessary to add a new process to the conventional process. Therefore, there is a problem that the product yield is reduced due to the increase in the number of steps. Further, there has been a problem that development costs increase due to the development of new materials and the technological development required for new processes.

[0023]

As described above, the conventional S
The P method is complicated and has a large number of steps, and further, the adhesion between the silicon nitride film on the upper portion of the gate wiring portion (gate electrode portion) and that on the side wall portion is deteriorated, which causes a problem that the manufacturing yield is reduced.

Further, in the conventional method of forming a contact hole, the alignment margin becomes smaller with the miniaturization of the element, so that the wiring layer in the interlayer insulating film is exposed when the contact hole is opened, There is a problem that the wiring layer in the contact hole and the wiring layer in the interlayer insulating film are short-circuited.

Further, in the method of avoiding the increase in contact resistance due to the miniaturization of the contact hole by using the new conductor material, the new material does not match well with the conventional method, and moreover, it is necessary to use the new material. It was necessary to add a new process. Therefore, there is a problem that the number of processes increases and the product yield decreases.

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to prevent a decrease in reliability and a decrease in product yield due to a contact portion even if the integration of elements progresses. It is to provide a method for manufacturing a semiconductor device.

[0027]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention (claim 1) comprises:
A step of depositing a first interlayer insulating film having a uniform film thickness on the entire surface of the semiconductor substrate having a contact layer formed between the first conductor layers; A film thickness of the peripheral portion is thicker than a film thickness of the central portion between the conductor layers.
The step of depositing the third interlayer insulating film, the step of forming the third interlayer insulating film on the second interlayer insulating film, and the step of forming the third interlayer insulating film before forming the third interlayer insulating film. Forming a stopper film having resistance to etching of the insulating film on the second interlayer insulating film; etching the third interlayer insulating film; A step of forming a large opening in the third interlayer insulating film on the contacted layer, and forming a large opening between the first conductor layers on the semiconductor substrate;
The second conductor layer is formed so as to contact the contacted layer electrically separated from the conductor layer.

Another method of manufacturing a semiconductor device according to the present invention (claim 2) includes a step of forming a conductor layer formed on a semiconductor substrate and contacting a contacted layer covered with an interlayer insulating film. In the method of manufacturing a device, the step of forming an opening for connecting the contacted layer and the conductor layer in the interlayer insulating film includes the step of forming an auxiliary mask film on the interlayer insulating film, Forming a first resist pattern for the opening on the mask film; etching the auxiliary mask film using the first resist pattern as a mask; and a reaction product generated by the etching by the etching. A step of depositing on the inner wall surface of the opening to be formed to form a second resist pattern having an opening area smaller than that of the first resist pattern; Characterized in that comprising the step of etching the interlayer insulating film of this second resist pattern as a mask.

Another method of manufacturing a semiconductor device according to the present invention (claim 3) is the step of forming an interlayer insulating film on the first conductor layer formed on the semiconductor substrate, and the first conductor layer. A step of forming an opening in the upper interlayer insulating film; and a step of contacting the first conductor layer under the condition that an interfacial resistance increasing substance is not formed on the surface of the first conductor layer in the opening. And a step of forming a third conductor layer in which a contact area with the second conductor layer is larger than a contact area between the first conductor layer and the second conductor layer. And having. Here, the interfacial resistance increasing substance refers to a substance that increases the interfacial resistance on the surface of the first conductor layer, such as a natural oxide film.

[0030]

According to the method of manufacturing a semiconductor device of the present invention (claim 1), the first interlayer insulating film having a uniform film thickness is deposited on the entire surface. That is, the first conductor layer is covered with the first interlayer insulating film having good coverage and no breaks. Therefore, the withstand voltage of the first conductor layer is improved.

Further, in the present invention, the second interlayer insulating film is deposited on the first interlayer insulating film such that the film thickness of the peripheral portion between the conductor layers is thicker than the film thickness of the central portion between the conductor layers. Therefore, in the entire surface etching step, the opening can be formed in the first conductor layer in a self-aligned manner without causing a short circuit.

According to another method of manufacturing a semiconductor device of the present invention (claim 2), after forming a first resist pattern for an opening, the auxiliary mask film is etched using the first resist pattern as a mask. At the same time, the reaction product generated by this etching is deposited on the inner wall surface of the opening formed by the above etching to form a second resist pattern having an opening area smaller than that of the first resist pattern.

Therefore, a fine opening can be formed by etching the interlayer insulating film using the second resist pattern as a mask. Therefore, even if the contact margin is reduced due to the miniaturization of the element, the wiring and the like in the interlayer insulating film are not exposed by being etched when the opening is formed, so that a short circuit at the contact portion can be prevented.

Further, according to another method of manufacturing a semiconductor device of the present invention (claim 3), the first conductor layer is provided under the condition that a natural oxide film or other interfacial resistance increasing substance is not formed on the surface of the first conductor layer. Since the second conductor layer that contacts the first conductor layer is formed, the contact resistance between the first conductor layer and the second conductor layer can be sufficiently reduced. Therefore, the contact area between the third conductor layer and the second conductor layer can be regarded as the contact area between the third conductor layer and the first conductor layer. Further, in the present invention, the contact area between the third conductor layer and the second conductor layer is larger than the contact area between the second conductor layer and the first conductor layer (that is, the opening area of the opening). Thus, the third conductor layer is formed. Therefore, the contact resistance can be reduced because the third conductor layer contacts the first conductor layer with a contact area larger than the opening area.

[0035]

Embodiments will be described below with reference to the drawings. 1 to 3 show a DRA according to a first embodiment of the present invention.
It is a figure which shows the manufacturing method of M. In the figure, the left side shows the memory cell area and the right side shows the peripheral circuit area.

First, as shown in FIG. 1A, after a well (not shown) is formed on a silicon substrate 110, a field insulating film 111 is formed, and the surface of the silicon substrate 110 is separated into element isolation regions and elements. It is divided into a formation area. Then, ion implantation is performed for the purpose of adjusting the threshold value of the transistor. Then, a gate oxide film 112 having a thickness of about 10 nm is formed on the surface of the substrate by a thermal oxidation method, and then a polycide film 113 to be a gate wiring (first conductor layer) is formed on the gate oxide film 112. This polycide film 113
Is a polysilicon film with a thickness of 100 nm and a thickness of 1
It is assumed to be a tungsten silicide film having a thickness of 00 nm.
Next, a photoresist pattern is formed on the polycide film 113, and then the polycide film 11 is formed by reactive ion etching using this photoresist pattern as a mask.
3 is etched to form the gate wiring 113. Then, using the gate wiring 113 as a mask, ion implantation is performed to form the impurity diffusion layer 109 (contact layer) in a self-aligned manner.

Next, as shown in FIG. 1B, in order to improve the withstand voltage of the gate wiring 113 and the reliability of the gate oxide film 112, post oxidation is performed to perform gate oxidation.
A thermal oxide film 114 having a thickness of about 10 nm is formed on the surface of
Then, on the thermal oxide film 114, a silicon nitride film 115 (first interlayer insulating film) having a thickness of about 250 nm and good coverage is deposited by the LPCVD method.

Here, unlike the conventional method, the silicon nitride film 115 is formed by integrally forming the upper part of the gate wiring 113 and the side part of the gate wiring 113 in the same process. There is no problem that the withstand voltage at the upper corner of 113 is lowered. Therefore, the bit line 120 and the gate wiring 1 of FIG.
It is possible to solve the problem of the conventional method that short-circuits with 13 and decreases the reliability and product yield.

Next, as shown in FIG. 1 (c), Si is formed on the entire surface.
An O ₂ film 116 (second interlayer insulating film) is deposited by the atmospheric pressure CVD method. Here, when the film thickness of the SiO ₂ film 116 on the gate wiring 115 is 150 nm, the film thickness of the SiO ₂ film 116 between the gate wirings in which the distance between the memory cell regions is narrow is 5
It becomes about 0 nm. That is, SiO ₂ between the gate wirings
The film thickness of the film 116 is smaller than that between the gate wirings. On the other hand, the distance between the gate wirings having a wide peripheral circuit area is about 150 nm, which remains unchanged. Further, the corner portion of the gate wiring 115 has a structure covered with the SiO ₂ film 116. Then, after removing the SiO ₂ film 16 between the gate wirings in the peripheral circuit region, the MOD of the LDD structure is removed.
In order to form an S-transistor, first, etching is performed with the sidewall left unetched to form the SiO ₂ film 116 in the peripheral circuit region.
Are left only on the side wall of the gate wiring 113. After that, by forming a deep impurity diffusion layer 108 (contact layer) in the shallow impurity diffusion layer 109 by using an ion implantation method, an LDD structure MOS transistor can be formed in the peripheral circuit region.

Here, the MO of the LDD structure is obtained as follows.
An S transistor may be created. That is, SiO ₂
Without leaving the sidewall of the film 116, the silicon nitride film 1
A MOS transistor having an LDD structure may be formed by directly implanting ions after depositing 15 to form a deep impurity diffusion layer 108.

Next, as shown in FIG. 2A, a polysilicon film 11 having a thickness of about 50 nm as a stopper film is formed on the entire surface.
7 is deposited, and then B of about 200 nm thickness is formed on the entire surface.
The PSG film 118 (third interlayer insulating film) is deposited.

Next, as shown in FIG. 2B, a photoresist pattern (not shown) is formed on the BPSG film 118 by using the photolithography technique. In the memory cell region, the photoresist pattern has a BPSG opening on the impurity diffusion layer 109 that is wider than between the gate wirings.
In the peripheral circuit region, on the other hand, in the peripheral circuit region, on the deep impurity diffusion layer 108, a narrow opening about the impurity diffusion layer 108 is formed in the BPSG film 118. Then, the photoresist pattern is used as a mask to etch the BPSG film 118 by reactive ion etching to about 400 nm to form a wide opening of the BPSG film 118 in the memory cell region and a narrow opening of the BPSG film 118 in the peripheral circuit region. Form at the same time. At this time, since the polysilicon film 117 functions as a stopper film, the base is not etched.

Next, as shown in FIG. 2C, after removing the photoresist pattern for the opening, the polysilicon film 1 in the opening is formed by chemical dry etching.
17 is removed by etching. Next, by heating the silicon substrate 110 that has undergone the above steps in an oxidizing atmosphere,
The BPSG film 110 is melted to planarize the BPSG film 110, and the polysilicon film 117 is oxidized to convert the polysilicon film 117 into an insulating film (oxidized polysilicon film) 1.
Change to 19. At this time, the film thickness of the insulating film 119 on the gate wiring 113 is about 400 nm, and that between the gate wirings is about 20 nm. Here, in order to prevent the stopper film from remaining without being oxidized, it is desirable that the heat treatment in the oxidizing atmosphere is performed at a pressure of atmospheric pressure (1 atom) or more. As a result, the polysilicon remaining on the stopper film can be prevented from remaining unoxidized, and the step of removing the stopper film of the peripheral circuit portion, which has been conventionally required, can be omitted and the number of steps can be shortened.

Next, as shown in FIG. 3, the entire surface is etched to form a contact hole. At this time, the insulating film in the opening (the thermal oxide film 114, the silicon nitride film 11
5. Of the oxidized polysilicon film 119), the central part of the impurity diffusion layer 109 is thinner than the other parts, so that the central part of the impurity diffusion layer 109 is exposed first. Next, the impurity diffusion layers 108 and 109 are formed on the entire surface.
After depositing a conductive material such as tungsten to be the bit line 120 (second conductor layer) to be in contact with with a thickness of about 200 nm, the film of this conductive material is processed into a bit line shape.

Next, an insulating film which can be deposited at a low temperature on the entire surface, for example, an oxide film 121 is deposited to a thickness of 10 nm, and then the nitride film 122 and the polysilicon oxide film 12 are deposited.
3, SiO ₂ film 124 and BPSG film 125 are formed,
A contact hole for the storage node is formed by using the same method as the contact hole between the gate wirings. Also in this case, since the nitride film 122 is integrally formed in the same step, it is possible to prevent the breakdown voltage of the upper corner portion of the bit line 120 from being lowered. Therefore, it is possible to prevent a short circuit between the storage node electrode 126 and the bit line 120 which will be formed in a later step.

Next, to make a capacitor, first,
After forming a film of an electrode material to be the storage node electrode 126, the film of the above electrode material is processed so as to obtain a predetermined capacitance to form the storage node electrode 126.
Then, a capacitor insulating film 127 and a plate electrode 28 are sequentially formed on the storage node electrode 126 to complete a stack type capacitor. Finally, the interlayer insulating film 12
After depositing 9, the DRAM having the Al wiring 130 is completed.

In this embodiment, the gate line material,
The insulating film material is not limited to those described above. Further, although the capacitor is formed in the upper layer of the bit line in this embodiment, the bit line may be formed later by using the method of forming the contact hole of this embodiment in the storage node process. The method of this embodiment can also be applied to a DRAM using a trench type capacitor. Further, it can be applied to other semiconductor devices having multi-layer wiring.

Further, in this embodiment, after forming the polycide film to be the gate wiring, patterning this polycide film, subsequently oxidizing the polycide film, and then forming the insulating film on the polycide film. Alternatively, an insulating film may be formed on the polycide film, and these may be patterned and then oxidized.

If the conductive film to be the gate wiring is not suitable for the post-oxidation process such as tungsten, an insulating film that can be deposited at a low temperature may be deposited on the conductive film without performing post-oxidation. . Further, although the polysilicon film is used as the stopper film in this embodiment, an amorphous silicon film may be used instead. Next, a method of manufacturing the DRAM according to the second embodiment of the present invention will be described.

The manufacturing method of this embodiment is different from that of the previous embodiment. In the step of FIG. 2A, a P-doped polysilicon film or a B-doped polysilicon film is used as a stopper film. It is in. Both P concentration and B concentration are 1
0 ²⁰ / cm ³ The above is preferable. The film thickness is 50 nm.

When an undoped polysilicon film is used as in the previous embodiment, if the heating temperature of the polysilicon film is low, the polysilicon film is not completely oxidized and remains conductive, so that a short circuit between contacts occurs. It may occur.

On the other hand, when the polysilicon film doped with impurities as described above is used as in the present embodiment, the oxidation rate increases, so that the silicon film can be completely oxidized easily even at a low heating temperature. .

Further, instead of depositing an impurity-doped polysilicon film, an undoped polysilicon film is deposited and then an impurity such as P, B or As is doped into the polysilicon film by an ion implantation method. Is also good. At this time, the impurity concentration in the polysilicon film is 10 ²⁰ / cm ³ The above is preferable. By using a film that is easily oxidized as the stopper film as described above, it is possible to prevent the oxidation residue of the polysilicon film, which has been a problem in the related art, and thus to omit the step of removing the stopper film in the peripheral circuit section, which was conventionally necessary. Therefore, the number of steps can be shortened. Next, a method of manufacturing the DRAM according to the third embodiment of the present invention will be described.

The process up to the step of FIG. 2B is the same as that of the previous embodiment. Thereafter, as shown in FIG. 4A, the polysilicon film 117 having the exposed opening and a part of the polysilicon film 117 below the BPSG film 118 are removed by etching by chemical dry etching. Next in FIG.
As shown in (b), the polysilicon film 117 is oxidized to form an oxidized polysilicon film 143. As a result, the withstand voltage between contacts can be secured, and highly reliable SAC is possible. The subsequent steps are similar to those of the previous embodiment shown in FIG.
This is the same as (c) and subsequent steps. FIG. 8 shows a fourth embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the contact method according to the example of FIG.

First, as shown in FIG. 8A, n ⁺ is formed on the surface of the semiconductor substrate 211. Type impurity layer or p ⁺ A contact layer 212 such as a type impurity layer is formed. The semiconductor substrate 2
Wells, element isolations, transistors, etc., which are not shown, are formed on the surface 11 by well-known techniques. Next, after forming the wiring layer 213 on the semiconductor substrate 211 via the interlayer insulating film 210, the SiO ₂ -based interlayer insulating film 219 is deposited on the entire surface. Then, the surface of the interlayer insulating film 219 is planarized by polishing or the like, and then an auxiliary mask 214 made of polysilicon and having a thickness of about 50 nm is deposited on the interlayer insulating film 219.

Next, as shown in FIG. 8B, a photoresist pattern 215 (first resist pattern) for the contact hole 216 for the contacted layer 211 is formed on the auxiliary mask 214.

Next, as shown in FIG. 8C, the auxiliary mask 214 is etched by reactive ion etching using the photoresist pattern 215 as a mask. Here, a gas containing C (carbon) such as CHF ₃ + CO is used as a reactive gas, and the pressure is set to several tens to several tens.
When etching is performed in the range of 0 mTorr,
Photoresist pattern 2 in contact hole 216
15 and the reaction product 21 on the side wall of the auxiliary mask 214.
7 is deposited. As a result, the photoresist pattern 21
Auxiliary mask 21 smaller than the hole diameter of 5 by about 0.1 μm
4, photoresist pattern 215 and reaction product 2
A resist pattern (second resist pattern) of 17 is formed.

Next, as shown in FIG. 8D, the interlayer insulating films 210 and 219 are etched using the second resist pattern as a mask until the contacted layer 212 appears. At this time, since the hole diameter (opening area) of the contact hole 216 is reduced by the reaction product 217, the wiring layer 213 is not etched even if the contact hole alignment margin is reduced due to the miniaturization of the element. Absent.

Then, as shown in FIG. 8E, after removing the photoresist pattern 215 and the reaction product 217, TiSi having a thickness of 30 nm to be the wiring layer 218 is formed on the entire surface.
_Two films, a TiN film with a thickness of 70 nm and an Al film with a thickness of 30 nm are sequentially deposited. Next, a photoresist pattern (not shown) for the wiring layer 218 is formed, and by using this as a mask, the above three films are etched by reactive ion etching to form the wiring layer 218, and then the auxiliary mask 21 is formed.
4 is also etched with the same pattern. Finally, the photoresist pattern is removed to remove the contact layer 211.
The contact process between the wiring layer 218 and the wiring layer 218 is completed.

As described above, according to this embodiment, a resist pattern having a hole diameter smaller than that of the photoresist pattern can be formed by using the reaction product. Therefore, a contact hole with a small alignment margin can be formed with a sufficient alignment margin, and the product yield can be improved.

Although polysilicon is used as the material of the auxiliary mask 214, the point is that any desired reaction product can be formed in the mask pattern when the auxiliary mask 214 is etched, and it is preferable. , TiN film, C film, and the like, which have an antireflection effect. 9A to 9D are process sectional views showing a contact method according to the fifth embodiment of the present invention.

First, as shown in FIG. 9A, after the contacted layer 232 is formed on the surface of the semiconductor substrate 231, as in the previous embodiment, the interlayer insulating film 230 and the wiring layer 233 are formed.
Are sequentially formed. Next, a thickness of 6 is formed on the entire surface by using the CVD method.
An interlayer insulating film 235 having a thickness of about 00 nm is formed. And
After the surface of the interlayer insulating film 235 is flattened by using a flattening method such as polishing, an auxiliary mask 234 made of a polysilicon film and having a thickness of 100 nm is formed on the interlayer insulating film 235.

Next, as shown in FIG. 9B, a photoresist pattern 236 (first resist pattern) for the contact hole 337 is formed by using a photolithography technique.
To form.

Next, as shown in FIG. 9C, the interlayer insulating film 235 is formed using the photoresist pattern 236 as a mask.
The auxiliary mask 234 is etched by reactive ion etching until exposed. Where C or O is a few%
When the contained Cl ₂ gas is used as a reactive gas and etching is performed with the pressure set to 100 mTorr or less, the auxiliary mask 234 is processed into a taper shape and the reaction product 238 is formed on the inner wall of the contact hole 237.
Is deposited.

Next, as shown in FIG. 9D, the photoresist pattern 236 and the reaction product 238 are removed. As a result, a resist pattern (second resist pattern) including the auxiliary mask 234 having a hole diameter (opening area) smaller than that of the photoresist pattern 236 is formed.

Next, as shown in FIG. 9E, the interlayer insulating films 230 and 235 are etched by reactive ion etching using the second resist pattern as a mask until the contacted layer 232 is exposed. Further, the auxiliary mask 234 is thinned by the etching at this time. Next, a 30 nm thick TiSi ₂ film, a 70 nm thick TiN film, and
After a W film having a thickness of 100 nm is sequentially deposited by the CVD method, the above three films are sequentially patterned to form the wiring layer 239.
To form. Moreover, the wiring layer 2 is formed by patterning at this time.
The auxiliary mask 234 other than the lower part of 39 is removed by etching.

Even with the method described above, a mask pattern having a hole diameter smaller than the hole diameter of the photoresist pattern 236 can be formed in the same manner as in the previous embodiment. It can be sufficiently secured and the reduction in product yield due to the contact portion can be prevented. Further, according to the present embodiment, since the film thickness of the auxiliary mask 234 below the wiring layer 239 can be made smaller than that of the previous embodiment, surface irregularities can be suppressed and the element having the multilayer wiring structure can be easily manufactured. Become.

In the fourth and fifth embodiments, when the hole diameter of the opened contact hole is small and the contact resistance increases, for example, a wet treatment with dilute NH ₄ F or the like is used. The diameter should be increased. Also,
When the hole diameter is increased by such a treatment and the product yield is lowered, each wiring layer is previously covered with a film having resistance to treatment such as dilute NH ₄ F treatment such as SiN. You can leave it.

Although the method of finally leaving the auxiliary mask has been described in the above embodiment, for example, after the etching of the interlayer insulating film is temporarily stopped on the way and the auxiliary mask is selectively removed, the interlayer insulating film is removed. The contact hole may be formed by restarting the etching.

As another method in which the auxiliary mask does not remain, for example, after forming a contact hole in which the contact layer is exposed, W is selectively grown to some extent on the contact layer in the contact hole and the auxiliary mask. Then, the auxiliary mask and W on it are removed by using a resist etch back method or the like. After that, a wiring layer that contacts the contacted layer is formed again. Figure 1
0 is a process sectional view showing the contact method according to the fifth embodiment of the present invention.

First, as shown in FIG. 10A, impurities such as P, As or B are introduced into a predetermined region of the silicon substrate 311 by an ion implantation method or the like. Then, heat treatment at 800 ° C. or higher is performed on the silicon substrate 311 to activate the impurities, and the impurity diffusion layer 312 (first conductor layer) is formed on the surface of the silicon substrate 311.

Next, as shown in FIG. 10B, an interlayer insulating film 313 made of SiO ₂ and having a thickness of about 400 nm is deposited on the silicon substrate 311 by the CVD method. Next, a photoresist pattern 314 for a contact hole is formed on the interlayer insulating film 313, and then the interlayer insulating film 313 is etched by about 500 nm or more using the photoresist pattern 314 as a mask to open a contact hole.

Next, as shown in FIG. 10C, after removing the photoresist pattern 314, a polysilicon film 315 (second conductor layer) is deposited on the entire surface to a thickness of about 50 nm. Here, the deposition of the polysilicon film 315 is normally performed by setting the furnace temperature to about 650 ° C.
11 is introduced into the furnace. However, since a natural oxide film having a thickness of about 0.5 to 1.0 nm is formed on the impurity diffusion layer 312, the temperature at which the natural oxide film is difficult to form, for example, about 400
The furnace temperature is set to ° C and the semiconductor substrate 311 is introduced into the furnace.
Moreover, since a natural oxide film may still be formed even in this case, it is desirable to perform a treatment for removing the natural oxide film formed at the time of introduction in the furnace. For example, HF, NH ₃
Wet etching with dilute hydrofluoric acid such as F or plasma cleaning using CF ₄ or the like is performed. Through such steps, it is possible to prevent an increase in interface resistance due to a substance such as a natural oxide film existing between the impurity diffusion layer 312 and the polysilicon film 315.

Next, the conductivity type of the polysilicon film 315 is made the same as that of the impurity diffusion layer 312 by using the ion implantation method, and then the polysilicon film 315 is patterned into a predetermined shape. As a result, the contact resistance between the impurity diffusion layer 312 and the polysilicon film 316 becomes sufficiently small.

Next, a TiSi ₂ film having a thickness of 30 nm and a thickness of 7 are formed.
A TiN film of 0 nm and a W film of 100 nm in thickness are sequentially formed on the polysilicon film 315 by a sputtering method. Finally, the above three films are etched to form the wiring layer 316 (third layer).
Conductor layer) is formed.

This wiring layer 316 and polysilicon film 315
The contact area with the contact hole is larger than the contact area between the impurity diffusion layer 312 and the polysilicon film 315 (that is, the opening area of the contact hole). Further, as described above, the contact resistance between the impurity diffusion layer 312 and the polysilicon film 315 is sufficiently small.

Therefore, the wiring layer 316 is in direct contact with the impurity diffusion layer 312 effectively with a contact area larger than the opening area of the contact hole, so that the contact resistance can be easily increased without using a new material. It can be reduced.

That is, in this embodiment, the interface resistance between the first conductor layer and the second conductor layer is R ₁₂ , and the first conductor layer and the third conductor layer are the same.
R ₁₃ is the interface resistance with the conductor layer, R ₂₃ is the interface resistance between the second conductor layer and the third conductor layer, S ₂₃ is the contact area between the second conductor layer and the third conductor layer, When the contact area S ₁₂ between the first conductor layer and the second conductor layer is S ₁₂ , the second conductor layer is formed such that R ₁₂ <R _{13 to} R ₂₃ and S ₁₂ <S ₂₃ . here,~
Indicates that those connected by this symbol are almost equal. Therefore, in this embodiment, the contact resistance is R
Proportional to ₂₃ / S _23. On the other hand, the contact resistance in the conventional case is proportional to R ₁₃ / S ₁₃ . Here, S ₁₃ is the opening area of the contact hole.

As described above, the contact resistance between the first conductor layer and the third conductor layer is not limited by the opening area of the contact hole, but between the first conductor layer and the third conductor layer, A second conductor layer having an interface resistance with the first conductor layer smaller than an interface resistance with the third conductor layer is formed, and a contact resistance between the first conductor layer and the third conductor layer is set to a second value. Is controlled at the interface between the second conductor layer and the third conductor layer.
The contact resistance is reduced by making the contact area with the conductor layer larger than the opening area of the contact hole.

FIG. 14 shows the effect of the present invention, and is a diagram showing the dependency of the contact resistance Rc on the contact area Sc (on the mask) in comparison with that in the conventional case. This has a thickness of 4 as the interlayer insulating film 313 in FIG.
This is a case where a SiO ₂ film of 00 nm is used and the thickness of the polysilicon film 315 is 100 nm. This FIG.
To contact area Sc 0.1 μm ² It can be seen that the contact resistance Rc according to the present invention becomes about an order of magnitude smaller than that of the conventional case when the contact resistance Rc becomes smaller. Therefore, even if the contact hole becomes fine, RC delay of the element due to increase in contact resistance can be prevented. FIG. 11 is a process sectional view showing a contact method according to the sixth embodiment of the present invention.

First, as shown in FIG. 11A, the impurity diffusion layer 32 is formed on the silicon substrate 321 as in the previous embodiment.
2 (first conductor layer), an interlayer insulating film 323, and a contact hole are sequentially formed. Then, a polysilicon film 325 (second conductor layer) having a thickness of about 50 nm is formed on the entire surface. Next, as shown in FIG. 11B, a resist 324 is applied on the entire surface.

Next, as shown in FIG. 11C, the polysilicon film 325 is selectively left in the contact holes by etching back the entire surface. Then, after removing the resist 324, the conductivity type of the polysilicon film 325 is made the same as that of the impurity diffusion layer by using ion implantation.

Finally, as shown in FIG. 11D, a TiSi ₂ film having a thickness of 30 nm and a TiN film having a thickness of 70 nm are formed on the entire surface.
After sequentially forming a film and a W film having a thickness of 100 nm by the Patter method, the above three films are processed into a predetermined shape to form the wiring layer 3
26 (third conductor layer) is formed.

By the method described above, the same effect as in the previous embodiment can be obtained, and since the polysilicon film 325 on the interlayer insulating film 323 is removed, the step difference in the contact hole portion becomes small. This is advantageous for a multilayer structure. FIG. 12 is a process sectional view showing a contact method according to a seventh embodiment of the present invention.

First, as shown in FIG. 12A, the impurity diffusion layer 33 is formed on the silicon substrate 331 as in the previous embodiment.
2 (first conductor layer), an interlayer insulating film 333, and a contact hole are sequentially formed. Next, as shown in FIG.
A polysilicon film 335 (second conductor layer) having a thickness of about 500 nm is formed on the entire surface.

Next, as shown in FIG. 12C, etch back is performed using a chemical dry etching method to selectively leave the polysilicon film 335 in the contact holes.

Next, as shown in FIG. 12D, after forming a photoresist pattern 334 for etching a part of the polysilicon film 335, the impurity diffusion 332 is exposed using this photoresist pattern 334 as a mask. A part of the polysilicon film 335 is etched and removed by reactive ion etching to the extent not to do so.

Next, as shown in FIG. 12E, after removing the photoresist pattern 334, the conductivity type of the polysilicon film 335 is changed to the impurity diffusion layer 3 by ion implantation.
Same as that of 32. Finally, after depositing a laminated film of W / TiN / TiSi _{2 on} the entire surface by using the sputtering method,
The laminated film is etched to form the wiring layer 336 (third conductor layer).

Even in such a method, the contact area between the wiring layer 336 and the polysilicon film 335 becomes larger than that between the polysilicon film 335 and the impurity diffusion layer 332, and therefore the same effect as the previous embodiment can be obtained. . FIG. 13 is a process sectional view showing the contact method according to the eighth embodiment of the present invention.

First, as shown in FIG. 13A, the impurity diffusion layer 34 is formed on the silicon substrate 341 as in the previous embodiment.
2 (first conductor layer), an interlayer insulating film 343, and a contact hole are sequentially formed.

Next, as shown in FIG. 13B, SEG
Using the (Selective Epitaial Growth) method, a silicon film 345 (second conductor layer) is formed on the impurity diffusion layer 342 by about 4 times.
It is grown to about 00 nm.

Next, as shown in FIG. 13C, a HF (hydrofluoric acid) treatment is performed to etch away the silicon film 345 near the facet surface of the SEG having poor crystallinity.

Then, as shown in FIG. 13D, the conductivity type of the silicon film 345 is set to be the same as that of the impurity diffusion layer 342 by using an ion implantation method or the like, and then the entire thickness is 30 nm by using a sputtering method. TiSi ₂ film, 70 nm thick Ti
An N film and a W film having a thickness of 100 nm are sequentially formed. Finally,
A wiring layer 346 is formed by patterning the above three films.

Also in the case of this embodiment, since the contact area between the wiring layer 346 and the silicon film 345 is larger than that between the silicon film 345 and the impurity diffusion layer 342, the contact resistance is reduced without using a new material. it can.

In the fifth to eighth embodiments described above, the W film and the TiN film are used as the wiring layer in contact with the impurity diffusion layer.
Although a laminated film of a film and a TiSi ₂ film was used, Al, Cu, A
g, metal such as Au, or TiSi ₂ , NiSi ₂ ,
A silicide film such as CoSi ₂ may be used. Also,
A transition metal of group IV to VIa such as Nb or V may be used as the barrier metal.

As the second conductor layer, first, an undoped polysilicon film or a polysilicon film was formed.
By forming a polysilicon film or an amorphous silicon film doped with impurities such as P, As, and B from the beginning, steps such as ion implantation can be omitted and the number of steps can be reduced.

In the contact methods of the above fifth to eighth embodiments, the case where the first conductor layer is the impurity diffusion layer has been described, but when the first conductor layer is the gate wiring, the data wiring, etc. Can also be applied. Although the Si-based film is used as the plug material, a metal-based film such as W may be used.

[0098]

As described above in detail, according to the present invention, it is possible to easily prevent the insulation resistance of the contact portion from decreasing and the contact resistance from increasing even if the integration of the device progresses, thus improving the product yield. Can be achieved.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first half of a method of manufacturing a DRAM according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing the latter half of the method for manufacturing a DRAM according to the first embodiment of the present invention.

FIG. 3 is an element cross-sectional view of the DRAM according to the first embodiment of the present invention.

FIG. 4 is a process cross-sectional view showing the method of manufacturing the DRAM according to the third embodiment of the present invention.

FIG. 5 is a diagram for explaining the SP method.

FIG. 6 is a diagram for explaining the SP method.

FIG. 7 is a diagram for explaining the SP method.

FIG. 8 is a process sectional view showing the contact method according to the fourth embodiment of the present invention.

FIG. 9 is a process sectional view showing a contact method according to a fifth embodiment of the present invention.

FIG. 10 is a process sectional view showing the contact method according to the fifth embodiment of the present invention.

FIG. 11 is a process sectional view showing the contact method according to the sixth embodiment of the present invention.

FIG. 12 is a process sectional view showing a contact method according to a seventh embodiment of the present invention.

FIG. 13 is a process sectional view showing the contact method according to the eighth embodiment of the present invention.

FIG. 14 is a diagram for explaining the effect of the present invention.

FIG. 15 is a diagram showing a conventional method of forming a contact hole.

FIG. 16 is an element cross-sectional view of a contact hole portion obtained by a conventional method.

[Explanation of symbols]

110 ... Silicon substrate, 111 ... Field insulating film, 1
12 ... Gate oxide film, 113 ... Gate electrode (first conductor layer), 114 ... Thermal oxide film, 115 ... Silicon nitride film (first interlayer insulating film), 116 ... SiO ₂ film (second interlayer insulating film) ) 117 ... Polysilicon film, 118 ... BPSG film (third interlayer insulating film), 119 ... Polysilicon oxide film,
120 ... Bit line (second conductor layer), 121 ... Oxide film,
122 ... Nitride film, 123 ... Polysilicon oxide film, 124
... SiO ₂ film, 125 ... BPSG film, 126 ... Storage node electrode, 127 ... Capacitor insulating film, 128 ... Plate electrode, 129 ... Interlayer insulating film, 130 ... Al wiring,
210 ... Interlayer insulating film, 211 ... Semiconductor substrate, 212 ... Contact layer, 213 ... Wiring layer, 214 ... Auxiliary mask film, 215 ... Photoresist pattern (first resist pattern), 216 ... Contact hole, 217 ... Reaction generation 218 ... Wiring layer, 219 ... Interlayer insulating film, 230
... interlayer insulating film, 231, ... semiconductor substrate, 232 ... contact layer, 233 ... wiring layer, 234 ... auxiliary mask film, 23
5 ... Interlayer insulating film, 236 ... Photoresist pattern (first resist pattern), 237 ... Contact hole,
238 ... Reaction product, 239 ... Wiring layer, 311 ... Silicon substrate, 312 ... Impurity diffusion layer (first conductor layer), 31
3 ... Interlayer insulating film, 314 ... Photoresist pattern, 3
15 ... Polysilicon film (second conductor layer), 316 ... Wiring layer (third conductor layer), 321 ... Silicon substrate, 322 ...
Impurity diffusion layer (first conductor layer) 323 ... Interlayer insulating film,
324 ... Resist, 325 ... Polysilicon film (second conductor layer), 326 ... Wiring layer (third conductor layer), 331 ... Silicon substrate, 332 ... Impurity diffusion layer (first conductor layer),
333 ... Interlayer insulating film, 334 ... Photoresist pattern, 335 ... Polysilicon film (second conductor layer), 336
... Wiring layer (third conductor layer), 341 ... Silicon substrate, 3
42 ... Impurity diffusion layer (first conductor layer), 343 ... Inter-layer insulating film, 345 ... Silicon film (second conductor layer), 346 ...
Wiring layer (third conductor layer).

Claims (3)

[Claims] 1. When forming a second conductor layer which is formed between first conductor layers on a semiconductor substrate and which contacts a contacted layer electrically separated from the first conductor layer by an interlayer insulating film. A step of depositing a first interlayer insulating film having a uniform thickness as the interlayer insulating film on the entire surface of the semiconductor substrate on which the contacted layer is formed between the first conductor layers; A step of depositing, as the interlayer insulating film, a second interlayer insulating film, which is thicker in a peripheral portion between the conductor layers than on a central portion between the conductor layers, on the interlayer insulating film On the interlayer insulating film, as the interlayer insulating film,
A step of forming a third interlayer insulating film, and a step of forming a stopper film having resistance to etching of the third interlayer insulating film before forming the third interlayer insulating film. And a step of forming the third interlayer insulating film by etching the third interlayer insulating film to form an opening having an opening width larger than a distance between the first conductor layers in the third interlayer insulating film on the contacted layer. And a step of removing the stopper film in the opening, and a step of selectively removing the first and second interlayer insulating films in the central portion between the conductor layers. Manufacturing method of semiconductor device. 2. A step of forming an auxiliary mask film on the interlayer insulating film when forming a conductor layer formed on a semiconductor substrate and contacting a contacted layer covered with the interlayer insulating film, and the auxiliary mask film. A step of forming a first resist pattern for the opening on the upper side, and the auxiliary mask film is etched by using the first resist pattern as a mask, and a reaction product generated by this etching is formed by the etching. Forming a second resist pattern having an opening area smaller than that of the first resist pattern on the inner wall surface of the opening, and etching the interlayer insulating film using the second resist pattern as a mask. A method of manufacturing a semiconductor device, comprising: 3. A step of forming an interlayer insulating film on a first conductor layer formed on a semiconductor substrate, a step of forming an opening in the interlayer insulating film on the first conductor layer, and the opening. A step of forming a second conductor layer in contact with the first conductor layer on the surface of the first conductor layer of the portion under the condition that an interfacial resistance increasing substance is not formed; A step of forming a third conductor layer, the contact area of which is larger than the contact area of the first conductor layer and the second conductor layer.