JPH0527275B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing an insulated gate semiconductor device;
More specifically, it is possible to simultaneously form a polycrystalline silicon gate electrode wiring formed on a semiconductor board and an interlayer insulating film, and to planarize the surface by burying the gate electrode wiring with the interlayer insulating film. The present invention relates to a method for manufacturing an insulated gate type semiconductor device.

Conventional configurations and their problems Large-scale integrated circuits (hereinafter referred to as LSI), e.g.
In the production of MOS type LSI, the active region that makes up the MOS transistor, the element isolation region that separates this active region within the semiconductor substrate, and the formation of electrode wiring that electrically interconnects the manufactured elements are formed. are essential, and these must be carried out accurately and
There is a strong desire to create fine structures while maintaining high reproducibility.

In a normal MOS LSI process, after forming an oxide film called a field oxide film necessary for element isolation, a gate electrode region is formed, and then a self-alignment method (self-alignment method) in which this gate electrode is used as a mask is used. A MOS transistor is fabricated by forming source and drain regions using the alignment method. After this, an interlayer insulating film and a metal oxide layer are formed. However, as the degree of integration of MOS LSI increases,
Wiring for electrically interconnecting a large number of circuit elements built into a semiconductor board becomes complicated, and electric paths intersect at various locations. For this reason, metal wiring layers are formed in multiple layers, realizing three-dimensional intersections of electric paths between different wiring layers and between the gate electrode and each wiring layer, and at the same time simplifying the metal wiring layer pattern. A multilayer wiring structure is adopted.

By the way, in a MOS type LSI with such a structure,
If there is a large step in the gate electrode, when an interlayer insulating film and a metal wiring layer are formed later, the film thickness becomes thinner in a portion extending beyond the step, resulting in a disconnection accident. Particularly, when electrical circuits are crossed over three-dimensionally at this gate electrode portion, there has been a problem in that disconnection accidents at the intersection of the electrical circuits become conspicuous.

OBJECTS OF THE INVENTION The present invention was made with the intention of eliminating problems caused by the formation of a step portion on a semiconductor substrate prior to the formation of an interlayer insulating film and a metal wiring layer. so as not to appear,
It is an object of the present invention to provide a method for manufacturing an insulated gate type semiconductor device that can form a flat gate electrode wiring layer and form an interlayer insulating film simultaneously with the formation of the gate electrode wiring layer.

Structure of the Invention A method for manufacturing an insulated gate type semiconductor device according to the present invention includes introducing an impurity of an opposite conductivity type into a surface layer of a semiconductor substrate of one conductivity type surrounded by an insulating film for isolation between elements. After forming an etched groove that bisects the surface layer of the opposite conductivity type, a gate insulating film is formed that covers at least the inner surface of the etched groove, and a shape that follows the shape of the exposed surface is obtained. A polycrystalline silicon film is formed on the entire surface so that the polycrystalline silicon film is formed, and then the entire surface is covered with a mask material, the etched groove portions are opened, and the exposed surface of the polycrystalline film except for the sidewall portions is nitrided by ion implantation. Using this as a mask, oxidation treatment is performed to oxidize the polycrystalline silicon film. At this time, the polycrystalline silicon film under the nitrided surface layer remains unoxidized, so that the polycrystalline silicon is buried in the etched groove. According to the present invention, since the main surface of the gate electrode wiring and the main surface of the active region of the semiconductor substrate are located in almost the same plane, a flat surface state with no steps can be obtained. The electrode wiring and the interlayer insulating film embedding the electrode wiring can be formed at the same time.

DESCRIPTION OF EMBODIMENTS The method for manufacturing an insulated gate semiconductor device of the present invention
The manufacturing of a MOS type LSI will be explained in detail below using an example.

First, as shown in FIG. 1, a field oxide film 2 having a function of separating elements is formed on the surface of a silicon substrate 1, and then a diffusion layer 3 is formed by ion-implanting arsenic or boron. Next, the silicon substrate 1 is subjected to a plasma etching process to form a groove 4 that divides the diffusion layer 3 into two as shown in FIG. In this case, the width of the etching window formed in the photoresist is preferably 3 μm or less, and
In order to etch the silicon substrate 1 faithfully to this dimensional width, anisotropic etching is performed using carbon tetrachloride gas plasma.

After this, as shown in Figure 3, an oxide film (gate oxide film) with a thickness of about 500 Å is formed in an oxygen atmosphere at 900°C.
5 is formed, and furthermore, on this oxide film 5, a film with a thickness of
A polycrystalline silicon film 6 of 4000 Å and a sheet resistance of about 15 Ω/□ is formed. Next, as shown in FIG. 4, a photoresist pattern 7 having an opening dimension width comparable to that when forming the groove 4 in the silicon substrate 1 is formed, and using this photoresist pattern 7 as a mask, nitrogen is irradiated at an accelerating voltage of 50 KeV. Perform ion implantation. Through this treatment, the surface of the polycrystalline silicon film 6 perpendicular to the ion implantation direction is nitrided, and the nitride films 8, 81,
82 is formed. And as a final step,
Heat treated in a high pressure oxygen atmosphere of 9Kg/ ^cm2 ,
A part of the polycrystalline silicon film 6 is converted into an oxide film.
That is, the portions of the polycrystalline silicon film that are not covered by the nitride films 8, 81, and 82 are completely oxidized, and the portions directly under the nitride films 81 and 82 are oxidized laterally, resulting in the formation of the etched grooves. If the width is chosen appropriately, oxidation from both sides will coalesce to form an oxide film. No oxidation occurs directly under the nitride film 8. Although the nitride film is also oxidized at this time, it is convenient to select the thickness of the nitride films 8, 81, and 82 so that they are oxidized and disappear. Further, even if a part of the nitride film remains, it will be incorporated into the oxide film and will not cause any harm. Due to the masking effect of the nitride film, as shown in FIG. 5, a gate electrode layer 9 is formed which has a width approximately equal to the width of the portions where the nitride films 8, 81, and 82 are formed and a total thickness of 4000 Å. Moreover, a structure is obtained in which the upper part is covered with the oxide film 10 which becomes an interlayer insulating film.

Although an example has been described above, the manufacturing method of the present invention is not limited to MOS structures, but can be widely applied to manufacturing semiconductor devices with MIS structures. Furthermore, if the thickness of the diffusion layer 3, the depth of the groove 4, and the thickness of the gate insulating film 5 and polycrystalline silicon film 6 are controlled, the step caused by the gate electrode can be made almost zero.

Effects of the Invention As described in detail above, according to the present invention, not only can a flat gate electrode with no steps be formed, but also an interlayer insulating film can be formed at the same time as the gate electrode is formed. As a result, the surface of the interlayer insulating film becomes flat, making it possible to make the thickness of the wiring layer uniform even in a multilayer wiring structure, especially in a structure in which the wiring layer crosses over the gate electrode formation part. The effect of reliably eliminating the occurrence of disconnection accidents is achieved.

[Brief explanation of the drawing]

Figures 1 to 5 show the results obtained by the manufacturing method of the present invention.
FIG. 3 is a diagram showing a process of manufacturing a MOS type LSI. 1... Silicon substrate, 2... Field oxide film, 3... Diffusion region, 4... Groove dividing the diffusion region into two, 5... Oxide film (gate oxide film), 6... Polycrystalline silicon film, 7 ...Photoresist, 8,81,
82...Nitride film, 9...Gate electrode layer, 10...
Insulating film (interlayer insulating film).

Claims (1)

[Claims] 1. Introducing an impurity of an opposite conductivity type into a surface layer of a semiconductor substrate of one conductivity type surrounded by an insulating film for isolation between elements,
After forming the opposite conductivity type surface layer, forming an etched groove that bisects the opposite conductivity type surface layer, and forming a gate insulating film that covers at least the inner surface of the etched groove,
Furthermore, a polycrystalline silicon film is formed on the entire surface so as to obtain a shape that follows the shape of the exposed surface, and then the entire surface is covered with a mask material, the etched groove portion is opened, and the polycrystalline silicon film is formed by ion implantation. 1. Manufacturing an insulated gate type semiconductor device characterized by nitriding the exposed surface excluding the side wall portions of the device, and then performing an oxidation treatment to oxidize the polycrystalline silicon film to leave polycrystalline silicon in the etched grooves. Method. 2. The method of manufacturing an insulated gate type semiconductor device according to claim 1, wherein the polycrystalline silicon in the etched groove is embedded in an oxide film obtained by oxidizing other polycrystalline silicon.