JP2639052B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for treating a surface of an interlayer insulating layer made of a polyimide resin in a semiconductor device, and to reduce a leakage current generated on the surface of the polyimide resin interlayer insulating layer by ion milling. Forming an interlayer insulating layer made of a polyimide resin on the surface of the substrate on which is formed, forming an opening in the interlayer insulating layer on the conductive region, and forming a surface layer of the conductive region exposed in the opening. An ion milling step for removing, a step of forming a wiring of a predetermined pattern on the interlayer insulating layer after the ion milling step, and making an exposed surface of the interlayer insulating layer on which the wiring is formed non-conductive And an oxidation treatment step.

[Industrial applications]

The present invention relates to a surface treatment method for an interlayer insulating layer made of a polyimide resin in a semiconductor device.

[Conventional technology]

A polyimide resin is used as an insulating layer in a semiconductor device. In other words, a good insulating layer can be formed only by applying a polyimide resin solution on the substrate and then heat-treating it at a temperature of around 300 ° C. Many are used as.

Figure 2 is a fragmentary cross-sectional view showing a two-layer wiring structure that is separated polyimide resin with an interlayer insulating layer, on the substrate 1, for example an insulating layer 2 made of SiO _2, for example from Aruminiumu (Al) The lower wiring 3 is formed, and an interlayer insulating layer 4 made of a polyimide resin is formed on the lower wiring 3. Further, on the interlayer insulating layer 4, an upper wiring 5 made of, for example, A1 is formed. The upper wiring 5 is connected to a predetermined lower wiring 3 through an opening (through hole) provided at a predetermined position in the interlayer insulating layer 4. Reference numeral 6 denotes a protective layer 6 which covers the upper wiring 5 and is made of, for example, a polyimide resin.

[Problems to be Solved by the Invention] After forming the through holes, prior to depositing a conductive layer forming the upper wiring 5 on the interlayer insulating layer 4 by a method such as vacuum deposition, a lower wiring is generally formed. 3
Is subjected to ion milling. This is because a surface layer such as a natural oxide film formed on the surface of the lower wiring 3 composed of 41 or the like is removed by ion milling, and the upper wiring 5 is removed.
The purpose is to obtain the reliability of the connection.

However, due to the ion milling, the surface of the upper wiring 5 becomes conductive, and the space between the wirings 5 is in a leak mode. This leakage current reaches 60 to 300 pA, and the operation of the semiconductor device or the integrated circuit comprising the upper phase wiring 5 becomes unstable or malfunctions. Therefore,
Due to such leakage on the surface of the interlayer insulating layer, there has been a problem that the reliability of the product and the production yield are reduced.

An object of the present invention is to reduce the leak current generated on the surface of a polyimide resin interlayer insulating layer by the ion milling process as described above.

[Means for solving the problem]

The object is to form an interlayer insulating layer made of a polyimide resin on the surface of the substrate on which the conductive region is formed, to form an opening in the interlayer insulating layer on the conductive region,
An ion milling step for removing a surface layer of the conductive region exposed in the opening, and a step of forming a wiring of a predetermined pattern on the interlayer insulating layer after the ion milling step;
An oxidation treatment step for rendering the exposed surface of the interlayer insulating layer on which the wiring is formed non-conductive, the method according to the present invention.

(Operation)

The reason why conductivity occurs on the surface of the insulating layer made of the polyimide resin as described above is considered as follows. (Showa
When the polyimide resin is thermally decomposed in vacuum, the imide bond is broken, carbon monoxide (CO) is released, and the surface is graphitized by a thermal crosslinking reaction. I do. When the temperature reaches 800 ° C, a black semiconductive substance forms.
Even in the ion milling process, nitrogen (N) and oxygen (O) atoms were lost from the polyimide resin surface due to the collision of ions such as argon (Ar), and excess carbon (C) was bonded to form graphite. Transformed layer 7 with low resistance
(See FIG. 2) is assumed to occur on the surface.

Therefore, by removing excess carbon generated on the surface of the polyimide resin insulating layer by heat treatment in an oxidizing atmosphere, oxygen plasma treatment, oxygen ion implantation, or the like, the surface insulation is restored. If the above oxidation treatment is performed after the upper wiring is formed, the surface of the lower wiring exposed in the opening of the polyimide resin interlayer insulating layer is not oxidized, and the connection between the upper wiring and the lower wiring is not affected. The deteriorated layer 7 will remain under the upper wiring, but this is not a problem.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the process explanatory diagram of FIG. In the following drawings, the same parts as those in the already-described drawings are denoted by the same reference numerals.

Referring to FIG. 1A, an insulating layer 2 made of SiO ₂ or the like is formed on a substrate 1 made of a silicon wafer or the like on which a diffusion layer or the like is formed in the same manner as in a normal semiconductor device manufacturing process. Then, for example, an Al thin film is deposited on the insulating layer 2 and is patterned into a predetermined wiring shape using a well-known lithographic technique to form a lower wiring 3.

After the above, a polyimide resin is applied on the substrate 1 by, for example, a spin coating method, and pre-baking and pre-curing are performed under the same conditions as usual to form an interlayer insulating layer 4. Then, the interlayer insulating layer 4 is formed using a well-known lithographic technique. An opening 8 reaching the lower wiring 3 is provided at a predetermined position of the layer 4.
After that, post cure is performed under the same conditions as usual.

Next, ion milling is performed on the surface of the lower wiring 3 exposed in the opening 8 using argon. This ion milling is performed, for example, in a high vacuum over the entire surface of the substrate 1,
Irradiation with mA argon ions for 140 seconds. By the ion milling, a clean surface of the lower wiring 3 is exposed in the opening 8. On the other hand, the altered layer 7 with excess carbon
Are generated on the surface of the polyimide resin interlayer insulating layer 4.

Next, for example, an A1 thin film is deposited on the entire surface of the substrate 1,
This is patterned into a predetermined wiring shape using a well-known lithographic technique, and an upper wiring 5 is formed as shown in FIG. 1 (b).

Next, the substrate 1 is placed in an oxidizing atmosphere, for example, nitrogen (N ₂ ).
Heat treatment at 350 ° C. for 60 minutes in a mixed gas of equal amounts of oxygen and oxygen (O ₂ ). As a result, as shown in FIG. 1B, on the surface of the interlayer insulating layer 4 exposed from the upper wiring 5, excess carbon is removed as CO gas, and the altered layer 7 has disappeared. Although the deteriorated layer 7 remains under the wiring 5, there is no possibility that a leak current occurs between the upper wirings 5. The leakage current between 60 and 300 pA between the upper wirings 5 is reduced to about 10 pA by the oxidation treatment.

Thereafter, according to a normal process, as shown in FIG. 1 (C), a protective layer 6 is formed by applying, for example, a polyimide resin to cover the wiring 5 and performing pre-baking and curing under predetermined conditions. Further, an opening (not shown) is formed in the protective layer 6.
Are provided and external wiring is connected to complete the semiconductor device of the present invention.

Instead of the heat treatment in an atmosphere containing oxygen, the first
Oxygen plasma treatment may be applied to the surface of the substrate 1 in the state shown in FIG. For this oxygen plasma treatment, a normal resist ashing apparatus can be used.
The treatment is performed in oxygen plasma.

Further, instead of the heat treatment in the oxygen atmosphere or the oxygen plasma treatment, oxygen ions may be implanted into the surface of the substrate 1 in the state shown in FIG. The processing conditions in this case may be, for example, an oxygen ion energy of 10 to 30 KeV and a dose of 1 × 10 ¹³ to 1 × 10 ¹⁶ ion / cm ² .

It is needless to say that the present invention can be applied to the case where the wiring is connected to, for example, the diffusion layer of the substrate 1 through the opening of the polyimide resin interlayer insulating layer.

〔The invention's effect〕

ADVANTAGE OF THE INVENTION According to this invention, the leak current between wirings in the semiconductor device using a polyimide resin interlayer insulating layer is reduced, and there exists an effect which can improve the reliability and manufacturing yield of this semiconductor device.

[Brief description of the drawings]

 FIG. 1 is an explanatory view of a process in an embodiment of the present invention, and FIG. 2 is an explanatory view of a conventional problem. In the figure, 1 is a substrate, 2 is an insulating layer, 3 is a lower wiring, 4 is an interlayer insulating layer, 5 is an upper wiring, 6 is a protective layer, 7 is a deteriorated layer, and 8 is an opening.

Continuation of the front page (72) Inventor Masashi Sasaki 1015 Ueodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-64-64237 (JP, A) JP-A-1-100946 (JP, A) Proceedings of the IEICE Semiconductor and Materials Division National Conference, 1981 2-250

Claims (1)

(57) [Claims] A step of forming an interlayer insulating layer made of a polyimide resin on a surface of the substrate on which the conductive region is formed; a step of forming an opening in the interlayer insulating layer on the conductive region; An ion milling step for removing a surface layer of a conductive region to be formed, a step of forming a wiring of a predetermined pattern on the interlayer insulating layer after the ion milling step, and exposing the interlayer insulating layer on which the wiring is formed An oxidation treatment step for rendering the surface non-conductive.