JPH0329293B2 - - Google Patents
Info
- Publication number
- JPH0329293B2 JPH0329293B2 JP60062322A JP6232285A JPH0329293B2 JP H0329293 B2 JPH0329293 B2 JP H0329293B2 JP 60062322 A JP60062322 A JP 60062322A JP 6232285 A JP6232285 A JP 6232285A JP H0329293 B2 JPH0329293 B2 JP H0329293B2
- Authority
- JP
- Japan
- Prior art keywords
- gate oxide
- oxide film
- film
- thin film
- polysilicon thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000010409 thin film Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000011109 contamination Methods 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 12
- 230000006866 deterioration Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 238000011282 treatment Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Description
【発明の詳細な説明】
[発明の技術分野]
この発明は、例えば半導体集積素子あるいは半
導体記憶素子等の半導体基板上にゲート酸化膜が
形成される半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which a gate oxide film is formed on a semiconductor substrate, such as a semiconductor integrated device or a semiconductor storage device.
[発明の技術的背景]
従来、例えばd RAM(dynamic RAM)に
おいてキヤパシタを形成するには、まず半導体基
板の表面に酸化炉中にて薄いゲート酸化膜を成長
させる。次に、このゲート酸化膜を露出させたま
まの状態でフオトリソグラフイやイオン注入を行
ない基板内に金属による拡散層を形成し、そして
レジスト膜の剥離および基板表面のRCA洗浄等
を行なつた後、上記ゲート酸化膜上に電極材料と
なるポリシリコン導電層を被着形成してキヤパシ
タを形成する。[Technical Background of the Invention] Conventionally, in order to form a capacitor in, for example, a dRAM (dynamic RAM), a thin gate oxide film is first grown on the surface of a semiconductor substrate in an oxidation furnace. Next, with this gate oxide film exposed, photolithography and ion implantation were performed to form a metal diffusion layer within the substrate, and the resist film was removed and the substrate surface was cleaned with RCA. Thereafter, a polysilicon conductive layer serving as an electrode material is deposited on the gate oxide film to form a capacitor.
[背景技術の問題点]
しかしながら上記のような半導体装置の製造工
程では、最も清浄度が必要とされるゲート酸化膜
が長時間に渡つて例えばNa、K等のイオンを含
む大気中にさらされるばかりか、フオトエツチン
グまたはレジスト剥離工程やイオン注入等により
金属汚染にさらされるため、たとえ電極材料を被
着させる以前に、基板表面に対して化学的な
RCA洗浄を施したとしても、上記汚染は充分に
取除くことができない。このため、上記ゲート酸
化膜自体の膜質を如何に向上させたとしても、そ
の膜質を維持する
ことが困難なため、例えばゲート酸化膜が上記汚
染にさらされる度合いが多ければ多い程、素子形
成後の耐圧特性が劣化する等の問題が生じる。[Problems with the Background Art] However, in the manufacturing process of semiconductor devices as described above, the gate oxide film, which requires the highest level of cleanliness, is exposed to the atmosphere containing ions such as Na and K for a long period of time. In addition, the substrate surface is exposed to metal contamination during photoetching or resist stripping processes, ion implantation, etc., so even if the substrate surface is not chemically exposed to the surface before depositing the electrode material,
Even if RCA cleaning is performed, the above contamination cannot be sufficiently removed. For this reason, no matter how much the film quality of the gate oxide film itself is improved, it is difficult to maintain the film quality. For example, the more the gate oxide film is exposed to the above contamination, the more Problems arise, such as deterioration of the breakdown voltage characteristics.
[発明の目的]
この発明は上記のような問題点に鑑みなされた
もので、ゲート酸化膜形成後の半導体基板面に対
してフオトエツチング、イオン注入、レジスト剥
離あるいは洗浄等の各処理を施した場合でも、上
記ゲート酸化膜の膜質低下を招くこなく、素子特
性の劣化を防止することが可能となる半導体装置
の製造方法を提供することを目的とする。[Purpose of the Invention] This invention was made in view of the above-mentioned problems, and it is a method of applying various treatments such as photoetching, ion implantation, resist peeling, or cleaning to the surface of a semiconductor substrate after forming a gate oxide film. An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent deterioration of device characteristics without causing deterioration in the film quality of the gate oxide film, even in the case of a semiconductor device.
[発明の概要]
すなわちこの発明に係わる半導体装置の製造方
法は、半導体基板の表面にゲート酸化膜を形成し
た直後に、予めその表面に次工程の妨げとならな
い程度の膜厚のポリシリコンの薄膜を形成し、そ
して必要な種々の工程を行なつた後、上記ポリシ
リコン薄膜の表面に所定の膜厚でポリシリコン導
電層を形成し、上記種々の工程による汚染を上記
ポリシリコン薄膜にてくい止めゲート酸化膜の膜
質低下を防ぐようにしたものである。[Summary of the Invention] In other words, the method for manufacturing a semiconductor device according to the present invention is such that immediately after forming a gate oxide film on the surface of a semiconductor substrate, a thin film of polysilicon is deposited on the surface in advance to a thickness that does not interfere with the next process. After forming and performing various necessary steps, a polysilicon conductive layer is formed with a predetermined thickness on the surface of the polysilicon thin film, and the polysilicon thin film prevents contamination caused by the various steps described above. This is to prevent deterioration in the quality of the gate oxide film.
[発明の実施例]
以下図面によりこの発明の一実施例を説明す
る。[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.
第1図A乃至Dはそれぞれその半導体装置の製
造工程を示すもので、まず同図Aに示すようなシ
リコン半導体基板11を、清浄な酸素雰囲気中に
て酸化し、その表面に同図Bに示すようにゲート
酸化膜12を形成する。このゲート酸化膜12
は、外部からの汚染に対して極めて敏感であるた
め、第1図Cに示すように、その形成直後の表面
に電極材料であるポリシリコンの薄膜13を被覆
形成する。この場合、上記ポリシリコン薄膜13
の膜厚を厚くすると、次工程において反転防止イ
オン注入層、チヤネルイオン注入層またはソー
ス、ドレイン層を形成する際に、大きなイオンの
加速電圧が必要となるもので、例えば膜厚100Å
のゲート酸化膜12上から直接Asイオンを注入
する方式に対して、上記ポリシリコン薄膜13を
500Åの膜厚で形成した後にイオン注入を施し、
上記と同等の注入層を得るには、加速電圧Vacc
=170〜180keVが必要となる。ここで、現状のイ
オン注入装置の加速電圧の限界は200keVである
ことから、上記ポリシリコン薄膜13の膜厚は
1000Å以下ということになる。 FIGS. 1A to 1D each show the manufacturing process of the semiconductor device. First, a silicon semiconductor substrate 11 as shown in FIG. 1A is oxidized in a clean oxygen atmosphere, and the surface is A gate oxide film 12 is formed as shown. This gate oxide film 12
Since the electrode is extremely sensitive to external contamination, a thin film 13 of polysilicon, which is an electrode material, is formed on the surface immediately after its formation, as shown in FIG. 1C. In this case, the polysilicon thin film 13
If the film thickness is increased, a large ion accelerating voltage will be required when forming the anti-inversion ion implantation layer, channel ion implantation layer, or source and drain layers in the next process.
In contrast to the method of directly implanting As ions onto the gate oxide film 12, the polysilicon thin film 13 described above is
After forming a film with a thickness of 500 Å, ion implantation is performed,
To obtain an injection layer equivalent to the above, the accelerating voltage Vacc
=170 to 180keV is required. Here, since the current acceleration voltage limit of ion implantation equipment is 200 keV, the thickness of the polysilicon thin film 13 is
This means that it is less than 1000Å.
この後、フオトエツチング工程を経て上記ポリ
シリコン薄膜13上から半導体基板11に対して
例えばAsイオンの注入を行ない、Asイオン注入
層14を形成する。この後、上記フオトエツチン
グのマスクとして形成したレジスト膜(図示せ
ず)を剥離し基板洗浄を行なう。この場合、上記
フオトエツチング、イオン注入、レジスト剥離お
よび基板洗浄による金属汚染あるいは大気接触に
よる汚染等は、上記ポリシリコン薄膜13により
その殆んどがブロツクされるようになり、汚染に
敏感な上記ゲート酸化膜12に悪影響を及ぼすこ
とはない。そしてこの後、本来電極として必要と
されるポリシリコン導電層15を、上記ポリシリ
コン薄膜13の表面にその膜厚との兼合いで決定
される所定の膜厚にて重合形成する。 Thereafter, through a photo-etching process, for example, As ions are implanted into the semiconductor substrate 11 from above the polysilicon thin film 13 to form an As ion-implanted layer 14. Thereafter, the resist film (not shown) formed as a mask for photoetching is peeled off and the substrate is cleaned. In this case, metal contamination due to photoetching, ion implantation, resist peeling, and substrate cleaning, or contamination due to contact with the atmosphere, is mostly blocked by the polysilicon thin film 13, and the gate, which is sensitive to contamination, is blocked by the polysilicon thin film 13. There is no adverse effect on the oxide film 12. Thereafter, a polysilicon conductive layer 15, which is essentially required as an electrode, is formed by polymerization on the surface of the polysilicon thin film 13 to a predetermined thickness determined in consideration of the thickness of the polysilicon thin film 13.
すなわちこのような製造工程においては、ゲー
ト酸化膜12はその形成後直ちにポリシリコン薄
膜13により被覆されるので、以後の工程でのフ
オトレジストからの汚染およびイオン注入時にお
ける金属汚染からも保護されるようになる。これ
により、上記ゲート酸化膜12は、その膜質が常
に形成時と同様の品質に保たれるようになる。第
2図AおよびBはそれぞれ120Åのゲート酸化膜
に対し直接種々の処理を施す従来の製造方法と、
ポリシリコン薄膜13により被覆をした後に上記
処理を施す本発明による製造方法とを用いた場合
の半導体素子の耐圧分布特性を比較して示すもの
である。ここで、第2図Aにおける従来方法によ
り製造された素子の場合には、まず電界が
1MV/CM以下にて初期不良が見られ、その後電
界が大きくなるに連れ不良率は徐々に増加し、
8.5MV/CMにおいて全て破壊に至つている。一
方、第2図Bおける本発明方法により製造された
素子の場合には、まず初期不良が殆んどないと共
に、電界が8MV/CMに達するまで不良率の増加
も殆んどなく、8.5MV/CMから急激に破壊に至
る。したがつて、本発明方法を適用することによ
り、極めて欠陥の少ないゲート酸化膜にて素子を
形成することが可能となり、このゲート酸化膜を
用いる半導体製品の歩留りおよび信頼性の向上が
達成出来る。 That is, in such a manufacturing process, since the gate oxide film 12 is covered with the polysilicon thin film 13 immediately after its formation, it is protected from contamination from photoresist in subsequent steps and metal contamination during ion implantation. It becomes like this. Thereby, the quality of the gate oxide film 12 is always maintained at the same quality as when it was formed. Figures 2A and 2B show a conventional manufacturing method in which various treatments are directly applied to a 120 Å gate oxide film, and
This figure shows a comparison of the breakdown voltage distribution characteristics of a semiconductor device when using the manufacturing method according to the present invention in which the above-mentioned treatment is performed after coating with a polysilicon thin film 13. Here, in the case of the device manufactured by the conventional method shown in FIG. 2A, first the electric field is
Initial failures were observed below 1 MV/CM, and as the electric field increased, the failure rate gradually increased.
All of them were destroyed at 8.5MV/CM. On the other hand, in the case of the device manufactured by the method of the present invention shown in FIG. / CM suddenly leads to destruction. Therefore, by applying the method of the present invention, it is possible to form elements using a gate oxide film with extremely few defects, and it is possible to improve the yield and reliability of semiconductor products using this gate oxide film.
[発明の効果]
以上のようにこの発明によれば、半導体基板の
表面にゲート酸化膜を形成した直後に、予めその
表面に次工程の妨げとならない程度の膜厚のポリ
シリコンの薄膜を形成し、そして必要な種々の工
程を行なつた後、上記ポリシリコン薄膜の表面に
所定の膜厚でポリシリコン導電層を形成するよう
にしたので、上記ゲート酸化膜の膜質低下を招く
ことなく、素子特性の劣化を防止することが可能
となる。[Effects of the Invention] As described above, according to the present invention, immediately after forming a gate oxide film on the surface of a semiconductor substrate, a thin polysilicon film is formed on the surface in advance to a thickness that does not interfere with the next process. Then, after performing various necessary steps, a polysilicon conductive layer is formed with a predetermined thickness on the surface of the polysilicon thin film, so that the film quality of the gate oxide film is not deteriorated. It becomes possible to prevent deterioration of element characteristics.
第1図A乃至Dはそれぞれこの発明の一実施例
に係わる半導体装置の製造工程を示す断面構成
図、第2図AおよびBはそれぞれ従来の製造方法
と本発明による製造方法とによる素子の耐圧分布
特性を比較して示す図である。
11…半導体基板、12…ゲート酸化膜、13
…ポリシリコン薄膜、14…イオン注入層、15
…ポリシリコン導電層。
1A to 1D are cross-sectional configuration diagrams showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIGS. 2A and 2B are diagrams showing the breakdown voltage of the device according to the conventional manufacturing method and the manufacturing method according to the present invention, respectively. FIG. 3 is a diagram showing a comparison of distribution characteristics. 11... Semiconductor substrate, 12... Gate oxide film, 13
...Polysilicon thin film, 14...Ion implantation layer, 15
...Polysilicon conductive layer.
Claims (1)
工程と、 このゲート酸化膜の形成後直ちに該ゲート酸化
膜の表面にポリシリコンの薄膜を形成する工程
と、 このポリシリコン薄膜により表面が被われた半
導体基板に対して少なくともイオン注入を含みフ
オトエツチング・レジスト剥離、あるいはウエハ
洗浄の何れか1つ以上の処理を施す工程と、 そして上記ポリシリコン薄膜の表面に所定の膜
厚でポリシリコン導電層を形成する工程とを具備
し、 上記ポリシリコン薄膜は上記ゲート酸化膜をフ
オトエツチング・イオン注入、レジスト剥離、あ
るいはウエハ洗浄の処理に伴なう汚染から保護す
る保護膜として形成し、しかもその膜厚は該ポリ
シリコン薄膜を通して上記半導体基板にイオン注
入可能な膜厚で形成することを特徴とする半導体
装置の製造方法。[Claims] 1. A step of forming a gate oxide film on the surface of a semiconductor substrate, a step of forming a polysilicon thin film on the surface of the gate oxide film immediately after forming the gate oxide film, and a step of forming a polysilicon thin film on the surface of the gate oxide film. a step of performing one or more of photoetching, resist stripping, or wafer cleaning, including at least ion implantation, on the semiconductor substrate whose surface is covered with the polysilicon thin film; forming a polysilicon conductive layer, and the polysilicon thin film is formed as a protective film to protect the gate oxide film from contamination caused by photoetching, ion implantation, resist stripping, or wafer cleaning. However, the method of manufacturing a semiconductor device is characterized in that the film is formed to a thickness that allows ion implantation into the semiconductor substrate through the polysilicon thin film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6232285A JPS61220451A (en) | 1985-03-27 | 1985-03-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6232285A JPS61220451A (en) | 1985-03-27 | 1985-03-27 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61220451A JPS61220451A (en) | 1986-09-30 |
JPH0329293B2 true JPH0329293B2 (en) | 1991-04-23 |
Family
ID=13196787
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6232285A Granted JPS61220451A (en) | 1985-03-27 | 1985-03-27 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61220451A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100445058B1 (en) * | 1997-06-30 | 2004-11-16 | 주식회사 하이닉스반도체 | Method for forming gate oxide in semiconductor device |
JP5729571B2 (en) | 2011-07-11 | 2015-06-03 | 栗田工業株式会社 | Metal gate semiconductor cleaning method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4858778A (en) * | 1971-11-22 | 1973-08-17 | ||
JPS59175767A (en) * | 1983-03-25 | 1984-10-04 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS59195859A (en) * | 1983-04-21 | 1984-11-07 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1985
- 1985-03-27 JP JP6232285A patent/JPS61220451A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4858778A (en) * | 1971-11-22 | 1973-08-17 | ||
JPS59175767A (en) * | 1983-03-25 | 1984-10-04 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS59195859A (en) * | 1983-04-21 | 1984-11-07 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS61220451A (en) | 1986-09-30 |
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