JPS6312402B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switched capacitor integrator used, for example, in electronic filters, speech recognition circuits, speech synthesis circuits, etc.

FIG. 1 shows the basic circuit of a switched capacitor circuit, and FIG. 2 shows its equivalent circuit. In FIG. 1, the first contact a of the changeover switch S is the input terminal 11.
The second contact point b is connected to the output terminal 12, and the common connection point c is connected to the ground terminal via the capacitor _CS . Ground potentials Vi _{and Vp} are applied to the input terminal 11 and output terminal 12, and the switch S is switched _S times per second. now,
As shown in FIG. 1a, switch S is connected to input terminal 11.
When connected to the side, the charge Q ₁ charged in the capacitor C _S becomes "Q ₁ = C _S ·V _i ". Next, Figure 1b
When the switch S is connected to the output terminal 12 side as shown in , the charge Q ₂ of the capacitor C _S becomes ``Q ₂ = C _S・
V _p ”. Therefore, switch S is input terminal 1
It is considered that the charge of ΔQ was moved from the input terminal 11 to the output terminal 12 due to the series of operations of switching from the 1 side to the output terminal 12 side.

ΔQ=Q ₁ −Q ₂ =C _S (V _i −V _p ) ...(1) Since the switch S switches _S times per second, the average current i from the input terminal 11 to the output terminal 12 is expressed as i=ΔQ・_S = C _S (V _i −V _p ) _S ...(2) will flow.

If the switching frequency _S of the switch S is sufficiently larger than the frequency of the voltages V _{i and} V _p , the current i becomes equal to the current determined by the instantaneous values of V _i and V _p , and the circuit of FIG. 1 becomes as shown in FIG. Input terminal 11, output terminal 12
This is equivalent to a circuit with a resistor R connected between them. Here, R=V _i −V _p /i=1/ _CS · _S (3).

In other words, a switched capacitor circuit is equivalent to obtaining a resistance R by switching the capacitor C _S as described above, and a switched capacitor integrator is an integrator constructed using this equivalent resistance. It is.

FIG. 3 shows a Miller integrator using an operational amplifier 31, and it is well known that its input/output characteristics are given by the following equation.

V _p /V _i =-1/S・R _S・C _f ...(4) V _i : Input voltage V _p : Output voltage R _S : Between input terminal 11 and inverting input terminal (-) of operational amplifier 31 Input resistance C _f connected between the output terminal and the inverting input terminal (-) of the operational amplifier 31. In Fig. 3, V _DD and V _SS are power supplies, and the operational amplifier 31 The non-inverting input terminal (+) of is grounded.

FIG. 4 shows a Miller integrator configured using a switched capacitor circuit 41 instead of _the resistor R _S in FIG.
This is obtained by substituting R in the previous equation (3) into .

V _p /V _i = - _S /S (C _f /C _S ) ...(5) In other words, the input/output characteristics of the Miller integrator shown in Fig. 4 are determined by the capacitance ratio of capacitors C _S and C _f and the switching of switch S. It is a function of frequency _S , especially a linear expression of frequency _S. This shows that the integration time constant can be changed in proportion to the frequency _S , and if the mirror integrator shown in Figure 4 is used as a filter unit, the filtering frequency can be changed in proportion to the switching frequency _S. becomes possible.

On the other hand, FIGS. 5 and 6 each show a Miller integrator equivalent to _that shown in _{FIG .} It is configured to switch both ends simultaneously. That is, the first contact _a1 of the first changeover switch _S1 is connected to the input terminal 11,
Further _{, the first contact a 2 of the second changeover switch S 2 is} connected to the inverting input terminal (-) of the operational amplifier 31, and the second contacts b ₁ and b ₂ of the switches S ₁ and S ₂ are collectively connected to the reference It is connected to the power supply V _ref (ground potential in this example).

5a and 5b each use a switched capacitor circuit as a resistor having an equivalent positive resistance value. Now, as shown in FIG. 5a, when the changeover switches S ₁ and S ₂ are connected to the second contacts b ₁ and b ₂ , respectively, the charge in the capacitor C _S is discharged and becomes zero. Next, as shown in FIG. 5b, the changeover switches S ₁ and S ₂ connect the first contacts a ₁ and
When connected to the _a2 side, the capacitor C _S is charged with an electric charge Q as shown in the following equation.

Q=C _S (V _i −V _i ′) ……(6) V _i : Voltage of input terminal 11 V _i ′ : Voltage of inverting input terminal (−) of operational amplifier 31 Therefore, capacitor C at this time _The average current i of _S is as _follows , where _S is the _switching frequency of the changeover switches _{S 1 and S 2} . The equivalent resistance R is R=V _i −V _i ′/i=1/ _CS · _S (8), which is similar to the previous equation (3).

6a and 6b each use a switched capacitor circuit equivalently as a negative resistance, _and now, as _shown in _{FIG .} When the capacitor C _S is connected to the side, an electric charge Q as shown in the following equation is charged to the capacitor C S .

Q= _CS・V _i ...(9) Next, as shown in FIG. 6b, selector switch S ₁ ,
When S ₂ is connected to the b ₁ and a ₂ sides, the charge Q in the previous equation (9) is supplied to the inverting input terminal (-) of the operational amplifier 31, and by repeating this switching operation, the equivalent A resistance circuit is constructed.

By the way, as shown in FIGS _. 4 to 6, the switched capacitor integrator used as a mirror integrator requires ₂
terminals and one terminal for the reference power supply V _ref (ground). Therefore, such a switched capacitor integrator can be used with two power supplies (V _DD , V _SS ).
In order to mix it with the normal random logic used, it becomes necessary to add one more power supply terminal.

However, increasing the number of power supply terminals is fatal, especially in integrated circuits. In other words, in integrated circuit design, the design period becomes longer, the chip area of the integrated circuit increases, and pattern design for three power supply terminals becomes difficult.Additionally, the increase in power supply during printed board mounting makes printed board design difficult. However, this would also result in a significant increase in costs.

This invention was made in view of the above-mentioned circumstances, and its purpose is to reduce the number of power supplies used and to create a switch that can be easily integrated into integrated circuits since the number of power supply terminals is small. The present invention provides a capacitor integrator.

An embodiment of the present invention will be described below with reference to the drawings.

When the switched capacitor integrator shown in Fig. 5 and Fig. 6 is made into a single power supply, Fig. 7 and Fig. 8
The result will be as shown in the figure. That is, in FIG. 7, the switched capacitor circuit 70 moves the capacitor C _S to the first contact a ₁ , a ₂ side or to the second contact b ₁ , b ₂ side by means of the changeover switches S ₁ and S 2 that operate _{simultaneously} . It is a switching connection, and the switching frequency is _S.
The first contact _a1 of the changeover switch S1 is connected to the input terminal 71 to which the input voltage V _i is applied, and the first contact _a2 of _the switch _S2 is connected to the inverting input terminal (-) of the operational amplifier 31, The second contacts b ₁ and b ₂ are connected to the power supply V _DD
It is connected to the.

On the other hand, the operational amplifier 31 is supplied with the power supply V _DD voltage and the ground potential GND, and its output terminal is connected to the output terminal 72 and also connected to the inverting input terminal (-) via the capacitor C _f , and the non-inverting input A voltage intermediate between the power supply V _DD potential and the ground potential GND is applied to the terminal (+) by a bias circuit.
This intermediate voltage is generated by the power supply V _DD and GND, and its magnitude is appropriately selected depending on the characteristics of the operational amplifier 31. If you want to obtain, for example, 1/2V _DD as the above intermediate voltage, connect resistors R and R in series between the power supply V _DD and GND, and connect this connection point E to the non-inverting input terminal (+). Bye.

Next, the operation of the circuit shown in FIG. 7 will be explained. Now, as shown in Fig. 7a, when the changeover switches S ₁ and S ₂ are connected to the second contacts b ₁ and b ₂ , both ends of the capacitor C _S are connected to V _DD , and the electric charge is discharged. It has become zero. This state is the fifth state mentioned above.
This is the same as in Figure a. Next, switch
When S ₁ and S ₂ are connected to the first contacts a ₁ and a ₂ as shown in Fig. 7b, the capacitor C _S has Q= _CS (V _i −V _i ′) ...(10 ) _Vi : Voltage at the input terminal 71 Vi _' : The voltage at the inverting input terminal (-) of the operational amplifier 31 is charged. At this time, the average current i of the capacitor C _S is i=C _S (V _i −V _i ′) _S ……(11), and its equivalent resistance R is R=V _i −V _i ′/i=1/ C _S・_S ...(12), and the above equation (12) is the same as the previous equation (3).

Therefore, the circuit shown in FIG. 7 has the same function as the circuit shown in FIGS. 4 and 5 described above, and
This means that the input/output characteristics of the integrator shown in the figure are V _p /V _i = _-S /S (C _f /C _S ), as in the previous equation (5). In other words, the switched capacitor circuit 5 in the circuit shown in FIG.
Even if the reference power supply V _ref connected to 0 is replaced with the operational amplifier power supply V _DD as shown in FIG. 7, by applying a predetermined bias to the non-inverting input terminal (+) of the operational amplifier 31, This means that it will not interfere with its operation.

Similarly, for the circuit shown in FIG.
It can be a single power supply circuit as shown in the figure.

However, in the circuit configuration shown in FIGS. 7 and 8, when a switched capacitor circuit is integrated, there may be problems between the metal wiring and the substrate, or between the P-type diffusion layer and the N-type diffusion layer. Stray capacitance between
_CP is attached. Although this capacitance value can be reduced in design, it is impossible to reduce it to zero.

The problems caused by this stray capacitance C _P will be explained in detail below. In the integrator shown in Fig. 7, which uses the switched capacitor C _S as a positive resistance, in the switching state shown in Fig. a, the stray capacitance
A charge of "Q _P = -C _P ·V _DD " is accumulated in C _P. (The charge on capacitor C _S is zero.) Next, when the switch is switched to the state shown in figure b, current I flows through capacitor C _f by the operational amplifier. This current I is the capacitor C _S when there is no stray capacitance C _P
However, when _a stray capacitance _{C P exists} , _the current I is shunted to _the capacitor C Charge is accumulated in each of C _S and stray capacitance C _P. In addition, in the switching state shown in Figure b, when the integration operation is completed, the inverting input terminal (-) of the operational amplifier 31 becomes at the same potential (1/2V _DD ) as the non-inverting input terminal (+).
Therefore, the stray capacitance C _P has “Q _P = C _P (1/2V _DD −
V _DD )” charge will be accumulated. In other words, due to the change from the switching state shown in figure a to the switching state shown in figure b, "QΔ _P = Q _2P -
The operational amplifier will supply a charge amount of ``Q _1P = _CP 1/2V _DD '', and if the switching frequency is _S , then the current I ₂ flowing through the stray capacitance _CP per second is expressed by the following formula.

I ₂ = QΔ _P・_S = 1/2C _P・V _DD・_S ... (13) At this time, the amount of change QΔ _S in the charge of the capacitor C _S is QΔ _S = Q _2S −Q _1S = C _S (V _i −1/2V _DD )−0, and the current I ₁ flowing through the capacitor C _S is I ₁ =QΔ _{S S} =C _S (V _i −1/2V _DD ) _S (14). Therefore, the total current I is I=I ₁ +I ₂ =C _S (V _i −1/2V _DD ) _S +1/2C _P ·V _DD · _S (15). Now, assuming that there is no stray capacitance _CP , "I=I ₁ ", and when "V _i =1/2V _DD ", "I=I ₁ = 0". In other words, if the input offset voltage is “V _i
= 1/2V _DD . However, if there is stray capacitance, the input offset voltage is determined by solving "I = 0" in the previous equation (15), and becomes V _i = 1/2V _DD -1/2・C _P /C _S V _DD ... (16) becomes. In other words, the input offset voltage is reduced by an amount proportional to the ratio C _P /C _S of the stray capacitance C _P and the switching capacitor C _S . In other words, even if the input potential is 1/2V _DD , the operational amplifier will flow a current of "I = 1/2C _P・V _DD・_S ", and as a result, the integral output will change. You end up doing it. This causes a change in the integral constant of the integrator and a change in the input offset voltage, which is extremely problematic in use.

If the circuit of FIG. 8 is calculated in the same way, the input offset voltage of equation (16) will be as follows.

V _i =1/2V _DD +1/2・C _P /C _S V _DD ...(17) In other words, since this circuit uses a switched capacitor as a negative resistance, the stray capacitance C _P and the switch A change in the input offset voltage caused by the switching capacitor C _S acts in the direction of increasing the offset potential. Of course, in this case, problems similar to those described above also occur.

By the way, to solve this problem, C _P /
All you have to do is make C _S sufficiently small. In other words, the capacitance of the switching capacitor C _S is increased relative to the stray capacitance to increase the ratio between both capacitors. In other words, as mentioned above, there is a limit to the reduction of stray capacitance in integrated circuits, which is 0.01pF to 0.05pF.
Since a certain degree always occurs, there is no way to reduce C _P /C _S other than increasing the capacity of the switching capacitor C _S . However, for example, “C _P
＝0.05pF'', the influence of this stray capacitance C _P is calculated as 1
If it is kept below %, it will be more than "C _S = 5pF". In a normal switched capacitor filter, the C _S /C _f ratio is about 5 to 100, and in this case, the capacitor C _f requires a large capacitance of about ``C _f = 25 pF to 500 pF'', which makes it difficult to integrate into an integrated circuit. In this case, an unacceptable situation arises in which the chip size increases due to an increase in the area occupied by this circuit, and the cost increases accordingly.

In order to eliminate the influence of such stray capacitance, a structure as shown in FIG. 9 or FIG. 10 may be used. Figure 9 shows the circuit shown in Figure 7 with stray capacitance C _P
This shows a circuit that is not affected by
By sequentially repeating the switching operations shown in figures a to d, a switched capacitor integrator is constructed in which the switched capacitor circuit is an equivalent positive resistance. That is, a capacitor C _f is connected between the inverting input terminal (-) and the output terminal of the operational amplifier 31, and a capacitor C f is connected between the operational amplifier power supply V _DD and the ground point at its non-inverting input terminal (+). A predetermined bias is applied by a bias circuit consisting of resistors R and R connected in series. Further, a switching capacitor C _S is provided between the inverting input terminal (-) of the operational amplifier 31 and the signal input terminal 91, and a first and a second switching capacitor C _{S is provided at both ends of the switching capacitor C S.} First and second changeover switches S ₁ and S ₂ are provided as switching means.

Now, in the first operation period shown in FIG. 9a,
When the changeover switches S ₁ and S ₂ are connected to the first contacts a ₁ and a ₂ , respectively, the amount of charge Q _1S of the capacitor C _S
is "Q _1S = 0", and the amount of charge Q _1P of the stray capacitance _CP is "Q _1P = _-CP ·V _DD ". Next, the ninth
In the second operating phase shown in figure b, the changeover switches S ₁ ,
S ₂ are connected to the second contacts b ₁ and b ₂ , respectively, and the charge amount Q _2S of the capacitor C _S is “Q _2S = C _S (V _i −1/2V _DD )”, and the charge of the stray capacitance C _P The quantity Q _2P is “Q _2P = −C _P・
It is 1/2V _DD . In the third operating period shown in FIG. 9c, the changeover switches S ₁ and S ₂ connect to the third contacts c ₁ and
The charge amount Q _3S of the capacitor C _S connected to c ₂ is ``Q _3S =
0", and the stray capacitance Q _3P is "Q _3P = 0".
Furthermore, in the fourth operation period shown in FIG. 9d, the changeover switches S ₁ and S ₂ are connected to the second contacts b ₁ and b _2, respectively, and the charge amount Q _4S of the capacitor C _S is expressed as "Q _4S = C _S (V _i −
1/2V _DD ), and the amount of charge C _4P of the stray capacitance C _P is "C _4P =-C _P 1/2V _DD ."

Considering the total amount of charge movement in the above-mentioned integral operation, the total amount of charge movement ΔQ in the first to fourth operation periods is ΔQ = (Q _2S - Q _1S ) + (Q _4S - Q _3S ) +(Q _2P −Q _1P )+(Q _4P −Q _3P ) =2C _S (V _i −1/2V _DD )+1/2C _P・V _DD −1/2C _P・V _DD =2C _S (V _i − 1/2V _DD ) ...(18) The current I is as shown in the formula below.

I=ΔQ _S /2=C _S (V _i -1/2V _DD )・_S ......(19
) ( _S : switching frequency) Moreover, the equivalent resistance value R of this switched capacitor circuit is R=V _i −1/2V _DD /I=1/ _CS · _S (20). Therefore, it is not affected by stray capacitance _CP .

Fig. 10 shows another embodiment of the present invention, which is an integrator using a switched capacitor circuit as a negative resistance. This is an improved version. In the figure, the same components as those in FIG. 9 are given the same reference numerals, and the explanation thereof will be omitted. That is, the 10th
In the first operating period shown in Figure a, the changeover switch
S ₁ is the second contact b ₁ , changeover switch S ₂ is the first contact a ₂
connected to. Next, in the second operating period shown in FIG. 10b, the changeover switch _S1 is connected to the third contact _c1 , and the changeover switch _S2 is connected to the second contact _b2 . In the third operating period shown in FIG. 10c, the changeover switch S ₁ is connected to the second contact b ₁ and the changeover switch S ₂ is connected to the third contact c ₂ . Further, in the fourth operation period shown in FIG. 10d, the changeover switch _S1 is connected to the first contact _a1 , and the changeover switch _S2 is connected to the second contact _b2 .

In the repetition of cycles in this switching state, the stray capacitance throughout one cycle is
The amount of charge transfer of C _P is expressed by the following formula.

ΔQ _P = (Q _2P - Q _1P ) + (Q _4P - Q _3P ) = {-C _P 1/2V _DD - (-C _P V _DD )} + (-C _P 1/2V _DD -0) = 0 ...(21) Therefore, the stray capacitance C _P has no effect on the integration operation, resulting in a highly accurate single power supply switched capacitor integrator.

By the way, although stray capacitance has been described as a linear capacitance, in an integrated circuit device, switching elements are formed by MOS FETs, so a diffusion junction capacitance, which is a non-linear capacitance, can also be a type of stray capacitance. Therefore, as shown in FIGS. 9 and 10, even if both ends of the switching capacitor C _S are alternately connected to the power supply V _DD or the ground potential GND, the influence of the junction capacitance cannot be canceled out.

FIG. 11 shows the circuit shown in FIG. 9 to which junction capacitances C _jP and C _jN are added. In the figure, C _jN is the junction capacitance that the N-type diffusion layer has with respect to the P-type substrate, and C _jP is the junction capacitance that the P-type diffusion layer has with respect to the N-type substrate. below,
If a potential is written after C _jP or C _jN , it indicates the capacitance when that potential difference is added to the junction capacitance.

In FIGS. 11a to 11d, the amount of charge of C _jP changes as follows.

In the switching state of figure a, "0" In the switching state of figure b, "C _jP 1/2V _DD・1/2V _DD " In the switching state of figure c, "C _jP V _DD・V _DD " In the switching state of figure d, " C _jP 1/2V _DD・1/2V _DD ” Also, the amount of charge of C _jN changes as follows.

Figure a..."-C _jN 1/2V _DD・V _DD " Figure b..."-C _jN 1/2V _DD・1/2V _DD " Figure c..."0" Figure d..."-C _jN 1 /2V _DD・1/2V _DD ” Therefore, since the movement of charge due to stray capacitance is the amount of movement of the sum of C _jP and C _jN in each state, ΔQ=C _jP 1/2V _DD・1/2V _DD −0+C _jP 1/2V _DD・1
/2V _DD −C _jP V _DD・V _DD −C _jN 1/2V _DD・1/2V _DD +C _jN V _DD・V _DD −C _jN 1/
2V _DD・1/2V _DD −0 =V _DD (C _jP 1/2V _DD −C _jP V _DD )−V _DD (C _jN 1/2V _DD
−C _jN V _DD )...(22) That is, the difference between the value of 1/2 V _DD of the juncture capacitance and the value of V _DD becomes the effect of the floating amount.

Next, a method will be described in which the value of equation (22) is set to zero to eliminate the influence of the juncture capacitance.
In equation (22), C _jP 1/2V _DD , C _jP V _DD , C _jN 1/2 V _DD , and C _jN V _DD indicate the capacitance value, and this capacitance value is the capacitance value per unit area. It is the product of the juncture area, and the previous equation (22) can be rewritten as follows.

ΔQ=V _DD A _jP (C′ _jP 1/2V _DD −C′ _jP V _DD ) −V _DD A _jN (C′ _jN 1/2V _DD −C′ _jN V _DD )……(23) Here, A _jP and A _jN are the respective juncture areas of C _jP and C _jN , and C′ _jP and C′ _jN are the juncture capacities per unit area. Therefore, A _jP /A _jN =C′ _jN 1/2V _DD −C′ _jN V _DD /C _jP 1/2V _DD
−C′ _jP V _DD (24) By setting the area ratio of the P-type diffusion layer and the N-type diffusion layer so that The area ratio of this diffusion layer can be easily set at the integrated circuit design stage.

In addition, as another method, the switching operations of figures a and b in Fig. 11 may be performed M times in one cycle.
The switching operations shown in Figures c and d may be performed N times to make one cycle M+N times. Considering the amount of charge movement in this case, including the linear stray capacitance, it is expressed by the following equation.

ΔQ=1/2C _P V _DD・M−1/2C _P V _DD・N=(C _jP 1/2V _DD・1/2V _DD −0)・M+(C _jP 1/2
V _DD・1/2V _DD −C _jP V _DD・V _DD )N = (−C _jN 1/2V _DD・1/2V _DD +C _jP V _DD・V _DD )・M +(−C _jN 1/2V _DD・V _DD −0)・N ……(25) Furthermore, ΔQ=1/2V _DD {C _P (M−N)+C _jP 1/2V _DD・(M
+N) -C _jP V _DD・2・N −(C _jN 1/2V _DD・(M+N)−C _jN V _DD・2・M}...
(26) Transforming the previous equation (26) in the same way as the previous equation (23), ΔQ=1/2V _DD [A _P・C′ _P (M−N) +A _jP {C′ _jP 1/2V _DD・(M+N)−C′ _jP V _DD・
2・N} −A _jN {C _jN 1/2V _DD・(M+N)−C _jN V _DD・2・
M}]...(27) becomes. Therefore, by appropriately setting M and N, the influence of stray capacitance can be reduced. In particular, when the juncture area ratio becomes too large in the above equation (24), the influence of stray capacitance on the integrator can be offset by setting the juncture area ratio and M and N.

In addition, in the above embodiment, a case was described in which the effect of the junction capacitance of an integrator using a switched capacitor as a positive resistance was canceled out, but the effect of the junction capacitance can be canceled in the same way when the switched capacitor is used as a negative resistance. Of course.

Furthermore, in each of the embodiments described above, the bias circuit for applying a potential (for example, V _DD /2) to the non-inverting input terminal (+) of the operational amplifier 31 can be modified in various ways. A circuit with low consumption may be used.

As explained above, according to the present invention, the charge accumulated in the stray capacitance is sequentially discharged to one power supply and the other power supply for the operational amplifier to prevent this charge from being input to the operational amplifier. Since there is no influence from the above, a highly accurate integrated output can be obtained, and a switched capacitor integrator that can be operated with a single power supply can be obtained.

[Brief explanation of the drawing]

Figures 1 a and b are circuit diagrams showing different operating states of the switched capacitor circuit, Figure 2 is the equivalent circuit of Figure 1 above, and Figures 3 and 4 are conventional Miller integrators, respectively. The circuit diagrams, Fig. 5 a, b and Fig. 6 a, b, respectively, are circuit diagrams showing different operating states of a conventional switched capacitor integrator, Fig. 7 a, b, and Fig. 8 a, b, respectively. Figures 9a to 9d are diagrams showing circuits in which the switched capacitor integrators of FIGS. FIGS. 10 and 11 are circuit diagrams showing different operating states of the capacitor integrator, respectively, showing other embodiments of the present invention. 31... operational amplifier, C _f ... capacitor, C _S ...
...switching capacitor, S ₁ , S ₂ ... switch, 91 ... signal input terminal, 92 ... output terminal,
R, R...Resistance, V _DD ...Power supply.

Claims (1)

[Claims] 1. An operational amplifier operated by one and the other of power supplies, a capacitor connected between an inverting input terminal and an output terminal of this operational amplifier, and a non-inverting input of the operational amplifier. a bias circuit connected to one end of the operational amplifier and obtaining a predetermined potential between these power supply potentials from one power supply and the other power supply for the operational amplifier; a signal input terminal to which an input signal voltage is applied; and an inverting input terminal of the operational amplifier; a switching capacitor connected between the switching capacitor and first and second capacitors provided at both ends of the switching capacitor to control charging and discharging of the switching capacitor;
switching means, wherein the first and second switching means connect both ends of the switching capacitor to one power supply for the operational amplifier in a first operation period, and connect both ends of the switching capacitor to one power supply for the operational amplifier in a second operation period. A switching capacitor is characterized in that one end of the switching capacitor is connected to a signal input terminal and the other end is connected to an inverting input terminal of the operational amplifier, so that the first and second operating periods are repeated as appropriate. Capacitor integrator. 2. The bias circuit consists of first and second resistors connected in series between one power source and the other power source for the operational amplifier, and is configured to obtain a predetermined potential from the connection point of these resistors. A switched capacitor integrator according to claim 1, characterized in that the switched capacitor integrator is constructed as follows. 3 an operational amplifier operated by one and the other of the power supplies; a capacitor connected between the inverting input terminal and the output terminal of the operational amplifier; and a capacitor connected to the non-inverting input terminal of the operational amplifier and operating the operational amplifier; a bias circuit that obtains a predetermined potential from one and the other power supply for the amplifier; a switching capacitor connected between a signal input terminal to which an input signal voltage is applied and an inverting input terminal of the operational amplifier; first and second switching means are provided at both ends of the switching capacitor to control charging and discharging thereof, and the first and second switching means control the switching capacitor in a first operation period. One end of the switching capacitor is connected to the signal input terminal and the other end is connected to one power supply for the operational amplifier, and in the second operation period, one end of the switching capacitor is connected to the other power supply, and the other end is connected to the power supply for the operational amplifier. A switched capacitor integrator, characterized in that it is connected to an inverting input terminal and configured to repeat the first and second operating periods as appropriate. 4. The bias circuit consists of first and second resistors connected in series between one power source and the other power source for the operational amplifier, and is configured to obtain a predetermined potential from the connection point of these resistors. 4. A switched capacitor integrator as claimed in claim 3, characterized in that the switched capacitor integrator is constructed as follows. 5 an operational amplifier operated by one and the other of the power supplies; a capacitor connected between the inverting input terminal and the output terminal of the operational amplifier; and a capacitor connected to the non-inverting input terminal of the operational amplifier and operating the operational amplifier; a bias circuit that obtains a predetermined potential from one and the other power supply for the amplifier; a switching capacitor connected between a signal input terminal to which an input signal voltage is applied and an inverting input terminal of the operational amplifier; first and second switching means are provided at both ends of the switching capacitor to control charging and discharging thereof, and the first and second switching means control the switching capacitor in a first operation period. Both ends of the switching capacitor are connected to one power supply for the operational amplifier, and in a second operation period, one end of the switching capacitor is connected to the signal input terminal, the other end is connected to the inverting input terminal of the operational amplifier, and the switching capacitor is connected to the inverting input terminal of the operational amplifier. In the third operating period, both ends of the switching capacitor are connected to the other power supply, and in the fourth operating period, one end of the switching capacitor is connected to the signal input terminal, and the other end is connected to the inverting input terminal of the operational amplifier. A switched capacitor integrator characterized in that the first to fourth operating periods are repeated as appropriate. 6. The bias circuit consists of first and second resistors connected in series between one power source and the other power source for the operational amplifier, and is configured to obtain a predetermined potential from the connection point of these resistors. A switched capacitor integrator according to claim 5, characterized in that it is constructed as follows. 7 an operational amplifier operated by one and the other of the power supplies; a capacitor connected between the inverting input terminal and the output terminal of the operational amplifier; and a capacitor connected to the non-inverting input terminal of the operational amplifier and operating the operational amplifier; a bias circuit that obtains a predetermined potential from one and the other power supply for the amplifier; a switching capacitor connected between a signal input terminal to which an input signal voltage is applied and an inverting input terminal of the operational amplifier; first and second switching means are provided at both ends of the switching capacitor to control charging and discharging thereof, and the first and second switching means control the switching capacitor in a first operation period. One end of the switching capacitor is connected to the signal input terminal and the other end is connected to one power supply for the operational amplifier, and in the second operation period, one end of the switching capacitor is connected to the other power supply, and the other end is connected to the power supply for the operational amplifier. Connect to the inverting input terminal and
In the fourth operation period, one end of the switching capacitor is connected to the above signal input terminal and the other end is connected to the other power supply, and in the fourth operation period, one end of the switching capacitor is connected to one power supply and the other end is connected to the above operation. 1. A switched capacitor integrator, characterized in that it is connected to an inverting input terminal of an amplifier and configured to repeat the first to fourth operating periods as appropriate. 8. The bias circuit consists of first and second resistors connected in series between one power source and the other power source for the operational amplifier, and is configured to obtain a predetermined potential from the connection point of these resistors. 8. A switched capacitor integrator according to claim 7, characterized in that: