JPS63123147A - Checking circuit for storage device - Google Patents

Abstract

PURPOSE:To smoothly continue testing by giving a function interrupting the transmission of the notification that a check circuit develops an error when an unloaded storage unit is selected and specifying a test mode in a variety of tests in the producing step of a computer or in a test at the time of terminating a fault. CONSTITUTION:A load decision circuit 9 controlling the transmission of the error occurrence notification 7 is provided. n-load display signals 8 outputted from n-storage units, an address bus 4 and a test mode specification signal 10 from a processor 1 are put together in the circuit 9, processed and decided. If the storage unit 3 addressed through the address bus 4 is unloaded in a test mode, it is provided with the function to interrupt the transmission of the error occurrence notification 7 to the processor 1. Thus, by specifying the test mode, such a disadvantage can be prevented that the check circuit which always patrols and checks the storage device behaves unnecessary actions to interrupt testing.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a check circuit for a storage device constituting a computer system, and in particular, the present invention relates to a check circuit for a storage device constituting a computer system. This relates to a storage device check circuit that has been improved so that tests and inspections can be performed without conflicting with the so-called "patrol" operation even when some of the storage units are removed from among the multiple storage units installed. be.

[Industrial application field]

As the field of application of computer systems expands, its influence on society becomes greater, and once a failure occurs in a system that is closely connected to society, such as a banking system or seat reservation system, the influence can be enormous and serious. For this reason, the computer system automatically checks each internal part at all times during operation, and detects problems before they occur.
Or, even if a problem occurs, it is common sense to have a function to take countermeasures before the damage spreads.

[Conventional technology]

When a failure occurs in a storage device, especially a main storage device among the components of a computer system, the effects are serious and may lead to malfunctions, system shutdowns, and other situations. For this reason, the storage device constantly checks its read data, and when an error occurs, measures are taken such as restoring the data using an ECC code or notifying the system. Furthermore, under program control, a so-called "patrol" operation is performed in which the contents of the storage device are sequentially read out and checked at fixed time intervals even while the computer system is operating.

An example of a conventional storage device is shown in FIG. According to this example, n memory units 3, which normally have a printed board unit structure, are mounted in the memory device 2 by being inserted into connectors. Here, terminal A is an address input terminal, and terminal A is a data output terminal. When the processing table holder reads data, it sends a storage address to the address bus 4 and issues a read command (not shown). No, I~No,
The memory unit 3 of n decodes the unit designation input, which is usually specified in the upper digit of the address bus 4, and when it determines that it is being addressed, decodes the intra-unit address, which is usually specified in the lower digit. , reads the data and sends it to the data bus 5. The data is checked by a check circuit 6 via a data bus 5. If an abnormality is found in the data, the check circuit 6 sends an error occurrence notification signal 7 to the processing device 1, and also executes a correction operation when an ECC code is used.

In such a system, if any of the storage units 3 is removed and accessed, the read data from that storage unit becomes all 0'' on the data bus 5, and the check circuit 6 It is determined as if a failure has occurred in the storage unit 7 3, and an error display signal 7 is sent to the processing device 1. This operation has a similar effect on the patrol operation.

[Problem that the invention seeks to solve]

As mentioned above, a computer system that constantly performs patrol operations on storage devices may be used with some storage units removed during various tests at the manufacturing stage or during failure recovery tests. May require driving. In such a case, when the patrol operation reaches a storage device address where no storage unit is installed, the check circuit 6 determines as if a failure has occurred in the storage unit, as described above, and causes the processing device to and the program may treat this as a system error, resulting in frequent system outages, etc.
This often interferes with the continuation of the test, and a means to prevent this has been required.

[Means for solving problems]

In order to solve the above-mentioned problems, in the present invention, a mounting determination circuit 9 is added to the data check circuit of the storage bag W2, the principle of which is shown in FIG.

When reading data, one of the plurality of storage units 3 is selected from the processing bag W1 by the address bus 4, the read data is output onto the data bus 5, and the presence or absence of a read error is checked before being sent to the device to be used. Check circuit 6
Checked by. If an error is found in the data as a result of the check, an error signal 11 is generated and an error occurrence notification 7 is sent to the processing device 1.

Here, the present invention provides a mounting determination circuit 9 that controls the sending of the error occurrence notification 7, and tests a total of n mounting display signals 8 output from each of the n storage units, the address bus 4, and the processing device 1. The mode designation signals 10 are collected here, processed and judged, and in the test mode, if the storage unit 3 addressed by the address bus 4 is not mounted, an error occurrence notification 7 is sent to the processing device 1. It has a function to shut it off.

[Effect]

As mentioned above, when the test mode is specified, a function is provided to cut off the error occurrence notification transmission of the check circuit when an unmounted storage unit is selected, and it is possible to perform various tests at the manufacturing stage of the computer, or By specifying a test mode in tests during failure recovery, etc., even if a patrol operation reaches an address in a storage unit that is not implemented, it may be determined that there is a read error on the data bus. Even if the error occurs, the transmission of the error notification to the processing device is blocked, thereby preventing the system from stopping, etc., and allowing the test to continue smoothly.

〔Example〕

FIG. 1 shows the principle of a storage device according to the present invention.

When reading, an address signal designating any one of the storage units 3 (No, 1 to No, n) is sent from the processing device 1 via the address bus 4 to the address input terminal A.
The operation of inputting the data to the data bus 5, outputting the data to the data bus 5, and checking the data in the check circuit 6 is the same as in the conventional example. The gist of the present invention lies in the mounting determination circuit 9. 1 transmitted from the terminals of the n storage units 3 to the mounting determination circuit 9.
Signals such as a book mounting display signal 8, an address bus 4, a test mode designation signal 10 from the processing device, and an error signal 11 from the check circuit are input.

FIG. 3 shows details of an embodiment of the mounting determination circuit 9.

An address signal input from the address bus 4 designates one memory unit 3 and is simultaneously input to the address decoder 21, decoded into one line corresponding to the memory unit number No. 1 to No. It is input to one terminal of the circuit 22. The mounting display signal 8 transmitted from the terminal of each storage unit 3 (No. 1 to No. n) corresponding to the same unit number is input to the input terminal on the other side of the AND circuit 22. As a result, when a certain storage unit is specified, the mounting display signal is "1", that is, when that storage unit is mounted, the AND circuit 22 outputs 1'', and this output is passed through the OR circuit 23. AND circuit 2
Enter 4. If the storage unit 3 specified by the address bus 4 has been removed, the mounting display signal 8 will be O''.
, and "0" appears at the output terminal of the AND circuit 22. Since all the output terminals of the AND circuit 22 are input to the OR circuit 23, the above situation occurs, that is, when the memory unit consisting of the address bus 4 is designated, the mounting indication signal is not output from the memory unit. Then, 0'' appears at the output of the OR circuit 23.The output of the OR circuit 23, the test mode designation signal 10 input from the processing device, and the error signal 11 which is the output of the check circuit 6 are input to the AND circuit 24. Therefore, when the test mode is specified and the storage unit 3 is not installed, the AND circuit is not activated even if the error signal 11 is 24, and the error occurrence notification 7, which is the output of the OR circuit 25, is not transmitted. However, when the mounting display signal 8 is "1",
It is easy to understand that the error occurrence notification 7 is sent normally. Thus, in the test mode, error notifications due to patrolling uninstalled storage units are suppressed, and the object of the present invention is achieved. The above is the operation in the test mode, but the test mode designation signal 10 becomes "0" under normal operating conditions. In this case, the output of the AND circuit 24 is suppressed, and the AND circuit 27 is used to generate the error occurrence notification 7. The test mode designation signal 1o indicates "0" under normal operating conditions, and this input is inverted by the inverter 26 to become "1" and is input to the AND circuit 27. In this state, when the error signal 11 becomes 1'', the output of the AND circuit 27 becomes 1'', and the OR circuit 2
5, an error occurrence notification 7 is sent to the processing device 1, and normal operation is executed.

〔Effect of the invention〕

By implementing the present invention, by specifying a test mode, it is possible to prevent the test execution from being interrupted due to unnecessary operation of the check circuit of the storage device that constantly performs patrol operations. .

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of a storage device check circuit according to the present invention. FIG. 2 is an example of a check circuit for a conventional storage device. FIG. 3 shows a detailed embodiment of the mounting determination circuit 9 according to the present invention. In the figure, 1 is a processing device, 2 is a storage device, 3 is a storage unit, 4 is an address bus, 5 is a data bus, 6 is an error signal, 21 is an address decoder, 23.25 is an OR circuit,
22, 24, and 27 are AND circuits, and 26 is an inverter circuit.

Claims (1)

[Claims] A plurality of storage units (3) each having a function of transmitting a mounting indication signal (8) are mounted on a plurality of connectors and are connected to each other by an address bus (4) inputted from a processing device (1). A storage device (2) in which one of the storage units (3) is selected and executes input/output of information, and when reading, information on the data bus (5) is checked by a check circuit (6) to detect errors. If an error signal (11) is generated by doing so, an error occurrence notification (
7) to the processing device (1), and when the test mode designation signal (10) is being sent from the processing device (1), the test mode designation signal (10) selected by the address bus (4) is provided. A memory characterized by having an implementation determination circuit (9) having a function of blocking transmission of the error occurrence notification (7) to the processing device (1) when the storage unit (3) is not installed. Equipment check circuit.