JPS63122231A - Multilayer circuit board - Google Patents

Abstract

PURPOSE:To make possible a bias test for wiring patterns in a board, which are not being connected to I/O pads, by a method wherein arbitrary ones of pads for bonding the I/O leads of a bare chip to correspond to a die pad on a circuit board are connected to the die pad through the cuttable wiring patterns. CONSTITUTION:As plural pieces of integrated circuit bare chips are mounted on a multilayer circuit board, bonding pads 1, a die pad 20 and groups of wiring patterns 21 are respectively formed at positions to be mounted with those chips. The wiring patterns 21 shall be patterns of a fine line width, which can be physically cut by a cutter and so on or can be fuse-cut with heat, chemical substances and so on. Through these wiring patterns 21, arbitrary ones of the bonding pads 1 and the die pad 20 being surrounded with those bonding pads 1 are electrically connected to each other. Thereby, a bias test can be conducted about a plurality of the wiring patterns easily, simultaneously and furthermore, without being subjected to restrictions on temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer circuit board on which bare chips of a plurality of integrated circuits are mounted and those bare chips are connected by a wiring pattern. Regarding testing patterns.

[Prior Art] In this type of multilayer circuit board having a fine wiring pattern, a voltage higher than a specified voltage value is applied to the signal wiring pattern in order to inspect the presence or absence of pinholes or electromigration within the board. A bias test is performed in which a voltage is applied and the device is exposed to a high temperature atmosphere for a certain period of time.

When performing such a bias test, for conventional multilayer circuit boards, the test terminals are applied to the I/O pads of the circuit board to make it easier to apply the test terminals to the I/O pads.
Previously, only the wiring patterns within the board connected to the pads were tested.

Bias testing also includes wiring patterns that only connect the bonding pads that bond the I/O leads of the integrated circuit bare chip to the circuit board, but are not connected to the I/O pads of the circuit board. If you want to perform a A method was used to apply a bias voltage to each wiring pattern.

[Problems to be Solved] As mentioned above, in conventional multilayer circuit boards, when performing a bias test, if a test terminal is placed on an I/O pad of the circuit board, the internal wiring connected to that I/O pad will be removed. Pattern inspection is possible, but the I/O of integrated circuit bare chips is
It is not possible to inspect a wiring pattern that only connects bonding pads for bonding O-leads to a board, but is not connected to I/O pads of the circuit board.

Furthermore, even if a conductive rubber plate is placed over the board surface for inspection, it is not possible to raise the temperature to high temperatures because the rubber plate is used, and in any case, the bonding pads are not connected to each other. However, there is a drawback in that it is difficult to perform a bias test on wiring patterns within the substrate that are not connected to I/O pads.

[Means for Solving Problems] The present invention, which solves the above conventional problems, provides a multilayer circuit board on which bare chips of a plurality of integrated circuits are mounted and the bare chips are connected by a wiring pattern. A die pad and any one of the pads for bonding the I/O leads of the bare chip corresponding to each die pad to the circuit board are connected by a cuttable wiring pattern.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

In Figure 1, bonding pad 1, die pad 20
, wiring pattern 21 are both formed on the surface of the multilayer circuit board.

The bonding pads 1 are for bonding the T/O leads 122 of one integrated circuit bare chip 120 to be mounted on the die pad 20 surrounded by these to the multilayer circuit board. Furthermore, below the bonding pads 1, VIA holes 61 are formed as shown in FIG.
It connects to the in-board wiring pattern 70 on the inner layer of the circuit board through the insulator.

A plurality of integrated circuit bare chips 120 are mounted on the multilayer circuit board.
1, a bonding pad 1, a die pad 20, and a group of wiring patterns 21 similar to those shown in FIG. 1 are formed at the positions where these chips are to be mounted.
The wiring pattern 70 in the board is the bonding pad ~ I/O
Pads, bonding pads 1 belonging to the same chip, or bonding pads 1 belonging to different chips are interconnected.

The die pad 20 is a pattern formed in the central portion surrounded by the bonding pad 1. This die pad 20 is formed at the location where the integrated circuit bare chip 120 is scheduled to be mounted after the inspection of the multilayer circuit board is completed.
It can be formed to cover approximately the same area as the integrated circuit bare chip 120, and is much larger than the surrounding bonding pads 1, making it easier to contact with test terminals. The die pad 20 is connected to a GND pattern 75 or a power supply pattern in the circuit board by providing a VIA hole 65 therebelow.

The wiring pattern 21 is a pattern with a narrow line width that can be physically cut with a cutter or the like, or cut by heat, chemicals, or the like. This wiring pattern 21 electrically connects any one of the bonding pads 1 to the die pad 20 surrounded by those bonding pads 1. In the embodiment, as shown in the figure, the bonding pad 1 and the die pad 20 are connected to the wiring pattern 2.
Connected with 1.

As a result, the die pad 20, the GND pattern 75 or power supply pattern in the substrate connected to the die pad 20 via the VIA hole 65 under the die pad 20, the bonding pad 1, and the bonding pad 1 under the bonding pad 1. In-board wiring patterns 70 each connected to the bonding pad 1 via the VIA hole 61 located in the
All are electrically connected.

Next, a method of using the embodiment will be explained with reference to FIGS. 2 and 3. FIGS. 2 and 3 are partial cross-sectional views of the multilayer circuit board viewed from the lateral direction.

In FIG. 2, on the multilayer circuit board there is a mounting location of a first integrated circuit bare chip t 20-1 consisting of a bonding pad 1-1, a die pad 20-1 and a wiring pattern 21-1, a bonding pad 1-2, die pad 20-1,
A second integrated circuit bare chip 120-2 comprising a wiring pattern 21-2 is provided.

There are VIA holes 61 under the bonding pads 1-1, 1-2, which are connected to the wiring patterns 70 in the board, and die pads 20-1, 20-2+7).
There is a VIA hole 65 below, which is connected to a GND pattern 75 inside the circuit board. Now, as explained in FIG. 1, by forming the wiring pattern 21-1.21-2, the die pad 20-1.20-2, the GND pattern 75, the bonding pad 1-1.1-2 , the wiring patterns 70 are all electrically connected.

Therefore, when performing a bias test on the multilayer circuit board of the present invention, if the test terminal is applied to the die pad 20-1 or 20-2 and a bias voltage is applied, the bonding pad 1 -1.1
-2 are only connected to each other and not to the I/O pads of the circuit board, making it possible to easily test wiring patterns that are difficult to test with conventional multilayer circuit boards.

FIG. 3 is a sectional view showing the state when the multilayer circuit board shown in FIG. 2 has been inspected and integrated circuit bare chips 120-1 and 120-2 are mounted thereon. After the bias test of the multilayer circuit board is completed, the die pad 20-1.20-2
The wiring pattern 21-1.21-2 connecting the bonding pad 1-1.1-2 is cut. By cutting the wiring patterns 21-1 and 21-2, the bonding pads 1-1 and 1-2 are connected to the die pad 2, respectively.
VIA hole 61 without losing connection with other bonding pads 1 on the substrate surface via 0-1.20-2.
Only the logical connections intended at the time of designing the multilayer circuit board through the wiring pattern 70 and the wiring pattern 70 in the board are valid. Therefore, if the bare chips 20-1 and 20-2 of the predetermined integrated circuit are mounted on this multilayer circuit board after cutting the wiring patterns 20-1 and 20-2, it will have the same circuit function as the conventional multilayer circuit board. can do.

[Effects of the Invention] As explained above, the present invention provides die pads for mounting bare chips in a multilayer circuit board on which bare chips of a plurality of integrated circuits are mounted and the bare chips are connected by wiring patterns, and a die pad corresponding to each die pad. A bonding pad for bonding the F/O lead of a bare chip by connecting any of the pads for bonding the I/O lead of the chip to the circuit board with a wiring pattern that can be cut later. Bias testing has traditionally been difficult for wiring patterns inside a board, because they are only connected to each other and not to the I/O pads on the circuit board. This has the effect of allowing bias testing to be performed without being subject to the above restrictions.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a die pad, a bonding pad, and a wiring pattern of a multilayer circuit board according to an embodiment of the present invention;
FIG. 2 is a partial sectional view of a multilayer circuit board according to one embodiment, and FIG. 3 is a partial sectional view of a bare chip mounted on the multilayer circuit board according to one embodiment. 1: Bonding pad 20: Die pad 21: Wiring pattern 61. 65: VIA hole 70: In-board wiring pattern 75: GND pattern 120: Integrated circuit bare chip 122: Ilo lead

Claims (1)

[Claims] In a multilayer circuit board on which bare chips of a plurality of integrated circuits are mounted and the bare chips are connected by a wiring pattern, a die pad for mounting the bare chips and an I/O of the bare chip corresponding to each die pad are provided.
A multilayer circuit board, characterized in that any of the pads for bonding leads to the circuit board are connected by a cuttable wiring pattern.