JPH01239950A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To execute a burn-in in a state of a wafer by a method wherein two or more signal lines extended to all chips in the transverse direction are installed in all rows and, after the signal lines are connected to two or more signal lines running longitudinally in the center of the wafer, they are connected to an electricity-feeding pad. CONSTITUTION:While a pad 2 for ground connection use is grounded, a ground potential is fed to all chips through ground lines 4, 5. While a voltage is applied to a pad 1 for power-supply use, all the chips become in an electricity-applied state through power supply lines 3, 7. When a wafer 11 is left in high- temperature surroundings in this electricity-applied state, a burn-in in large quantities can be executed in one operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor wafer that can be easily burn-in in the wafer state.

[Conventional technology]

In most conventional semiconductor burn-in processes, the final product is equipped with a dedicated socket and a printed circuit board with wiring.

In addition, in wafer burn-in, the wafer is sandwiched in some way with a substrate or film, etc. that has contact electrodes at positions corresponding to the pads on the chip, and the band and the contact electrodes are brought into contact with each other. energize,
Perform burn-in. In addition, by gathering the electrodes around the wafer and pressing the electrodes with a special socket,
Burn-in is performed by supplying power to all chips.

[Problem to be solved by the invention]

Conventional semiconductor burn-in is performed in the manner described above, which has the following problems.

+1) Burn-in in the product state increases the manufacturing cost of the product. Additionally, the cost of manufacturing the jig for performing the burn-in is significant. There is a limit to the number of ICs that can be burn-in at a time, both in terms of cost and space, such as the size of a single IC.

(2) With the method of bringing contact electrodes into contact with the wafer and supplying electricity, it is difficult to manufacture a substrate etc. with contact electrodes corresponding to the positions of the pads of the chip. I wonder if the positioning of the pad and contact electrode is correct. It is difficult to confirm whether all chips and knobs are making proper contact, and there is a high possibility that chips that do not make contact or cracked wafers will occur. A number of burn-in boards are required depending on the product type.

(3) With the method of gathering electrodes around the wafer, it is difficult to prevent short circuits between the t-source and GND in the peripheral chips.

The present invention has been made to solve the above-mentioned problems. The semiconductor wafer according to the present invention performs low-cost burn-in that allows easy contact positioning in the wafer state. A plurality of signal lines extending to the chip are provided in all rows in the horizontal direction, and these are connected by system to a plurality of signal lines running vertically across the center of the wafer at right angles to these lines.
It is connected to a wide power supply pad provided around the wafer.

[Operation] In this invention, a plurality of signal lines extending to all the chips in one horizontal row are provided in all rows in the horizontal direction, and these are connected to a plurality of signal lines running vertically across the center of the wafer according to the system, so that the power supply around the wafer is By connecting to the pads, the voltage, ground, and other input signals applied to the power pads are supplied to each chip from a signal line extending to each chip via a signal line that traverses the center of the wafer. Burn-in becomes possible, and a large amount of burn-in can be performed at one time. Further, it becomes easy to prevent short circuits between the burn-in signal line and other circuits in the peripheral area, and contact positioning becomes easy. Furthermore, it becomes possible to share burn-in equipment and jigs.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, ▪ indicates a power supply pad, and 2 indicates a GND connection pad, which are formed with a sufficient size at the edge of the wafer. Also, 3 is a power line that cuts through the center of the wafer, 4 is a GND line that cuts through the center of the wafer, and 5 is a GN line.
A GND line short-circuited to the D line 4, 6 a scribe line, 7 a power supply line short-circuited to the power supply line 3, 8 a scribe line, and 11 a wafer. Among these, pad 1.2, power line 3゜7, GND
Aluminum patterns for burn-in are formed on lines 4 and 7.

By connecting GND connection pad 2 to GND,
By supplying the GND potential to all chips through the GND lines 4 and 5 and applying a voltage to the power supply pad 1, all the chips become energized through the power supply lines 3 and 7. Thereafter, the wafer 11 is left in a high temperature environment to perform burn-in.

Burn-in of such semiconductor wafers results in lower product costs than burn-in of final products.

Furthermore, since the burn-in signal power supply path is not product-specific, it can be handled with a common jig, and there is no need to manufacture costly burn-in jigs for each product type. Furthermore,
In terms of space, the burn-in on the wafer-like Lt is warmer and smaller than the burn-in on the final product, so it is possible to perform a large amount of burn-in at one time. Furthermore, since a sufficiently large power supply band is used, positioning at the time of contact is also easy. Further, in order to prevent the signal line from short-circuiting to other parts at the periphery of the wafer, an aluminum pattern of about 11 meters in length from the periphery of the wafer can be easily removed by etching. Further, the wafer manufacturing method is easy, and the number of wafer process steps is minimal.

Note that in the above embodiment, the signal line is connected to the power supply line and GND.
This shows two types of input signals, such as a line and a line, but this is a three-way line in which other input signals, such as a clock signal line, are added.
There may be more than one type.

Furthermore, by providing a check pad to confirm whether burn-in bias is reliably applied to the power supply pad, more reliable burn-in can be achieved.

An example of such a case is shown in FIG. 2, and will be explained. In FIG. 2, 9 and 10 are check pads, 12
is a voltmeter.

When the GND connection pad 2 is grounded and a voltage is applied to the power supply pad 1, check whether the specified voltage is applied to the check pads 9 and 10 connected to the @source line 3 and GND line 4, respectively. can be checked with the voltmeter 12.

Here, it goes without saying that instead of the voltmeter 12, a light emitting diode or the like can be used for constant monitoring.

〔Effect of the invention〕

As described above, according to the semiconductor wafer according to the present invention,
Multiple signal lines extending to all chips in one horizontal row are provided in all horizontal rows, and these are connected to multiple signal lines that run vertically across the center of the wafer, which are then connected to power supply pads around the wafer. All the chips on the wafer can be energized through the signal line that runs from the power supply band to the center of the wafer, making it easy to position the chips in the event of contact and prevent short circuits at the periphery, making it easier to burn-in the wafer. A large amount of burn-in can be performed, a common jig can be used, and the product cost can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a surface view showing a semiconductor wafer according to one embodiment of the invention, and FIG. 2 is a diagram showing a semiconductor wafer according to another embodiment of the invention. 1 is a power supply band, 2 is a CND connection pad, 3 and 7 are power lines for burn-in, 4 and 5 are GND lines for burn-in, 6 and 8 are scribe lines, 9
is a check pad connected to power supply pad 1,
10 is a check pad connected to the GND connection pad 2, 11 is a wafer, and I2 is a voltmeter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Each horizontal row has multiple signal lines that electrically connect all the chips in one horizontal row to each other, and the signal lines in all the horizontal rows are grouped by signal system and placed at the edge of the wafer. A semiconductor wafer comprising a plurality of vertical signal lines in the center of the wafer for connection to a power supply pad having a large area.