JPS63119570A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a high-performance transistor with a minute configuration, by constituting a base layer with a recrystallized semiconductor film. CONSTITUTION:A wafer, in which an n-type layer 3 that is to become a collector layer is epitaxially grown on a high resistance p<-> type single crystal Si substrate 1, is used. An n<+> type embedded layer 2 is formed between the substrate 1 and the n-type layer 3. A p-type base layer 5, which is formed on the n-type layer 3, is obtained by recrystallizing a silicon film, which is deposited by a CVD method, by annealing. On the p-type base layer 5, an n-type emitter layer 6, which is formed with a silicon film deposited by a CVD method is provided. Since the base layer and the emitter layer are formed with the CVD films, the impurity concentration of the base layer is made especially high, and the width of the base is made thin. Thus a transistor having a step shaped ideal p-n junction is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a bipolar transistor and a method for manufacturing the same.

(Prior Art) A conventional general bipolar integrated circuit is obtained by using a Si epitaxial wafer, using an epitaxial layer as a collector layer, and forming a base layer and an emitter layer by ion implantation. More specifically, for example, a high-resistance p-type Si substrate is used to selectively diffuse and form an n+-type layer that will become a collector buried layer, and then the n-type layer that will become a collector layer is epitaxially grown. Next, insulating films for element isolation and collector/base isolation are formed by selective oxidation. Normally, prior to forming this isolation insulating film, selective etching is performed on the location where the insulating film is to be formed, and the device strength tm
A p+ type layer serving as a channel stopper is formed in the region by ion implantation. Thereafter, a base layer is formed by boron ion implantation and activation, and then an emitter layer is formed by arsenic ion implantation and activation. Finally, the emitter, base, and collector electrodes are formed using the A.degree. C. film to complete the process.

With such conventional structures and methods, when transistors are further miniaturized, it is difficult to control the impurity concentration and thickness of each region with high precision. That is, since the base layer and emitter layer are formed by ion implantation, it is difficult to obtain a thin base layer with a high impurity concentration. This is because there is a limit to increasing the impurity concentration through ion implantation, and because heat treatment is essential to activate the impurities after ion implantation, impurity re-diffusion occurs.
This is because it is difficult to form an ideal stepped pn junction.

(Problems to be Solved by the Invention) As described above, the conventional bipolar integrated circuit has a problem in that it is difficult to further miniaturize the elements and improve performance.

It is an object of the present invention to solve these problems and provide a fine bipolar transistor that exhibits high performance and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) A bipolar transistor according to the present invention is characterized in that a base layer is formed of a recrystallized semiconductor film.

The method of the present invention involves depositing a semiconductor film doped with impurities on a substrate on which a collector layer is formed, annealing and recrystallizing this to form a base layer, and then forming an emitter layer by depositing a semiconductor film or by ion implantation. It is characterized by forming a layer.

(Function) According to the present invention, by forming the base layer from a deposited semiconductor film, the impurity concentration in the base layer can be made sufficiently high. Further, since recrystallization annealing involves local heating, re-diffusion of impurities in the base layer can be almost ignored, and an ideal step junction can be obtained as a pn junction between the base and the collector. Therefore, it is possible to obtain a fine, high-performance bipolar transistor with a small base width and a high impurity concentration in the base layer.

Furthermore, according to the method of the present invention, since the base layer is formed by depositing an impurity-doped semiconductor film, it is easier to control the impurity concentration and base width than the conventional method, which requires ion implantation and high-temperature heat treatment. It's easy. Therefore, a high performance bipolar transistor can be obtained. Moreover, since semiconductor film deposition can be performed at low temperatures, manufacturing costs can also be reduced.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing one npn transistor in a bipolar integrated circuit according to an embodiment of the present invention. In this embodiment, a wafer is used in which an n-type layer 3 serving as a collector layer is epitaxially grown on a high-resistance p-type single crystal 3i substrate 1.

An n"-type buried layer 2 is formed between the substrate 1 and the n-type layer 3. 41 is an element isolation oxide film, and 42 is a base-collector isolation oxide film. On the n-type layer 3 The p-type base layer 5 formed on the p-type base layer 5 is formed by recrystallizing a silicon film deposited by CVD by annealing. There is a type emitter layer 6.7.8.9
are the emitter, base, and collector electrodes, respectively, and 1
o is an n+ type layer for taking out the collector, and 11 is a p2 type layer as a channel stopper.

FIGS. 2(a) to 2(h) are cross-sectional views showing the manufacturing process of this npn transistor. First, as shown in (a>, ρ
A blank film 21 is formed on the - type Sil board 1 by thermal oxidation, and openings are formed in this by selective etching.
b) is diffused to form an n+ type buried layer 2. Then the second
As shown in Figure (b), the oxide film 21 is removed and an n-type layer 3, which will become a collector layer, is formed by epitaxial growth, and an oxide film 22 formed by thermal oxidation and a nitride film formed by CVD are formed on the obtained epitaxial wafer. (Si3N4
)23 is formed. Then, as shown in FIG. 2C, the laminated film of 1m22 oxide and 11123 nitride is selectively etched to expose the convex surface of the wafer, and using this laminated film as a mask, the n-type layer 3 is etched to a predetermined thickness. Thereafter, as shown in FIG. 2(d), the element isolation oxide film 41 is formed by high temperature oxidation.
And the MVA film 42 between the base and the collector is applied to the substrate 1.
Form to a depth that reaches . Prior to this thermal oxidation, boron (8>) is ion-implanted into the element isolation region of the wafer to form a p+ type layer 11 that will serve as a channel stopper under the element isolation oxidized PIA 4x. After this, the nitride film 23 is removed. After that, phosphorus (P) is diffused into the collector extraction region to form an n+ type 1110 that lowers the collector resistance, and then a photoresist mask 24 is formed and the oxide film in the base layer formation region is etched to form the convex surface of the wafer. expose.

Then, a p-type substitute layer 5 is formed on the exposed n-type layer 3, as shown in FIG. 2(f). To explain the process of forming this p-type substitute layer 5 in more detail, first, plasma CVD is used.
Amorphous 5ill doped with boron by method (
Alternatively, a microcrystalline 3i film, polycrystalline 3i film) is deposited, laser annealed to recrystallize it, and selectively etched to leave it only in the base region. Selective etching may occur before laser annealing. Only the base region needs to be recrystallized by laser annealing, and since the deposited 511M is in contact with the single-crystal 3i wafer 8, the wafer crystal serves as a seed crystal and the annealing process produces high-quality 511M. A crystalline layer can be obtained. After this, Figure 2 (
As shown in Q), an oxide film 25 (or an insulating film such as a nitride film may be used) is deposited by CVD to form an emitter! [
An IC opening is provided, and n-type 5ills doped with a high concentration of AS are deposited by plasma CVD, and this is patterned to form an n-type emitter 6. Finally, Figure 2 (h)
As shown in the figure, a contact window is opened for each electrode, and an A2 film is deposited and patterned to form the emitter and base.

The collector electrodes 7, 8, and 9 are formed to complete the npn transistor.

Thus, according to this embodiment, since the base layer and emitter layer are formed by CVD films, the impurity concentration of the base layer is particularly high, and the base width is made thin and an ideal step-like pn junction is formed. Realizes a transistor with a lot of power. Therefore, integrated circuits having high performance transistors with fine dimensions can be manufactured at low cost.

FIG. 3 is a sectional view showing a transistor portion of a bipolar integrated circuit according to another embodiment of the present invention.

Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. The difference from FIG. 1 is that the n-type emitter layer 6' is formed by ion implantation and heat treatment.

FIGS. 4(a) to 4(h) show the manufacturing process of this transistor section in correspondence with FIGS. 2(a) to (h). This is basically the same as FIGS. 2(a) to 2(h), except that in FIG. 4(Q), an n-type emitter layer 6' is formed by As ion implantation and heat treatment.

This embodiment also provides the same effects as the previous embodiment.

The present invention is not limited to the above embodiments, but can be implemented with modifications as listed below.

(a) Although an npn transistor has been described in the embodiment, the present invention can be applied to a pnp transistor by reversing the conductivity type of each part.

(b) For the recrystallization treatment of the deposited semiconductor film, in addition to laser annealing, lamp annealing using infrared light or visible light, electron beam annealing, etc. can be used.

(C) In the embodiment, the case where the substrate and the deposited film were 81 was described, but as a combination of the substrate and the semiconductor film to be deposited, mutually different materials such as Sl and Ge can be used. Of course, it is also possible to combine compound semiconductors. Thereby, a heterojunction can be introduced into the emitter junction or the collector junction.

(d) In the embodiment, a transistor with a so-called emitter-top structure in which the collector layer is formed on the substrate side is shown, but the present invention can be similarly applied to a collector-top structure in which the emitter layer is formed on the substrate side. It is possible.

[Effects of the Invention] As described above, according to the present invention, the width of the base layer and the impurity concentration are excellently controllable, and it is possible to realize a high-performance microtransistor having an ideal step-like pn junction. .

Further, according to the present invention, excellent fine transistors can be manufactured at low cost, and bipolar integrated circuits using fine transistors can be improved in performance and reduced in cost.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a transistor section of an integrated circuit according to one embodiment of the present invention, FIGS. 2(a) to (h) are sectional views showing the manufacturing process thereof, and FIG. 3 is an integrated circuit of another embodiment. FIGS. 4(a) to 4(h) are cross-sectional views showing the manufacturing process thereof. DESCRIPTION OF SYMBOLS 1... P-type wheel crystal 3i substrate, 2... N+ type buried layer, 3... N-type layer (epitaxial growth 1i!>, 4
t. 42... Isolation oxide film, 5... P-type base layer (plasma CVD-8i film), 6... N-type emitter layer (Braz?CVD-8+R''), 6'-n-type emitter layer (ion injection layer), 7 to 9... electrode, 10... n+ type layer,
11... p4' 4-layer type applicant's representative Patent attorney Takehiko Suzue] Figure 1 Figure 2 (1) Φ Moan ---
? ``+' (71C y+-++ Figure 4 (1) Ma ＾ X
--Cn:

Claims (6)

[Claims] (1) A bipolar transistor characterized in that the base layer is composed of a recrystallized deposited semiconductor film. (2) A bipolar transistor according to claim 1, wherein the emitter layer is formed of a deposited semiconductor film. (3) The bipolar transistor according to claim 1, wherein the emitter layer is formed of an ion-implanted layer. (4) Depositing a semiconductor film doped with impurities in contact with the collector layer of the single crystal semiconductor wafer on which the collector layer has been formed, and recrystallizing the deposited semiconductor film by annealing to form a base layer. A method for manufacturing a bipolar transistor, comprising: a step of forming an emitter layer in contact with the base layer. (5) The method of manufacturing a bipolar transistor according to claim 4, wherein the emitter layer is formed of a semiconductor film deposited in contact with the base layer. (6) The emitter layer is formed by doping impurities into the base layer by ion implantation.
A method for manufacturing a bipolar transistor as described in Section 1.