JPS63118944A - Data processor - Google Patents

Abstract

PURPOSE:To perform a various kinds of shift operations simultaneously, by providing plural processing units to process list data of list form. CONSTITUTION:The elements of the list data of list form accumulated in a memory device 1 is assigned and transferred one by one to the register device of the processing unit 3. It is required to perform the shift operation such as CAR shift, and CDR shift, etc., for all of the elements of the data of list form, however, it is possible to execute the operation in one cycle because each processing unit 3 can perform the operation in parallel. In such way, it is possible to perform a various kinds of shift operations in an ADDRESS part of list form simultaneously, thereby, to perform the processing of the list data at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data processing device mainly intended for use in the field of artificial intelligence.

BACKGROUND OF THE INVENTION In recent years, the field of artificial intelligence has been actively researched as one of computer applications. In this field, it is necessary to process structured data, and therefore LISP, a language that can handle structured data, is widely used. Since it is inefficient to execute the LISP language on a general-purpose computer, special-purpose machines with various improvements have been developed.

These dedicated machines have been improved mainly by approaching from the language aspect, and the typical improvements are shown below. (Primitive functions such as IICAR and CDR are executed at the microprogram level. (2) Data format with TAG to handle generic data type. (3) Provide hardware control stack to speed up stack processing (for example, rLIsP machine" Information Processing Vol. 23 N118 pp
752-772).

Problems to be Solved by the Invention However, although improvements have been made to the execution system of the language as described above, the representation of structure data inside a computer is basically based on pointer order relationships and connection methods of elements. Because it uses a representation (hereinafter referred to as a list), there were the following problems. (1) Access to any element is inefficient as it involves going through a list.
(2) List matching is inefficient because it involves a list decomposition operation. (3) Garbage collection is difficult.

(4) Poor locality of memory references, resulting in cache failure.

rate decreases. Additionally, since it basically uses a shared structure, the following problems arose. (51 RPLACA.

Direct list operations such as in RPLACD cause unexpected side effects such as secretly changing other data. (6) It is difficult to lock variables during parallel processing. In order to solve these problems, it is basically necessary to change the expression of list data.

A binary tree list starts from the starting node and branches left and right sequentially, ending at each leaf node.The 0-leaf node has two nodes: an atom node and an NTL node.
There are different types. A node that is not a leaf node is a list node indicating that the branch is continuing. This list node is used to indirectly indicate the position of the leaf node.

In the pointer representation, this structural representation is expressed as is by cells in which all nodes are connected by addresses.

However, if the positions of leaf nodes can be directly determined, there is no need to have list node information.

Therefore, equivalent list data can be expressed by a table in which leaf position information and leaf information are sequentially arranged. We adopted a one-dimensional vector representation in which numbers are sequentially assigned in the CDR direction and items are sequentially assigned in the CAR direction as a method of expressing the node positions of this leaf. Therefore, the list data is expressed as a set of data that includes a vector indicating leaf position information and information about the leaf itself.

FIG. 3 shows an example of list data representation. This shows the diagrammatic representation (al and tabular representation) of list data that becomes (A (B (C)) D) when expressed in 3 formulas. 0 In the diagrammatic representation, the circle is a list node. , and the squares indicate leaf nodes.

Further, the number string added above each node indicates the node position expressed according to the above-described method. This leaf part is extracted and expressed in the form of a table, which is expressed in tabular form (
b), which consists of a table in which the ADDRESS section contains node position vectors and the VALUE section contains leaf elements.

When a list is represented in such a tabular form, many of the drawbacks of the pointer representation described above can be avoided, but the arithmetic system is naturally different from the conventional pointer representation.

FIG. 4 shows an example of a behind-the-scenes operation in the basic list operation function of LISP.

As is clear from Figure 4, the CAR function extracts the element with the first 1 in the ADDRESS section, and
By shifting SS toward the beginning (hereinafter referred to as C
(referred to as AR shift). Contrary to the CAR function, the CDR function is executed by removing the element whose leading ADDRESS is 1 and subtracting 1 from the leading ADDRESS of the remaining elements (hereinafter referred to as CDR shift).

The C0N5 function is a little more complicated.

First, regarding the first argument of the C0N5 function, go to 〇DIIES
Shift the S section in the opposite direction to the beginning direction, and move the beginning ADDR
Let ESS be 1. This is an operation opposite to the above-mentioned CAR shift, and is hereinafter referred to as RCAR shift. For the second argument, 1 is added to the leading ADDRESS (hereinafter this is referred to as RCDR shift for the same reason as RCAR). Next, the C0N5 function is executed by combining these two arguments into one table.

As described above, the basic LISP functions such as CAR, CDR, and C0N5, which can be performed extremely easily in pointer representation, have the drawback of requiring calculations for all elements in table format.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a data processing device that has a simple configuration and can efficiently process list data in a tabular format.

Means for Solving the Problems In order to solve the above problems, the data processing device of the present invention includes a memory device that stores list data as tabular data, and a processing unit that includes a plurality of registers and calculation means. It is equipped with a plurality of arithmetic units and a transfer device that sequentially allocates elements of tabular data stored in a memory device to each processing unit, so that list data can be processed in parallel.

Effect of the Invention With the above-described configuration, the present invention transfers elements of tabular list data from a memory device to a plurality of processing units that process tabular list data so as to sequentially allocate them one by one. This allows various shift operations of the ADDRESS section to be performed simultaneously.

Embodiment Hereinafter, a data processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a data processing device in an embodiment of the present invention.

In FIG. 1, 1 is a memory device, 2 is a transfer device, 3 is a processing unit, 4 is a condition register, 5 is a second register device, 6 is a second arithmetic unit, 7 is a second memory means, and 8 is a It is an arithmetic device consisting of multiple processing units. FIG. 2 shows the internal configuration of the processing unit in the above embodiment.

In FIG. 2, 11 is a register device, 12 is a shift device, 13 is a comparison device, and 14 is a gate device.

The operation of the data processing apparatus configured as described above will be explained below using FIG. 1 and Part 2.

When the list data stored in the memory device W1 is processed, the transfer device 2 transfers it to the register device 11 of the processing unit 3.
transferred through the shift device 12. In this case, each element of the tabular data is transferred to a separate processing unit. The register device 11 is composed of a plurality of registers that are storage units, and one of them is selected by a selection signal R3. The various operations listed above are performed on data in registers. In the case of a CAR operation, the contents of the register selected by the selection signal R3 are inputted through the comparator 13 to the shifter 12, where the contents receiving the aforementioned CAR shift are inputted into the register again. CD
The same applies to the R operation, and the shift operation becomes a CDR shift. As described above, this shift operation must be performed on all elements of the tabular data, but since this operation is performed in parallel in each processing unit, it can be performed in one cycle.

When operating the CAR, CDR, etc., the memory device 1
You can also do this at the same time as transferring list data from. That is, when the transfer device 2 transfers the list data to the register device 11 of the processing unit 3, it passes through the shift device 12, so the shift operation may be performed at this time. In this case, shift processing can be performed at the same time as transfer, so processing can be performed at high speed.

An example of the internal configuration of the shift device 12 is shown in FIG.

In FIG. 5, 51 is an input selection circuit, 52 is a barrel shift circuit, and 53 is an adder circuit.

In FIG. 5, the input selection circuit 51 switches and outputs transfer data from the memory device 1 and data fed back from the register in the processing unit 3 using a selection signal SEL. In the case of a register operation, an AI signal is output.

The data output from the input selection circuit 51 is ADDRES.
It is separated into an S section and a VALUE section, and the ADDRESS section data AD becomes the input of the barrel shift circuit 52, and the - side VA
The LUE section data VD becomes part of the output RD of the shift device 12 as it is. Barrel shift circuit is ADDRESS
This circuit shifts the data of the section in the left-right direction, and is controlled by a shift selection signal SHC. When performing a CAR shift, the shift is towards the beginning as described above, but in this case, 0 is entered in the last address.

Conversely, during RCAR shift, 0 is entered at the beginning.

CDR shift and RCDR shift are not so-called shift operations, but operations that increase or decrease the leading value of the ADDRESS section by 1, so they are not shifted by the barrel shift circuit.
This process is performed by an adder circuit 53 connected to its output.

References to atom data are stored in the VALUE section of each element of the tabular list, but list processing requires calculations on the actual values, such as numerical values and characters. The calculation is not performed by the processing unit but by the second calculation device 6. First, the reference value of the list element is output from the processing unit 3 to the data bus DB, the second memory device 7 storing the actual value is accessed, and the value is stored in the second register device N5.

Thereafter, arithmetic processing is performed between the second register device 5 and the second arithmetic device 6, and the result is stored in the second memory device 7 again.

In this way, by separating the processing of structural data and the processing of values, the configuration of the processing system can be simplified.

Comparison operations are important operations for list data. This is a test to check whether the structure and atom elements of two list data are equal. In point expression, both lists are decomposed into elements using the same procedure, and by testing whether those elements are equal. In the table format, where the identity of list structure data is checked, one element is compared with the other one after another, and for every element, its AD
If the DRESS part and the VALUE part are equal, it can be seen that they are the same. What is particularly powerful about the tabular representation is that matching of partial lists can be easily performed by allowing wild numbers as part of ADDRESS. An example of the ASSOC function is shown in FIG. Here, * indicates a wild number and indicates matching with any number. Using this method, it is possible to relatively easily perform processing that is difficult with conventional pointer methods, such as extracting a part with a specific structure from certain structured data. This process is performed by the comparator 13.

FIG. 7 shows an example of the configuration of a comparison circuit of the ADDRESS section, which is a part of the comparison device 13. In FIG. 7, 61 is a wild number detection circuit, 62 is a match detection circuit, and 63 is a wild number detection circuit.
is an OR gate circuit, and 64 is an AND gate circuit. In FIG. 7, the comparison data CD stored in the condition register 4 in FIG. be done. The wild number detection circuit 61 detects a wild number that is a predetermined specific number that matches all the numbers in the comparison data, and outputs a defeat signal to the OR gate circuit 63 when the comparison data is a wild number. do. Therefore, the OR gate circuit 63 outputs a match signal to the AND gate circuit 64 when CD and RED match or when CD is a wild number. AND gate circuit 6
4 outputs FLAG as a signal indicating that the addresses match when all match signals for each item are present.

This comparison operation can also be performed at high speed because it is simultaneously performed by a plurality of processing units for each element of the list data, as described above.

Effects of the Invention As described above, the present invention provides a memory device that stores list data as tabular data, an arithmetic device that includes a plurality of processing units each consisting of a plurality of registers and arithmetic means, and a memory device for each processing unit. Equipped with a transfer device that sequentially allocates elements of tabular data stored in the device, and sequentially allocates elements of tabular list data one by one from a memory device to a plurality of processing units that process tabular list data. By transferring data in the following manner, various shift operations of the ADDRESS section of tabular data can be performed simultaneously in the processing unit.
This allows list data to be processed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is an internal block diagram of the processing unit in FIG. 1, FIG. 3 is a diagram showing an example of table format representation of list data, 4
The figure shows an example of a table operation in the basic list operation function of LISP, Figure 5 is an internal configuration diagram of a shift device, Figure 6 is an explanatory diagram when a wild number is used to execute the ASSOC function, and Figure 7 2 is a configuration diagram of a comparison circuit of the ADDRESS section, which is a part of the comparison device 13 in FIG. 2. FIG. l...Memory device, 2. Old transfer device, 3.
...Processing unit 7), 8... Arithmetic unit. Name of agent Patent attorney Toshio Nakao and one other person Figure 2 e DB Figure 3 (A (B (c)) D) ALIIJKbNS% VALUE
Sound list Figure 4 5 (A ce+) (Co)d (e#'
(A (♂))'+CI+υ%' (LA fil e
D) Figure 5 Scale Figure 6 Figure 7

Claims (1)

[Claims] A memory device that stores list data as tabular data, an arithmetic device that includes a plurality of processing units each consisting of a plurality of registers and arithmetic means, and elements of tabular data stored in the memory device for each processing unit. What is claimed is: 1. A data processing device comprising a transfer device that sequentially allocates list data, and is capable of processing list data in parallel.