JP2005284683A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor registering a more accurate input-output group in a command section storage means in reusing a function. <P>SOLUTION: A dependence storage part M shows which input address and input value each output address and output value originate in. An interlinear AND comparing part MR computes AND between the interlinear components stored in the dependence storage part M and sets the input-output group comprising an output pattern including one ore more output addresses and output values, and an input pattern including one or more input addresses and input values. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data processing apparatus that performs a process of reading an instruction section from a main storage unit and writing a result of an arithmetic process into the main storage unit.

  2. Description of the Related Art Conventionally, research and development relating to a technique for increasing the operation speed of a microprocessor such as a CPU (Central Processing Unit) has been actively conducted. Examples of the speed-up technology include pipeline, superscaler, out-of-order execution, and register renaming.

  Pipeline is a technique that decomposes instruction execution processing into several stages, and flows a plurality of instructions and performs simultaneous processing. Superscaler is a technology that prepares two or more instruction execution circuits and executes a plurality of instructions simultaneously in parallel. Out-of-order execution is a technique for ignoring the description order of instructions and searching for the first executable instruction among several consecutive instructions and performing a preceding process. Register renaming is a technique for increasing the probability that parallel processing is performed by increasing the number of general-purpose registers while maintaining compatibility of instructions in a conventional processor, for example, in a CISC (Complex Instruction Set Computer) type processor. .

  Thus, in order to increase the calculation speed in the microprocessor, it is important to execute instructions in parallel. However, most of the programs include a dependency relationship in which different instructions are executed depending on the result of a certain instruction, in other words, a branch. When such a branch is included, if processing is performed in advance by parallel processing, a situation occurs in which the content of the preceding processing is wasted depending on the result of the branch, and the calculation speed is increased. There is a problem that the effect of.

  Therefore, when there is a branch in the program, many studies have been made on a technique for reducing the probability that the preceding process is wasted by predicting the branch destination and improving the effect of parallel processing, so-called branch prediction.

  However, when speculative preceding processing is performed based on branch prediction, there are generally the following problems. The first problem is that the execution time of the preceding instruction sequence itself cannot be reduced because it is necessary to always verify the correctness of the prediction. As a second problem, since it is necessary to invalidate a series of predecessor operation results based on erroneous prediction, in order to increase the number of instructions that can be speculatively processed at once, a corresponding hardware cost is required. That is the point. As the third problem, the more the dependency between instructions, the more it becomes necessary to carry out speculative predecessor processing, and the verification validity verification process and the invalidation process based on erroneous prediction are extremely complicated. Is that it becomes.

  On the other hand, a technique called value reuse has also been proposed as a speed-up technique different from branch prediction. In this value reuse, input values and output values related to a part of the program are registered in the reuse table, and when the same part is executed again, the input values are registered in the reuse table. Is a technique of outputting a registered output value. The effects of this value reuse include the following. (1) If the input value matches the input value registered in the reuse table, there is no need to verify the execution result. (2) The hardware cost is determined only by the total number of input values and output values, and the length of the instruction sequence that can be omitted is not restricted. (3) The degree of dependency between instructions does not affect the complexity of the reuse mechanism. (4) Redundant load / store instructions can be reduced, and power consumption can be reduced accordingly.

  Non-Patent Document 1, which will be described later, shows a technique for reusing values for functions in a program. In this prior art, a load module is generally used in accordance with ABI (Application Binary Interface), and in particular, SPARC (Scalable Processor ARChitecture) ABI is used. Then, value reuse is realized by specifying input / output of a function in this ABI. That is, it is not necessary to embed a dedicated instruction by a compiler for value reuse, and application to an existing load module is possible.

  Also, by dynamically grasping the multiplex structure of functions, local registers in the function and local variables on the stack are excluded from input / output values in value reuse, thereby improving efficiency. For functions in particular, regardless of the complexity of the function, reuse and pre-execution are possible by registering a maximum of 6 register inputs, a maximum of 4 register outputs, and a minimum main memory value that does not include local variables. ing. This prior art will be described in detail below.

  First, for a single function, we will clarify what is input and what is output, and explain the mechanism required to perform one-level reuse. In a program, functions generally form multiple structures. FIG. 15A shows a structure in which the function A (Function-A) calls the function B (Function-B).

  The global variable (Globals) can be an input / output (Ain / Aout) of the function A and an input / output (Bin / Bout) of the function B. The local variable (Locals-A) of the function A is not an input / output of the function A, but can be an input / output of B through a pointer. An argument (Args) from function A to function B can be an input to function B, and a return value (Ret.Val.) From function B to function A can be an output from function B. It is. The local variable (Locals-B) of the function B is not included in the input / output of the function A and the function B.

  In order to reuse the function B without depending on the context, only the input / output Bin / Bout of the function B must be registered as the input / output when the function B is executed. Here, FIG. 15B shows a memory map in the main memory when executing the program structure shown in FIG. In this memory map, only the Locals-B area does not include Bin / Bout. Therefore, in order to identify Bin / Bout, the boundary between Globals and Locals-B and the boundary between Locals-B and Locals-A must be determined, respectively. For the former, the OS (Operating System) generally determines the upper limit of the data size and stack size at the time of execution, and the boundary between Globals and Locals-B is determined based on the boundary (LIMIT) set by the OS. It can be confirmed. For the latter, the boundary between Locals-B and Locals-A can be determined by using the value of the stack pointer (SP in A) immediately before B is called.

Next, a method for identifying whether a given main memory address is a global variable or a local variable of which function will be described. It is assumed that the load module satisfies the following conditions specified in SPARC ABI. Note that% fp means a frame pointer, and% sp means a stack pointer.
(1) Of the areas above% sp,% sp + 0 to 63 are register save areas, and% sp + 68 to 91 are argument save areas, which are not function inputs / outputs.
(2) An implicit argument (Implicit Arg.) For returning a structure is stored in% sp + 64 to 67.
(3) An explicit argument (Explicit Arg.) Is placed in an area of registers% o0 to 5 and% sp + 92 or more.

First, in order to distinguish between a global variable and a local variable, generally, the OS determines the upper limit of the data size and stack size at the time of execution, and assumes the following matters.
(1) Global variables are placed in the area below LIMIT.
(2)% sp never falls below LIMIT, and the area from LIMIT to% sp is invalid.

  FIG. 16 shows an outline of arguments and frames in the memory map when the function A calls the function B while satisfying the above conditions. A method for distinguishing the local variable A and the local variable B will be described below with reference to FIG.

  In the figure, (a) shows a state in which A is being executed. Instructions (Instructions) and global variables (Global Vars.) Are stored in a thick frame part less than LIMIT, and valid values are stored above% sp. In% sp + 64, the head address of the structure is stored as an implicit argument when B returns the structure. The first 6 words of the explicit argument for B are stored in registers% o0 to 5 and the seventh and subsequent words are stored in% sp + 92 or more. When an operand% sp + 92 having a base register% sp appears, this area is the seventh word of the argument, that is, a local variable of B. On the other hand, if the operand% sp + 92 does not appear, this area is a local variable of A. Thus, in the state (a), the local variable of A and the local variable of B can be distinguished by verifying the operand.

  On the other hand, (b) shows a state in which B is being executed. Arguments can be input, return values can be output, global variables and A local variables can be input / output. However, since B may accept a variable-length argument, it is generally impossible to determine whether the area of% fp + 92 or more is the local variable area of A or the local variable area of B.

  In order to distinguish local variables, first, the function call that detects the seventh word and the following of the argument at the time of (a) is excluded from the reuse target, and the function call that does not detect the seventh word and later is immediately before% sp + 92. Record the value of. In addition, since the appearance frequency of function calls using the seventh word and later is expected to be low, it is considered that the performance degradation due to the restriction that the function using the seventh word and later is excluded from reuse.

  From the above preparation, it can be seen that when the main memory reference address in (b) is greater than or equal to the previously recorded value of% sp + 92, it is a local variable of A, and if it is smaller, it is a local variable of B. At the time of execution of B, the global variable and the local variable of A are registered in the reuse table while excluding the local variable of B.

  At the time of reuse, since the local variable of B is excluded from input / output, the address of the local variable of B does not need to match. Therefore, any context can be reused as long as the input matches. However, for the global variable referenced by B and the local variable of A, both the address and data need to completely match the contents of the reuse table. That is, the point is how to cover the main memory addresses to be compared before executing B.

  The address of the global variable referred to by B or the local variable of A is originally based on an address constant generated in B or a pointer originating from the global variable / argument. Therefore, first, by selecting an entry in the reuse table whose arguments completely match, by referring to all the related main memory addresses and performing a matching comparison, it is possible to cover the main memory addresses that B should refer to. it can. The registered output (return value, global variable, and A local variable) can be reused only when all the inputs match.

  In order to realize function reuse, a function management table (RF) and an input / output record table (RB) are provided as reuse tables. A hardware configuration necessary for reusing one function is shown in FIG. To make a plurality of functions reusable, a plurality of sets of this configuration are prepared.

  In this table, V held in RF and RB is a flag indicating whether or not an entry is valid, and LRU (least recently used) indicates a hint for entry replacement. In addition to the above V and LRU, the RF holds the start address (Start) of the function and the main memory address (Read / Write) to be referred to. In addition to the above V and LRU, RB includes% sp (SP) immediately before the function call, argument (Args.) (V: valid entry, Val .: value), main memory value (Mask: Read / Write address) Holds valid byte, Value: value), and Return Values (V: valid entry, Val .: value).

  The return value is stored in% i0 to 1 (read as% o0 to 1 in the leaf function) or% f0 to 1, and the return value using% f2 to 3 (extended double precision floating point number) is not included in the target program. Assume that it does not exist. The read address is collectively managed by the RF, and the mask and value are managed by the RB, thereby enabling a configuration in which the contents of the read address and a plurality of entries of the RB are compared at once by a CAM (content-addressable memory).

  To reuse a single function, first, input / output information related to arguments, return values, global variables, and local variables of higher-level functions is registered in the reuse table while excluding local variables when the function is executed. . Here, the argument register preceded by reading is registered as the input / output of the function, and the writing to the return value register is registered as the output of the function. Other register references do not need to be registered. Similarly, in the main memory reference, an address preceded by reading is registered as input and writing as output.

  When the next function is called before returning from the function, or the input / output to be registered exceeds the capacity of the reuse table, the seventh word of the argument is detected, a system call or interrupt occurs in the middle, etc. If no disturbance occurs, the registered I / O table entry is validated when the return instruction is executed.

Hereinafter, with reference to FIG. 17, before calling a function, (1) a function head address is searched, (2) an entry whose arguments completely match is selected, and (3) an associated main memory address, that is, All read addresses for which at least one mask is valid are referred to, and (4) match comparison is performed. When all the inputs match, the execution of the function can be omitted by writing back the registered output (return value, global variable, and A local variable).
IPSJ Journal: High Performance Computing System, HPS5, pp.1-12, Sep. (2002), "High-speed technology using function value reuse and parallel pre-execution" (Yasuhiko Nakajima, Katsuya Ogata, Shingo Masanishi) Masahiro Goto, Junichiro Mori, Toshiaki Kitamura, Junji Tomita) (issued on September 15, 2002)

  In the above prior art, in the RB, each entry needs to be registered as a different entry if the contents of even one item are different. Therefore, the memory utilization efficiency in the RB is not good. Also, if there is even one difference between the input pattern of the function to be executed and the input pattern included in each entry of the RB, reuse cannot be performed.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a data processing apparatus that can register a more accurate input / output group in the instruction section storage means for reuse. It is to provide.

  In order to solve the above problems, the data processing apparatus according to the present invention is a data processing apparatus for performing a process of reading a command section from a main storage unit and writing a result of arithmetic processing into the main storage unit. First arithmetic means for performing an operation based on the instruction section read from the first register, a register used when the first arithmetic means reads and writes to the main storage means, and the arithmetic operation of the instruction section is performed by the first arithmetic means. Input / output generation means for generating an input / output group composed of an input pattern and an output pattern when performed, and an instruction interval storage means for storing the input / output group generated by the input / output generation means. When the instruction means executes the instruction interval, the input pattern of the instruction interval and the input stored in the instruction interval storage means are stored. When the pattern matches, a re-use process for outputting the output pattern stored in the instruction section storage unit corresponding to the input pattern to the register and / or the main storage unit is performed, and the input / output generation unit includes: Based on the dependency storage unit that indicates which input element included in the input pattern is derived from each output element included in the output pattern, and information stored in the dependency storage unit 1 Input / output group setting means for setting an input / output group composed of an output pattern including the above-described output elements and an input pattern including one or more of the input elements is provided.

  In the above configuration, when the first calculation means executes the instruction section, if the input pattern of the instruction section matches the input pattern stored in the instruction section storage means, the input section corresponds to the input pattern. Thus, a reuse process for outputting the output pattern stored in the instruction section storage means to the register and / or the main storage means is performed. The input pattern and the output pattern stored in the instruction section storage unit are generated by the input / output generation unit.

  The input / output generation means includes an output pattern including one or more output elements based on information indicating which input element included in the input pattern originates from each output element included in the output pattern; An input / output group including an input pattern including one or more input elements is set, and the set one or more input / output groups are generated. Therefore, in comparison with the case where the input pattern and output pattern when a certain instruction section is executed are simply registered in the instruction section storage means, a more accurate input / output group is used in the instruction section storage means for reuse. It becomes possible to register. Therefore, it is possible to improve the search efficiency when reusing.

  Further, in the data processing device according to the present invention, in the above configuration, the input / output group setting means is configured such that a set of input elements that are the origins of a certain first output element is a source of another second output element. An input / output group in which the input element set that is the origin of the second output element is an input pattern, and the first output element and the second output element are output patterns It is good also as a structure which sets.

  In the above configuration, when a set of input elements that are the origins of a certain first output element are all included in the set of input elements that are the origins of another second output element, these are one input element. Will be grouped into output groups. Therefore, it is possible to delete redundant input / output groups, and therefore it is possible to prevent redundant registration of input / output groups in the instruction section storage means.

  In the data processing apparatus according to the present invention, in the above configuration, the input / output group setting means includes a set of input elements that are the origin of a certain first output element and the origin of another second output element. A first input element set as an input pattern and a first output element as an output pattern when there is no common input element with the input element set. A configuration may be adopted in which a second input / output group is set in which an input / output group and a set of input elements that are the origin of the second output element are input patterns, and the second output element is an output pattern.

  According to the above configuration, when there is no common input element in the two input / output groups, the input / output groups are set as separate input / output groups. Here, the case where there is no common input element means that the respective input / output groups have no dependency relationship with each other. In other words, when reusing, even if only part of the input pattern and output pattern in the previously executed instruction section match, it can be reused, so it can be reused The probability of becoming can be increased.

  In the data processing device according to the present invention, in the configuration described above, the dependency storage unit includes a two-dimensional array memory in which each output element is a row component and each input element is a column component. Each memory element of the dimensional array memory may be configured to hold information on whether or not the output element corresponding to the row component of the memory element originates from the input element corresponding to the column component of the memory element. Good.

  In the above configuration, the information indicating which input element included in the input pattern originates from each output element included in the output pattern is indicated by the two-dimensional array memory. Therefore, the above information can be stored for each memory element of the two-dimensional array memory by a simple process of storing 1 or 0, for example, and each row is obtained by performing a logical operation on each memory element, for example. It becomes possible to easily grasp the relationship between components.

  In addition, in the data processing apparatus according to the present invention, in the above configuration, when the instruction section is calculated by the first calculation means, the data processor is read when reading from the register and / or the main storage means is performed. The entry output generating means (1) When the address of the register and / or the main storage means from which the reading has been performed is registered as an output element in the dependency relation storing section, the dependency storing section corresponding to the output element Processing for temporarily storing a provisional matrix composed of row components, (2) The address of the read register and / or main storage means is not registered in the dependency storage unit as an output element, but depends on as an input element When registered in the relationship storage unit, a temporary row in which the memory element corresponding to the column of the dependency relationship storage unit corresponding to the input element is 1 and the other memory elements are 0 And (3) when the address of the register and / or main storage means from which the reading has been performed is not registered in the dependency storage unit as either an output element or an input element, Registers the address and value as input elements in the dependency storage unit, and temporarily stores a temporary matrix in which the memory element corresponding to the column of the dependency storage unit corresponding to the input element is 1 and the other memory elements are 0 When the writing to the register and / or main storage means is performed, the input / output generation means is (4) the address of the written register and / or main storage means is the output element If it is registered as, the output value corresponding to the registered output element is updated to the value that was written and already registered A process of replacing the row component of the dependency storage corresponding to the force element with the logical sum of all the temporary matrices temporarily stored at that time, and then initializing the temporary matrix temporarily stored; 5) When the address of the re-register and / or main storage means to which writing has been performed is not registered as an output element, the address and value are registered as an output element in the dependency relationship storage unit and correspond to the output element A configuration may be adopted in which the row component in the dependency relationship storage unit is replaced with the logical sum of all the temporary matrices temporarily stored at that time, and then the temporarily stored temporary matrix is initialized.

  By performing the above process, the input / output relationship when a certain instruction section is executed, that is, each output element included in the output pattern originates from which input element included in the input pattern. Information about whether or not there is can be accurately stored in the two-dimensional array memory of the dependency storage unit.

  In the data processor according to the present invention, in the above configuration, the input / output group setting unit includes an inter-row logical product comparison unit that performs a logical product operation between the respective row components in the two-dimensional array memory. The entry output group setting means extracts a set of row components in which the logical product of the inversion of a certain first row component and a certain second row component is all 0 in the dependency storage unit, and the extracted row component Of the sets, the row components other than the row component including the most input element sets may be set out of the input / output group.

  In the above configuration, by performing the logical product of the row components, the row components other than the row component including the largest number of sets of input elements are set out of the input / output group. By this processing, when the set of input elements that are the origins of a certain first output element are all included in the set of input elements that are the origins of other second output elements, these are output as one input / output. The grouping will be realized. Therefore, since redundant input / output groups can be deleted, it is possible to prevent redundant registration of input / output groups in the instruction section storage means.

  In the data processor according to the present invention, in the above configuration, the input / output group setting unit includes an inter-row logical product comparison unit that performs a logical product operation between the respective row components in the two-dimensional array memory. The entry output group setting means may be configured to set, as an input / output group, row components whose logical products are all 0 with respect to any other row components in the dependency storage unit.

  In the above configuration, by performing the logical product of the row components, the row components that are independent of the other row components are set as an input / output group. By this processing, it is possible to extract input / output groups that do not have a common input element, in other words, that have no dependency relationship with each other, so when performing reuse, the input pattern in the previously executed instruction section Even when only a part of the output pattern matches, it is possible to perform reuse.

  In the data processing apparatus according to the present invention, in the above configuration, the command interval storage means stores input pattern storage means for storing a plurality of the input patterns as a tree structure in which items to be compared for comparison are regarded as nodes. It is good also as a structure provided.

  According to the configuration described above, items common to a plurality of input patterns can be stored as one node, so that the redundancy of stored contents in the input pattern storage unit can be reduced. Therefore, since the storage capacity required for the instruction section storage means can be reduced, the cost of the data processing apparatus itself can be reduced.

  When the input pattern storage means is configured by, for example, an associative search device, there is a high possibility that past input patterns are grouped and registered, so that a plurality of input patterns are searched simultaneously. It becomes possible to increase the possibility. That is, it is possible to more effectively enjoy the merit of long latency and high throughput, which is a characteristic of a general associative search device. In addition, since the possibility that past input patterns are divided into groups and registered becomes high, the hit rate of the input pattern at the time of reuse can be improved.

  Further, in the data processing apparatus according to the present invention, in the above configuration, the input pattern storage means stores the value of the item to be compared and matched in the input pattern in correspondence with the item to be compared next. Therefore, the above tree structure may be realized.

  In this case, since it is possible to sequentially match and compare items to be matched, it is possible to realize storing an input pattern as a tree structure in which the items to be matched and compared are regarded as nodes.

  In the data processing device according to the present invention, in the above configuration, the input pattern storage means includes an associative search means and an additional storage means, and the associative search means stores the values of items to be matched and compared. One or more search target lines each having a value storage area for storing the key for identifying the item, and the additional storage means performs the following for each corresponding line corresponding to the search target line: It is good also as a structure which has the search item designation | designated area | region which stores the item which should perform an associative search.

  In this case, when the value of the item to be matched and compared is input to the associative search means, the search target line whose value and key match is single matched, and the corresponding line in the additional storage means corresponding to the single match search target line Thus, the item to be subjected to the associative search next is determined.

  Here, since each input pattern is stored as a tree structure in which items to be matched and compared are regarded as nodes, in the associative search means, there is one search target that matches for a certain item as described above (single Match). While an associative search memory having only a single match mechanism is generally marketed, an associative search memory that can report multimatches with the same performance as a single match is generally not commercially available. That is, according to the above configuration, since a commercially available associative search memory can be used as an associative search means, the data processing device according to the present invention can be realized in a shorter period of time and at a lower cost.

  In the data processing apparatus according to the present invention, as described above, the second calculation means sets the predicted input value that is expected to be input in the future with respect to the instruction section being processed by the first calculation means. On the basis of the calculation of the instruction section, the result may be registered in the instruction section storage means. In this case, the second arithmetic unit performs an operation based on the predicted input value for the instruction interval currently being processed by the first arithmetic unit, and the result is stored in the instruction interval storage unit. It will be. Therefore, next, when the same command section appears and the same input as the predicted input value is made, the value stored in the command section storage means can be reused. For example, in the case of an instruction interval in which the input value changes monotonously, the predicted input value is likely to be correct, so the effect of the above configuration is high.

  In the data processing device according to the present invention, as described above, the input / output generation unit is dependent on which input element included in the input pattern is derived from each output element included in the output pattern. Based on information stored in the relationship storage unit and the dependency storage unit, an input / output group including an output pattern including one or more output elements and an input pattern including one or more input elements is set. Input / output group setting means. As a result, in comparison with the case where the input pattern and the output pattern when a certain instruction section is executed are simply registered in the instruction section storage means, a more accurate input / output group is used for the reuse of the instruction section storage means. Can be registered. Therefore, it is possible to improve the search efficiency when reusing.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 14 as follows.

(Configuration of data processing device)
FIG. 2 shows a schematic configuration of the data processing apparatus according to the present embodiment. As shown in the figure, the data processing apparatus includes an MSP (Main Stream Processor) 1A, an SSP (Shadow Stream Processor) 1B, an instruction interval storage unit (instruction interval storage means) 2 as a reuse table, and a main memory ( Main storage means) 3 is provided, which reads out program data and the like stored in the main memory 3, performs various arithmetic processes, and performs a process of writing the arithmetic results into the main memory 3. In the configuration shown in the figure, the configuration includes one SSP 1B, but the configuration may include two or more. Moreover, although the configuration shown in FIG. 6 is provided with the SSP 1B, it may be configured without the SSP 1B. Operations and effects when the SSP 1B is provided will be described later.

  The instruction section storage unit 2 is memory means for storing data for reusing instruction sections such as functions and loops in a program. Details of the command section storage unit 2 will be described later.

  The main memory 3 is a memory as a work area of the MSP 1A and the SSP 1B, and is constituted by, for example, a RAM (Random Access Memory). For example, programs and data are read to the main memory 3 from an external storage means such as a hard disk or an external device such as an external input / output (I / O) device, and the MSP 1A and SSP 1B are read to the main memory 3. The calculation is performed based on the obtained data. Also, the calculation result by the MSP 1A is written in the main memory 3, and the calculation result is sent to the external device.

  The MSP 1A includes an RW (input / output generation unit) 4A, a calculator (first calculation unit) 5A, a register 6A, and a Cache 7A as reuse storage units. Similarly, the SSP 1B includes an RW (second arithmetic unit) 4B, a calculator (second arithmetic unit) 5B, a register 6B, and a Cache / Local 7B as reuse storage units. .

  RW4A and 4B are reuse windows, and hold each line of RF (additional storage means) and RB (associative search means) (to be described later) currently being executed and registered as a ring structure stack. . The actual hardware structure of the RWs 4A and 4B includes a set of control lines that activate a specific line in the instruction section storage unit 2. As will be described in detail later, the RWs 4A and 4B generate an input / output pattern for the executed instruction section, and perform processing for registering the generated input / output group as an execution result in the instruction section storage unit 2. .

  The arithmetic units 5A and 5B perform arithmetic processing based on the data held in the registers 6A and 6B, and are called ALUs (arithmetic and logical units). The registers 6A and 6B are storage means for holding data for performing calculations by the calculators 5A and 5B. In this embodiment, it is assumed that the arithmetic units 5A and 5B and the registers 6A and 6B conform to the SPARC architecture. The Caches 7A and 7B function as cache memories between the main memory 3 and the MSP 1A and SSP 1B. In SSP1B, Cache7B includes Local7B as a local memory.

(Configuration of instruction section storage)
FIG. 1 shows a reuse table realized by the instruction interval storage unit 2 in the present embodiment. As shown in the figure, the instruction interval storage unit 2 includes RB, RF, RO1 (second output pattern storage means), and RO2 (first output pattern storage means).

  The RB includes a value (value storage area) for storing a register value or a main memory input value, which is a value to be compared, and a key (key storage area) for storing a key number. There are multiple.

  RF is an end flag E indicating that there is no register number or main memory address to be compared next, a comparison required flag indicating that the contents of the register number or main memory address to be compared next is updated, and then comparing R / M indicating whether the object to be registered is a register or main memory, Adr. (Search item designation area) indicating the register number or main memory address to be compared next, UP indicating the line number referenced immediately before (stored in parent node) Area), Alt. (Comparison item specification area) indicating the register number or main memory address to be compared with priority over the register number or main memory address to be compared next, and necessary for priority comparison DN (comparison key designation area) indicating a correct key is provided corresponding to each line in the RB.

  RO1 and RO2 store an output value to be output to the main memory and / or a register when it is determined that reuse is possible based on the search results by RB and RF. RO1 stores an output value and an address to be output in one-to-one correspondence with each line of RF. RO2 stores output values and addresses to be output when the output values cannot be stored by RO1 alone. When it is necessary to read the output value from RO2, a pointer storing the output value at RO2 is shown in the corresponding line at RO1, and the output value is read from RO2 using this pointer. .

  Further, the RB and the RF are configured by a CAM (content-addressable memory) and a RAM (Random Access Memory), respectively. Generally, when an address is given, a memory that can refer to a value stored at the address is a memory called a RAM. On the other hand, the CAM is a memory called an associative memory, and when a content to be searched is given, a line that matches the content is selected. Normally, CAM is used as a set with RAM.

  Here, the cooperative operation between the CAM and the RAM will be described with a specific example. "5, 5, 5, 5, 5", "1, 3, 1, 1, 1", "1, 3, 3, 5, 2", "6, 6, 6, 6, 6" The data strings “5, 5”, “1, 1”, “1, 2”, “6, 6” are stored in the RAM corresponding to the data strings in the CAM. Suppose that it is registered. Here, when “1, 3, 3, 5, 2” is input to the CAM as the data string to be searched, the matching entry is turned ON, and the corresponding data “1, 2” registered in the RAM is output. Will be. The above RB and RF are realized by the same configuration and operation as this specific example.

(Comparative example)
Here, as a comparative example, the operation by the RF and RB having the configuration shown in FIG. 8 will be described. As shown in the figure, RF indicates a status display flag V indicating whether or not an entry is valid, an LRU indicating an entry replacement hint, an F / L for distinguishing a function from a loop, and a head address of an instruction section. And Start indicating the end address of the instruction section, Read indicating information related to the main memory input address to be referred to, and Write indicating information related to the main memory output address to be referred to.

  RB is a status display flag V indicating whether the entry is valid, an LRU indicating an entry replacement hint, an SP indicating the stack point% sp immediately before calling the instruction section, an end address of the loop (End ), Taken / not indicating the branch direction at the end of the loop, argument (Args.) (V: valid entry, Val .: value) as register input value, and register input value and condition code other than argument (Regs., CC) ), Main memory input valid byte Mask, Main memory input value Value, Main memory output valid byte Mask, Main memory output value Value, Return value Return value as register output value, and register output value and condition code other than return value Regs., CC (V: Valid entry, Val .: Value) are held.

  When a function or loop is executed, it is determined in the following procedure when it is determined whether or not a previously executed instruction section can be reused. First, (1) a search is made as to whether a start address Start of a function or loop entry registered in RF matches the start address of the corresponding function or loop. If there is a match, (2) among the corresponding entries registered in the RB, an entry whose status display flag V indicating a valid entry is set to the registered state, and in the entry Selects one or more entries whose arguments args. And Regs., CC exactly match the corresponding value of the function or loop to call. In the selected entry, (3) the main memory is sequentially referred to using the relevant main memory address, that is, the read address where at least one mask is valid, and (4) the main memory input value of the corresponding function or loop. And the main memory input value registered in the RB. When all inputs match, (5) Return Values stored in the RB are written to the register, and the main memory output value in which each valid flag Mask is sequentially set for the main memory output address. Write Value. As described above, the reuse of the function or loop is realized.

  The operation in the comparative example as described above will be described more specifically with reference to FIG. First, the program counter (PC) and the instruction section start address (Region) registered in the RF are compared, and the register contents (Reg.) And the register input values (Args.,. Regs., CC). At this time, it is assumed that entry 03 and entry 04 are determined to match among entries 01 to 04 in RB. That is, at this point, it is a multi-match.

  Next, comparison is made with respect to the main memory address A1, but for the main memory address A1, a flag (0) indicating that it is not necessary to perform a coincidence comparison is shown in RF. Is not done. That is, entry 03 and entry 04 remain as candidates.

  Next, a comparison is made with respect to the main memory address A2. Here, in the RF, the flag (1) indicating that it is necessary to perform a coincidence comparison with respect to the main memory address A2 is shown, so the coincidence comparison is performed. As a result, only the entry 03 whose content is “00” remains as a candidate. Thereafter, there are main memory addresses A3 and A4 as items to be subjected to coincidence comparison. However, since both of them indicate a flag indicating that it is not necessary to perform coincidence comparison, entry 03 includes all of the items requiring comparison. The item matches. Therefore, the main memory output value and the register output value as the output values corresponding to the entry 03 are output to the main memory and the register.

  The points of operation in this comparative example are as follows. (A) When comparing each value registered in the RB with the corresponding value in the function or loop to be reused, the vertical columns in the RB are sequentially checked for coincidence. It is allowed that multiple entries with the same content exist (multi-match). (B) Although multi-matching is permitted during the search, one entry may be finally selected. (C) Since the order in which the columns in the RBs are checked for coincidence is arbitrary, it is possible to compare, for example, register input values together first.

  In addition, this comparative example has the following problems. (D) In RB, the number of items (horizontal length) in each entry is fixed. Therefore, items other than the registered items cannot be added. On the other hand, the memory area corresponding to the item that is not used is an empty area, but this cannot be used effectively. (E) Each entry must be registered as a separate entry if the contents of one item are different. Therefore, the memory utilization efficiency in the RB is not good.

  In the case of the comparative example as described above, the memory constituting the RF and RB has a horizontally long structure. For example, if this memory capacity is 2 Mbytes, the horizontal width is 2 Kwords and the vertical length is 256 entries.

(First configuration example for registering an input pattern as a tree structure)
In the above comparative example, the horizontal row as each entry in the RB includes all items of input values to be subjected to matching comparison. That is, all input patterns are registered in the RB as one entry.

  On the other hand, in the first configuration example, items of input values to be subjected to coincidence comparison are divided into short units, each comparison unit is regarded as a node, and an input pattern is registered as a tree structure in RF and RB. It has become. Then, when reusing, by sequentially selecting matching nodes, it is determined whether or not reusable is finally possible. In other words, portions common to a plurality of input patterns are combined into one and associated with one line of RF and RB.

  As a result, redundancy can be eliminated and the utilization efficiency of the memory constituting the instruction section storage unit 2 can be improved. Also, since the input pattern has a tree structure, it is not necessary to associate one input pattern with an entry as one row in the RB. Therefore, it is possible to vary the number of input value items to be subjected to coincidence comparison.

  Also, since RF and RB register their input patterns as a tree structure, multimatching is not performed when matching comparison is performed. That is, the instruction interval storage unit 2 can be realized as long as it is an associative search memory having a single match mechanism. Here, while an associative search memory having only a single match mechanism is generally marketed, an associative search memory capable of reporting multimatches with the same performance as a single match is not generally marketed. That is, according to the instruction section storage unit 2 in the first configuration example, since a commercially available associative search memory can be used, the data processing apparatus according to the present embodiment can be realized in a shorter period of time and at a lower cost. Is possible.

  Next, a specific example of the associative search operation in the instruction section storage unit 2 in the first configuration example will be described with reference to FIG. First, when execution of an instruction interval is detected, a program counter (PC) and register contents (Reg.) Are input to the RB. Then, in the RB, these values inputted by the associative search are compared with the instruction section start address and the register value registered in the Value column of the RB, and the only line (line) in which the values match is found. Selected as a candidate (match line). In this example, the “01” line in the RB is selected as the match line.

  Next, “01”, which is the address in the RB of the line selected as the match line, is transmitted to the RF as an encoding result, and the line in the RF corresponding to the key 01 is referred to. In the RF line corresponding to the key 01, the comparison required flag is “0”, and the main storage address to be compared is A1. That is, it is not necessary to perform a coincidence comparison on the main memory address A1.

  Next, using the key 01, a search is performed on the Key column in the RB. In this example, the line “03” in RB is selected as the match line. Then, the key 03 is transmitted to the RF as an encoding result, and the line in the RF corresponding to the key 03 is referred to. In the RF line corresponding to the key 03, the comparison required flag is “1”, and the main storage address to be compared is A2. That is, it is necessary to perform a coincidence comparison on the main memory address A2. Here, the value of the main memory address A2 in the main memory 3 is read via the Cache 7A, and in RB, the value is the value read from the main memory 3, and the key is “03”. A line is searched. In the example shown in FIG. 3, there are two lines “04” and “05” whose Key is “03”. However, since the value read from the main memory 3 is “00”, “05” "Is selected as a match line, and the key 05 is transmitted to the RF as an encoding result.

  When the above processing is repeated and a termination flag E indicating that there is no register number or main memory address to be compared next is detected in RF, it is determined that all the input patterns match, and the corresponding instruction section Is determined to be reusable. Then, a “Select Output” signal is output from the line in which the termination flag E is detected, and output values corresponding to the lines stored in RO1 and RO2 are output to the register 6A and the main memory 3.

As described above, the associative search operation by the instruction section storage unit 2 in the first configuration example has the following characteristics. First, since there is only one match line in the RB indicating that the contents match, it is only necessary to transmit one encoded result when propagating the search operation to the next column. Therefore, one set (N) of signal lines connecting the RB and the RF may be sufficient as the result of address encoding. On the other hand, in the comparative example described above, multi-matching is allowed in the RB. Therefore, it is necessary to provide ( ^2N ) signal lines for connecting each column in the RB for each line. . That is, according to the configuration of the first configuration example, the number of signal lines in the associative search memory configuring the instruction section storage unit 2 can be significantly reduced.

  Further, since only a single match is allowed during the search, the comparison order of items to be compared is limited to the reference order in the tree structure. That is, it is necessary to compare the register value and the memory contents while mixing them in the reference order.

  The input pattern is registered in RB and RF by a tree structure by linking each item in the form of Key to be referred to. Further, the end of the input pattern item is indicated by the end flag. Therefore, since the number of input pattern items can be made variable, the number of input pattern items can be flexibly set in accordance with the state of the command section to be registered in the reuse table. In addition, since the number of items in the input pattern is not fixed, the unused area does not occupy the memory area unnecessarily, and the use efficiency of the memory area can be improved.

  In addition, since the input pattern is registered by the tree structure, it is possible to share one line with a plurality of input patterns for portions where the contents of the items overlap. Therefore, the utilization efficiency of the memory area can be further improved.

  In the case of the above configuration, the memory constituting the RF and RB has a vertically long structure. For example, when the memory capacity is 2 Mbytes, the horizontal is 8 words and the vertical is 65536 lines.

(Second configuration example for registering an input pattern as a tree structure)
In the above example, the items UP, Alt., And DN are not used in the RF shown in FIG. That is, in the above example, it is not necessary to provide these items in the RF. On the other hand, a second configuration example for further speeding up the associative search operation by using items of UP, Alt., And DN and its operation will be described below.

  First, in FIG. 4B, only the program counter (PC) and the register contents (Reg.) Are compared, and if they match, the section can be reused without comparing the main memory values. The state when it can be determined that it exists is shown. In this state, first, PC and Reg. Are registered in Value in the RB “01” line. In the RF “01” line, the termination flag is “E” and the comparison required flag is “0”. The main storage address to be compared is “A1”, and the UP indicating the parent node number is “FF”. In the RB “03” line, the Key is “01” without the Value value, and in the RF “03” line, the termination flag is “E”, the comparison required flag is “0”, The main storage address to be compared is “A2”, and the UP indicating the parent node number is “FF”. Thereafter, similarly, the “05” line and the “07” line in the RB and RF are registered, the termination flag is “E”, and the comparison required flag is “0”, respectively.

  In this state, when execution of a certain instruction section is detected, PC and Reg. Are input to the RB, and the line “01” in the RB is selected as a match line. Then, “01” which is the address in the RB of the line selected as the match line is transmitted to the RF as an encoding result, and the line in the RF corresponding to the key 01 is referred to. Since the end flag is “E” in the RF line corresponding to the key 01, it can be seen that there is no main memory address to be compared next. Further, since the comparison required flag is “0”, it can be seen that it is not necessary to compare the main memory address A1.

  Therefore, as shown in the tree structure of FIG. 4A, when the coincidence of PC and Reg. Is confirmed in S1, comparison is performed at main memory addresses A1, A2, and A3 as in the node indicated by Tr1. Instead, the corresponding output value is output.

  When RF and RB are in this state, it is assumed that writing has been performed on the main memory address A2. In this case, it is not necessary to perform a coincidence comparison of the main memory address A2 at the time of registering the input pattern in the RF and RB, but a coincidence comparison of the main memory address A2 is performed by changing the main memory address A2. There will be a need. Therefore, in this case, RF and RB are changed as shown in FIG.

First, using A2 which is the main memory address whose contents are changed as a key, Adr.
A search is performed on the columns. As a result, the line “03” in RF is selected. Then, in the selected line “03”, the comparison required flag is set to “1” and the end flag “E” is deleted.

  Next, by referring to the UP in the “03” line, the “01” line as the parent node is recognized. In the line “01”, A2 which is the main storage address whose contents are changed is written to Alt. Indicating the main storage address to be compared with priority over the main storage address to be compared next. The termination flag “E” is deleted. Further, in the “01” line, “03” is written in the DN indicating the key required for the priority comparison.

  The associative search operation when RF and RB are rewritten as described above is as follows. When a certain instruction section is detected, first, PC and Reg. Are input to RB. Then, in the RB, these values input by the associative search are compared with the instruction section start address and register value registered in the Value column of the RB, and the “01” line in the RB is used as a match line. Selected.

  Next, “01”, which is the address in the RB of the line selected as the match line, is transmitted to the RF as an encoding result, and the line in the RF corresponding to the key 01 is referred to. In the RF line corresponding to the key 01, the comparison required flag is “0”, and the main storage address to be compared is A1. That is, it can be seen that it is not necessary to perform a coincidence comparison with respect to the main memory address A1.

  Also, the main memory address A2 is registered in Alt. Indicating the main memory address to be compared with priority over the main memory address to be compared next, and DN indicating the key required for the priority comparison It is confirmed that “03” is registered in. In this case, the value of the main memory address A2 in the main memory 3 is read through the Cache 7A, and in RB, Value is the value read from the main memory 3, and Key is indicated in DN. A line with “03” is searched.

  In the example shown in FIG. 5B, there are two lines “04” and “05” with Key “03”, but the value read from the main memory 3 is “00”. , “05” is selected as a match line, and key 05 is transmitted to RF as an encoding result. In the line in RF corresponding to the key 05, since the termination flag is “E”, it is determined that all the input patterns match, and the corresponding command section is determined to be reusable. Then, a “Select Output” signal is output from the line in which the termination flag E is detected, and output values corresponding to the lines stored in RO1 and RO2 are output to the register 6A and the main memory 3.

  According to the second configuration example for performing the associative search operation as described above, in RF, Alt. Indicating the main memory address to be compared with priority over the main memory address to be compared next, and Since a DN indicating a key necessary for the comparison is provided, the contents of the main memory address A1 and the search by the key 01 are skipped, and the contents of the main memory address A2 and the key 03 can be searched. Accordingly, the processing steps of the search operation can be reduced, and the processing speed can be increased.

(Example of output value storage means configuration)
In the above description, the input pattern of the instruction section is registered in RF and RB, and the associative search operation is performed. However, in the following, the output value output as reuse is stored after the input pattern match is confirmed. A configuration example of the means for performing will be described. As described above with reference to FIG. 1, the instruction interval storage unit 2 stores an output value for storing an output value to be output to the main memory and / or the register when it is determined that reuse is possible. RO1 and RO2 are provided as storage means.

  The output value can be obtained by referring to storage means such as a RAM for storing the output value based on the address output from the RF and RB. However, like the input pattern, it is preferable that the number of output value items be variable for the output pattern, and thus a device for storing the output value needs to be devised.

  The input pattern is registered in a tree structure in RF and RB. Then, it is determined that reuse is possible in the line that is the end of the tree structure, that is, the line in which the end flag E is registered. Therefore, by registering a pointer in the output value storage means for storing the output value to be output in each line in which the termination flag E is registered, it is possible to perform an output operation at the time of reuse. .

  However, when the storage position in the output value storage unit is specified based on the pointer storing the output value when it is confirmed that all the input patterns match, the storage position is specified based on the pointer. Conversion processing is required, which causes a reduction in processing speed.

  Therefore, in this configuration example, two storage units, RO1 and RO2, are provided as output value storage units. RO1 stores an output value and an address to be output in a one-to-one correspondence with each line of RF. That is, when it is determined that the RF line in which the termination flag E is registered can be reused, the RO1 line corresponding to the line is selected and the output value is output.

  However, in this way, when the output value storage means stores the output value and the address to be output in one-to-one correspondence with each line of the RF, the RF in which the termination flag E is not registered in the RF A memory area is secured in RO1 for these lines. Further, since the output value is stored in RO1 corresponding to all the lines of the RF in which the termination flag E is registered, there is a redundancy that the same contents are stored in a plurality of locations. Become. Therefore, RO1 is excellent in terms of processing at high speed, but it is not good in terms of memory utilization efficiency.

  In order to solve this problem, the number of items that can be registered in RO1, that is, the number of pairs of output values and output addresses is set to be small (two in the example of FIG. 1), and output that cannot be registered in RO1. A set of a value and an output address is registered in RO2 having a configuration in which a storage area is designated using a pointer.

  In RO2, since the storage area is indicated by the pointer, there is almost no unused memory area. Also, when registering multiple sets of output values and output addresses, you can connect them sequentially using pointers, so the number of sets of output values and output addresses that can be registered can be made variable. It is. Furthermore, since a pointer indicating the same storage position in RO2 can be designated from a plurality of lines in RO1, storage information in RO2 can also be shared by a plurality of lines in RO1. Therefore, in RO2, the redundancy of stored contents can be reduced.

  As described above, by providing two output value storage units, RO1 and RO2, when the number of output value items is small, the processing speed can be increased by using only RO1, and the number of output value items is large. The case is dealt with by using RO2, which can change the number of items. Therefore, according to the above configuration, it is possible to realize high-speed processing and improvement in memory utilization efficiency.

(Registration processing for the command section storage unit)
In the above, the operation in the case of reusing when executing a certain instruction section has been described. In the following, an operation when registering input / output in an instruction section in RF, RB, RO1, and RO2 when it is determined that reuse cannot be performed when executing a certain instruction section will be described.

  First, when execution of a certain instruction section is detected, the values of PC and Reg. Are input to RB. Then, in the RB, these values inputted by the associative search are compared with the instruction section start address and the register value registered in the Value column of the RB. Here, if it is determined that there is no RB Value column that matches the input value, it is determined that the instruction section cannot be reused, and the arithmetic unit 5A performs arithmetic processing. Is called. Then, the register input value, the main memory input value, the main memory output value, and the register output value that are used until the calculation process of the corresponding instruction section is completed are registered in RB, RF, RO1, and RO2 as necessary. . Here, when registering in RB and RF, registration is performed so that each item corresponds to one line so as to have the tree structure as described above. Then, in the line where the last item of the input pattern to be registered is registered, the RF termination flag is set to “E”, and the registration of the input pattern is completed.

  On the other hand, if an item that matches the entered PC and Reg. Values is registered in the RB Value column, the next item to be compared is compared in the same manner as the associative search operation described above. A match comparison is performed. In this way, the comparison between the input pattern registered in RB and RF and the input pattern in the corresponding instruction section is continued, and a new node is added when an unmatched item occurs. Then, registration is performed in the RB and RF for the mismatched items. Then, in the line where the last item of the input pattern to be registered is registered, the RF termination flag is set to “E”, and the registration of the input pattern is completed.

  When the registration of the input pattern is completed, the output value and the output address are registered in the line in RO1 corresponding to the line in RF whose end flag is “E”. When items to be registered as output values cannot be registered in RO1, registration is performed for RO2 using a pointer. Thus, the instruction section registration process is completed.

(Generation of I / O set during instruction section execution)
When a certain instruction section is executed, an execution result is registered in the instruction section storage unit 2, and this execution result is stored in a register and / or main memory (hereinafter simply referred to as the execution of the instruction section). This is equivalent to a set of inputs and outputs made to a register / memory). Hereinafter, how to generate an input / output set to be registered in the instruction section storage unit 2 will be described.

  In the case of the first and second configuration examples in which the above input pattern is registered as a tree structure, the input / output set is generated by RW4A and 4B, and based on the generated input / output set, to RB, RF, RO1, and RO2 The registration process as described above is performed. The RWs 4A and 4B monitor the reading from the register / memory and / or the writing to the register / memory performed when a certain instruction section is executed, and generate an input / output set based on this. A method for generating an input / output set by the RWs 4A and 4B will be described below. In the following description, RW4A is described, but the same applies to RW4B.

(First configuration example of RW)
FIG. 12 is a diagram showing an outline of the memory configuration of the RW 4A. As shown in the figure, the RW 4A has a PC for storing the PC value of the instruction section, an RWI for storing the input address and the input value, and an RWO memory for storing the output address and the output value. The input / output set when a certain instruction section is executed is stored in the memory of this RW 4A, and then registered in the instruction section storage unit 2.

  First, when execution of a certain instruction section is started, the PC value is stored in the PC in the RW 4A. Thereafter, when the execution of the instruction section is sequentially performed, reading from the register / memory and / or writing to the register / memory are sequentially performed.

  When reading from the register / memory is performed at the time of executing the instruction section, the following processing is performed by the RW 4A.

  (AR1) It is searched whether or not the address of the register / memory from which reading has been performed is registered in the RWO. When registered in the RWO, since the value already registered in the input / output set as the output value has been read out, it is not necessary to register as the input value. That is, the process ends without registering the address in the RWI.

  (AR2) If the address of the register / memory from which data has been read is not registered in the RWO, it is searched whether or not the address is registered in the RWI. When registered in the RWI, since the value already registered in the input / output set as the input value has been read out, it is not necessary to register as an input value. That is, the process ends without registering the address in the RWI.

  (AR3) When the address of the register / memory from which data has been read is not registered in either RWO or RWI, the address and value are registered in the RWI as an input address and an input value.

  Further, when writing to the register / memory is performed at the time of executing the instruction section, the following processing is performed by the RW 4A.

  (AW1) It is searched whether or not the address of the register / memory in which writing has been performed is registered in the RWO. When registered in the RWO, since the value already registered in the input / output set as the output value has been rewritten, the output value corresponding to the registered output address is written. Update to the specified value and exit.

  (AW2) If the address of the register / memory to which writing has been performed is not registered in RWO, the address and value are registered in RWO as an output address and output value.

  By performing the above processing until the end of the instruction section, an input / output set of the instruction section is generated by the RW 4A. The generated input / output set is registered in the instruction section storage unit 2 by the registration process as described above.

  Here, as an example of the instruction interval, an example when the instruction interval shown in FIG. 11 is executed will be described. In the figure, PC indicates a PC value when the instruction section is started. This PC value is stored in the PC of RW4A.

  Thereafter, in the first line, the value (00001000) stored in the address R1 in the register is read, and the result obtained by performing an operation of adding 100 to the read value is stored in the main memory address (address A1). Command) is read out. At this time, since the address R1 is not registered in either RWO or RWI, the address R1 and the value (00001000) are registered in the RWI. In addition, the value (---- FF--) of the address A1 is read and the register address reg. The instruction to store in is performed. At this time, since the address A1 is not registered in either RWO or RWI, the address A1 and the value (---- FF--) are registered in the RWI.

  At this time, the address reg. Is not registered in the RWO, the address reg. And the value (---- FF--) are registered in the RWO.

  Next, in the second line, the address reg. A value is read from the main memory and a write process to the main memory is performed, and a value (---- FF--) is written to address B1. At this point, the address reg. Is registered in the RWO, it is not registered in the RWO. Since the address B1 is not registered in the RWO, the address B1 and the value (---- FF--) are registered in the RWO.

  Next, in the third row, the value (00001000) stored at the address R1 in the register is read, and the main memory address (address A2) as a result of the operation of adding 200 to the read value is performed. Instruction) is read out. At this time, since the address R1 is already registered in the RWI, registration in the RWI is not performed. Also, the value of address A2 (--01 ----) is read out and the register address reg. The instruction to store in is performed. At this time, since the address A2 is not registered in either the RWO or RWI, the address A2 and the value (--01 ----) are registered in the RWI.

  At this time, the address reg. Is registered in the RWO, and the address reg. The value of is updated to the value (--01 ----).

  Next, in the fourth line, the address reg. The value is read out from the memory and written into the main memory, and the value (--01 ----) is written into the address B2. At this point, the address reg. Is registered in the RWO, it is not registered in the RWO. Further, since the address B2 is not registered in the RWO, the address B2 and the value (--01 ----) are registered in the RWO.

  Next, in the fifth line, the value (5678 ----) of the address A3 is read and the register address reg. The instruction to store in is performed. At this time, since the address A3 is not registered in either the RWO or the RWI, the address A3 and the value (5678 ----) are registered in the RWI.

  At this time, the address reg. Is registered in the RWO, and the address reg. The value of is updated to the value (5678 ----).

  Finally, in the sixth line, the address reg. The value is read out from the memory and written into the main memory, and the value (5678 ----) is written into the address B3. At this point, the address reg. Is registered in the RWO, it is not registered in the RWO. Further, since the address B3 is not registered in the RWO, the address B3 and the value (5678 ----) are registered in the RWO. Through the above processing, the RW4A input / output set shown in FIG. 12 is generated.

  The input / output set generated as described above is registered in the instruction section storage unit 2 as a tree structure as shown in FIG. In this tree structure, the registered input pattern is held in the instruction section storage unit 2 as one path from the root node to the leaf. Thereafter, before executing the instruction section, in order to determine whether the input pattern of the instruction section is the same as the registered input pattern, as shown in FIG. With reference to the recorded address, the node that matches the obtained value is repeatedly selected using the associative search mechanism.

(Problem of tree structure associative search)
In the case of the above tree structure, input patterns are sequentially read one by one and an associative search is performed. After a matching node is found, the next node is selected. That is, the search for the next node is started after the search for the preceding node is completely completed.

  Here, the associative search device configured by CAM / RAM generally has a characteristic of long latency and high throughput. That is, a general associative search apparatus has a relatively long period from when one search input is made to when it is output, but it can process and output a plurality of search inputs simultaneously. It has characteristics. On the other hand, as described above, when the search for the next node is started after the search for the preceding node is completely completed, the high-throughput capability of the associative search device is used. Thus, the capability of the associative search device cannot be fully exhibited (Problem 1).

  In the case of the tree structure described above, the input pattern of the instruction section is realized as a single path in the order of reference, and the output cannot be reused unless the entire input pattern matches. Here, the following example is assumed. First, among the input patterns when executing a certain instruction section, the first half is pattern A1, the second half is pattern A2, the output corresponding to pattern A1 is X1, and the output corresponding to pattern A2 is X2. To do. Of the input patterns when executing another instruction section, the first half is pattern B1, the second half is pattern B2, the output corresponding to pattern B1 is Y1, and the output corresponding to pattern B2 is Y2. Suppose. After that, among the input patterns when trying to execute a certain instruction section, when the first half is the pattern A1 and the second half is the pattern B2, each of the first half and the second half of the input pattern can be reused. Since the same pattern does not appear in the past as the entire input pattern, it cannot be reused in practice (Problem 2).

(Second configuration example of RW)
The above two problems are caused by expressing the input pattern of the instruction section at a certain call time by a single path from the root node to the leaf. In order to solve these problems, associative search is performed by dividing the input pattern into groups, constructing a tree structure that holds past input patterns for each group, and enabling simultaneous search of multiple tree structures. It is necessary to be able to use the device effectively. For example, the tree structure as shown in FIG. 13 is divided into a plurality of tree structures as shown in FIG. 14, and reuse is performed independently for each input group corresponding to the path from the root node to the leaf. do it.

  As described above, in order to realize the division of the tree structure, it is necessary that there is no data dependency between the input groups. That is, when an input pattern is divided into group A and group B, when the input of group A depends on the input of group B, or when the input of group B depends on the input of group A, Even if the groups are divided, the possibility that each group can be reused independently is extremely low.

  In order to divide into groups having no data dependency, it is necessary to analyze the data dependency when generating an input pattern. That is, the RW 4A may analyze the data dependency and then divide the input pattern into groups having no data dependency to generate an input / output set.

  FIG. 10 shows a schematic configuration of the RW 4A as a second configuration example for realizing the above. As shown in the figure, the RW 4A includes a PC for storing the PC value of the instruction section, an RWI for storing the input address and the input value, an RWO for storing the output address and the output value, a dependency storage unit M, and an inter-row AND comparison. Part (input / output group setting means) MR and group ID storage part ID.

  The dependency relationship storage unit M is a two-dimensional array memory, and 0 or 1 is stored in each memory element. In the dependency relationship storage unit M, each column corresponds to each input address and input value registered in the RWI, and each row corresponds to each output address and output value registered in the RWO. The dependency relationship storage unit M indicates which input address and input value each output address and output value originate from.

  The inter-row logical product comparison unit MR performs a logical product operation between the respective row components stored in the dependency relationship storage unit M, an output pattern including one or more output addresses and output values, and one or more input addresses and input values. Is an arithmetic unit for setting an input / output group including input patterns including. Details of the logical product operation by the inter-row logical product comparison unit MR will be described later.

  The group ID storage unit ID is a memory that stores a group ID given to an input address and an input value corresponding to each column in the dependency storage unit M based on a logical product operation result by the inter-row logical product comparison unit MR. It is. Details of the group ID will be described later.

  When execution of a certain instruction section is started, first, all initial values of the memory elements in the dependency relationship storage unit M are set to 0. Then, the PC value of the instruction section is stored in the PC in RW4A. Thereafter, when the execution of the instruction section is sequentially performed, reading from the register / memory and / or writing to the register / memory are sequentially performed.

  When reading from the register / memory is performed at the time of executing the instruction section, the following processing is performed by the RW 4A.

  (BR1) It is searched whether or not the address of the register / memory from which data has been read is registered in RWO. When registered in the RWO, since the value already registered in the input / output set as the output value has been read out, it is not necessary to register as the input value. That is, the process ends without registering the address in the RWI.

  At this time, the value of each memory element of the row component of the dependency storage unit M corresponding to the address already registered in the RWO is extracted and stored as a provisional matrix A (x) as a one-dimensional matrix of only the row component. The Here, x is a number given in the order in which the provisional matrix A is generated. The provisional matrix A (x) is initialized at the time when a writing process described later is completed. The provisional matrix A (x) is not shown in FIG. 10, but is stored in a provisional matrix storage memory that can store a plurality of provisional matrices A (x).

  (BR2) When the address of the register / memory from which reading has been performed is not registered in the RWO, it is searched whether or not the address is registered in the RWI. When registered in the RWI, since the value already registered in the input / output set as the input value has been read out, it is not necessary to register as an input value. That is, the process ends without registering the address in the RWI.

  At this time, a temporary matrix A (x) is stored in which the memory elements corresponding to the columns of the dependency storage unit M corresponding to the addresses already registered in the RWI are set to 1 and the other memory elements are set to 0.

  (BR3) When the address of the register / memory from which reading has been performed is not registered in either RWO or RWI, the address and value are registered in the RWI as an input address and an input value.

  At this time, a temporary matrix A (x) in which the memory element corresponding to the column of the dependency storage unit M corresponding to the newly added input address and input value (entry) is set to 1 and the other memory elements are set to 0 is stored. Is done.

  Further, when writing to the register / memory is performed at the time of executing the instruction section, the following processing is performed by the RW 4A.

  (BW1) It is searched whether or not the address of the register / memory to which writing has been performed is registered in the RWO. When registered in the RWO, since the value already registered in the input / output set as the output value has been rewritten, the output value corresponding to the registered output address is written. Update to the specified value and exit.

  At this time, the row component of the dependency relationship storage unit M corresponding to the address already registered in the RWO is replaced with the logical sum of all the provisional matrices A (x) stored at that time. As a result, the pattern of the input address / value that is the origin of the output for the output address / value already registered in the RWO is indicated by the row component of the dependency storage unit M corresponding to the output address. When the writing process is completed and the replacement of the provisional matrix A (x) with the logical sum is completed, the provisional matrix A (x) is all initialized.

  (BW2) If the address of the register / memory to which data has been written is not registered in the RWO, the address and value are registered in the RWO as the output address and output value.

  At this time, the row component of the dependency relationship storage unit M corresponding to the newly added output address and output value (entry) is replaced with the logical sum of all the provisional matrices A (x) stored at that time. As a result, the pattern of the input address / value that is the origin of the output for the output address / value newly registered in the RWO is indicated by the row component of the dependency storage unit M corresponding to the output address. When the writing process is completed and the replacement of the provisional matrix A (x) with the logical sum is completed, the provisional matrix A (x) is all initialized.

  Here, as an example of the instruction interval, an example when the instruction interval shown in FIG. 11 is executed will be described. In the figure, PC indicates a PC value when the instruction section is started. This PC value is stored in the PC of RW4A.

  Thereafter, in the first line, the value (00001000) stored in the address R1 in the register is read, and the result obtained by performing an operation of adding 100 to the read value is stored in the main memory address (address A1). Command) is read out. At this time, since the address R1 is not registered in either RWO or RWI, the address R1 and the value (00001000) are registered in the RWI.

  At this time, the temporary matrix A (1) [1000] is stored in which the memory element corresponding to the column of the dependency storage unit M corresponding to the address R1 is set to 1, and the other memory elements are set to 0.

  In addition, the value (---- FF--) of the address A1 is read and the register address reg. The instruction to store in is performed. At this time, since the address A1 is not registered in either RWO or RWI, the address A1 and the value (---- FF--) are registered in the RWI.

  At this time, a temporary matrix A (2) [0100] is stored in which the memory element corresponding to the column of the dependency storage unit M corresponding to the address A1 is set to 1, and the other memory elements are set to 0.

  At this time, the address reg. Is not registered in the RWO, the address reg. And the value (---- FF--) are registered in the RWO. At this time, the newly added address reg. Is replaced with the logical sum [1100] of all the provisional matrices A (1) to A (2) stored at that time. Thereafter, the provisional matrix A (x) is initialized.

  Next, in the second line, the address reg. A value is read from the main memory and a write process to the main memory is performed, and a value (---- FF--) is written to address B1. At this point, the address reg. Is registered in the RWO, it is not registered in the RWO. At this time, the address reg. Are extracted, and the provisional matrix A (1) [1100] is stored.

  Since the address B1 is not registered in the RWO, the address B1 and the value (---- FF--) are registered in the RWO.

  At this time, the row component of the dependency relationship storage unit M corresponding to the newly added output address is replaced with the logical sum [1100] of all the provisional matrices A (1) stored at that time. Thereafter, the provisional matrix A (x) is initialized.

  Next, in the third row, the value (00001000) stored at the address R1 in the register is read, and the main memory address (address A2) as a result of the operation of adding 200 to the read value is performed. Instruction) is read out. At this time, since the address R1 is already registered in the RWI, registration in the RWI is not performed.

  At this time, the temporary matrix A (1) [1000] is stored in which the memory element corresponding to the column of the dependency storage unit M corresponding to the address R1 is set to 1, and the other memory elements are set to 0.

  Also, the value of address A2 (--01 ----) is read out and the register address reg. The instruction to store in is performed. At this time, since the address A2 is not registered in either the RWO or RWI, the address A2 and the value (--01 ----) are registered in the RWI.

  At this time, a temporary matrix A (2) [0010] is stored in which the memory element corresponding to the column of the dependency relationship storage unit M corresponding to the address A2 is set to 1, and the other memory elements are set to 0.

  At this time, the address reg. Is registered in the RWO, and the address reg. The value of is updated to the value (--01 ----). At this time, the updated address reg. Is replaced with the logical sum [1010] of all the provisional matrices A (1) to A (2) stored at that time. Thereafter, the provisional matrix A (x) is initialized.

  Next, in the fourth line, the address reg. The value is read out from the memory and written into the main memory, and the value (--01 ----) is written into the address B2. At this point, the address reg. Is registered in the RWO, it is not registered in the RWO. At this time, the address reg. Are extracted, and the provisional matrix A (1) [1010] is stored.

  Further, since the address B2 is not registered in the RWO, the address B2 and the value (--01 ----) are registered in the RWO.

  At this time, the row component of the dependency relationship storage unit M corresponding to the newly added output address is replaced with the logical sum [1010] of all the provisional matrices A (1) stored at that time. Thereafter, the provisional matrix A (x) is initialized.

  Next, in the fifth line, the value (5678 ----) of the address A3 is read and the register address reg. The instruction to store in is performed. At this time, since the address A3 is not registered in either the RWO or the RWI, the address A3 and the value (5678 ----) are registered in the RWI.

  At this time, a temporary matrix A (1) [0001] is stored in which the memory element corresponding to the column of the dependency relationship storage unit M corresponding to the address A3 is set to 1, and the other memory elements are set to 0.

  At this time, the address reg. Is registered in the RWO, and the address reg. The value of is updated to the value (5678 ----). At this time, the updated address reg. Is replaced with the logical sum [0001] of all provisional matrices A (1) stored at that time. Thereafter, the provisional matrix A (x) is initialized.

  Finally, in the sixth line, the address reg. The value is read out from the memory and written into the main memory, and the value (5678 ----) is written into the address B3. At this point, the address reg. Is registered in the RWO, it is not registered in the RWO. At this time, the address reg. Is extracted, and the provisional matrix A (1) [0001] is stored.

  Further, since the address B3 is not registered in the RWO, the address B3 and the value (5678 ----) are registered in the RWO.

  At this time, the row component of the dependency relationship storage unit M corresponding to the newly added output address is replaced with the logical sum [0001] of all the provisional matrices A (1) stored at that time. Thereafter, the provisional matrix A (x) is initialized. Through the above processing, the RW4A input / output set shown in FIG. 10 is generated.

  By generating the dependency relationship storage unit M as described above, the following information is obtained when the execution of the instruction section is completed.

  The row component of the (Rs1) dependency relationship storage unit M indicates by 1 the input address / value that is the origin of the corresponding output address / value.

  (Rs2) An input address / value pair in which 1 is indicated in a certain row component Ma forms one input group, and an output address / value that can be reused when the input groups match is the row component Ma Is an output address / value corresponding to.

  (Rs3) When the logical product of “inversion of a certain row component Ma” and “some row component Mb” is all 0, the pattern of 1 in Ma includes the pattern of 1 in Mb. That is, the input address / value pairs belonging to Ma form one input group, and when the input groups match, the output address / value that can be reused is the output address / value corresponding to Ma, and An output address / value corresponding to Mb.

  (Rs4) When the logical product of “a row component Ma” and “a row component Mb” is all 0, the input address / value belonging to Ma and the input address / value belonging to Mb are independent of each other .

  Based on the above information, the RW 4A divides the input / output set into a plurality of input / output groups. First, as processing related to the above (Rs3), in the dependency storage unit M, a set of row components in which the logical product of “inversion of a certain row component Ma” and “some row component Mb” is all 0 Extracted by the logical product comparison unit MR. Of the extracted row component pairs, the row component that contains the most input address / value pairs, that is, the row component that contains all the input address / value pairs in other row components is selected as the upper row component. . Then, among the extracted row components, the lower row components other than the upper row component are deleted. This process can eliminate redundant input / output groups.

  Next, in a state where the lower row component is deleted, as processing related to the above (Rs4), a set of row components in which the logical product of “a row component Ma” and “a row component Mb” is all 0 Are extracted by the inter-row logical product comparison unit MR. Then, among the extracted row component sets, row components whose logical products are all 0 with respect to any other row components are further extracted. The row components extracted here have no dependency with respect to any other row components, so this is set as an independent row component, and the others are set as non-independent row components.

  The independent row component is set as one input / output group by extracting a corresponding input address / value pair and output address / value pair, respectively. On the other hand, the non-independent row component is set as an input / output group by one of the following two processes.

  The first processing is processing for setting the sum of input address / value pairs and output address / value pairs included in all non-independent row components as one input / output group. The second process is a process of setting each non-independent row component as an input / output group as it is. When the first process is performed, the number of input / output groups is not increased more than necessary, so that the memory usage capacity in the instruction interval storage unit 2 can be reduced. On the other hand, when the second processing is performed, there is a problem that the number of input / output groups is relatively large and the memory usage capacity in the instruction interval storage unit 2 is relatively large. Since the number of tree structures to be increased can be increased, the high-throughput capability of the associative search device can be used.

  When the input / output groups are set as described above, based on this, the inter-row logical product comparison unit MR assigns a group ID to each input / output group, and each of the input addresses / values registered in the RWI. On the other hand, information indicating which group ID is included is stored in the group ID storage unit ID. Thereby, it becomes possible to identify the input pattern in each input / output group by looking at the contents of the group ID storage unit ID.

  As described above, the RW 4A generates one or more input / output groups and registers the generated input / output groups as execution results in the instruction interval storage unit 2. Through such processing, the execution result of one instruction section is registered in the instruction section storage unit 2 as one or more input / output groups. Therefore, when executing a certain instruction section by reuse, it is possible to increase the probability that reuse can be performed even if only part of the input pattern of the previously executed instruction section matches. . In addition, since the probability that there are a plurality of tree structures to be searched at the same time can be increased, the high-throughput capability of the associative search device can be used, and an improvement in processing speed can be expected.

  In the present embodiment, the input / output group generated by the RW 4A is registered in the instruction section storage unit 2 for registering the input pattern as a tree structure. However, the present invention is not limited to this. . That is, the RW4A according to the present embodiment is applied to any instruction section storage unit that can register the input / output group generated by the RW4A in a form in which the execution result of the instruction section can be reused. It is possible.

(Details of register values)
Register input / output values include arguments, return values (Args.), And registers and condition codes (Regs., CC) other than arguments and return values. In the present embodiment, among the SPARC architecture registers, general-purpose registers% g0-7,% o0-7,% l0-7,% i0-7, floating point register% f0-31, condition code register ICC, floating point condition code The register FCC is used (details will be described later). Of these, the leaf function input is general-purpose register% o0-5, the output is general-purpose register% o0-1 or% f0-1, the non-leaf function input is general-purpose register% i0-5, and the output is general-purpose register% i0 -1 or% f0-1, and the input is registered in arg [0-5] and the output is registered in rti [0-1] or% rtf [0-1]. According to the SPARC-ABI regulations, registers other than these are not input / output of functions, and therefore, for functions, Args. Is registered in RB and RO1 / RO2 as register input / output values.

  On the other hand, according to the SPARC-ABI rules, the type of register used cannot be specified for loop input / output. Therefore, in order to specify loop input / output, all types of registers must be registered in the RB. There is. Therefore, for the loop, register input / output values corresponding to Regs., CC,% g0-7,% o0-7,% l0-7,% i0-7,% f0-31, ICC, FCC are registered. Will be.

(Multiple reuse)
When the reuse mechanism as described above is used at one level, in the example shown in FIG. 10A, the function B as the leaf function, the loop C inside the function B, etc. are reused. It becomes possible. On the other hand, multiple reuse is a mechanism for performing registration so that all instruction sections including functions and loops included in the function can be reused by executing a function once. For example, in the above example, according to multiple reuse, all the instruction sections of A, B, and C that are nested can be reused by executing the function A once. The function expansion required for realizing multiple reuse will be described below.

  FIG. 6 shows a conceptual structure of the function A and the function D as an example. In the example shown in the figure, a loop B exists inside the function A, a loop C exists inside the loop B, and the function D is called in the loop C. A loop E exists inside the function D, and a loop F exists inside the loop E.

  7, in the nested structure of functions A and D and loops B, C, E, and F shown in FIG. 6, the register input / output (thick frame cell region) of the inner structure becomes the register input / output of the outer structure. The influence range (arrow) is shown. For example,% i0 to 5 referred to as an input in the loop F is also an input to the loop E and the function D, and further, an input to the loop C and the loop B that called the function D (but replaced with% o0 to 5). It is also. On the other hand, for function A,% o0 to 5 correspond to local variables, so% i0 to 5 (% o0 to 5) are not register inputs for function A. That is, the influence range of% i0 to 5 (% o0 to 5) is up to loop B. From another point of view, if% i0-5 is referenced inside function D,% o0-5 is input to loop B even if loop B does not directly reference% o0-5. Must be registered as a value. The same applies to% i0-1 output in the loop F.

  Since the floating point register is not included in the register window, the output% f0 to 1 is output of all layers including the function A. On the other hand, other register inputs and outputs have no effect beyond functions. That is, input / output in the loop F, that is,% i6-7,% g, l, o,% f0-31,% icc,% fcc as register inputs, and% I2-7,% g as register outputs , l, o,% f2 to 31,% icc,% fcc range up to loop E. For the input / output to / from the main memory, the influence range can be specified by applying the above-described method of comparison with% sp (SP) immediately before the function call to all nested hierarchies.

  Here, according to the configuration of the RW 4A, the RW 4B, and the instruction section storage unit 2 as described above, input / output of a plurality of instruction sections can be individually recorded, so that multiple reuse can be realized. It becomes possible.

(Parallel pre-execution)
The multiple reuse of functions and loops described above has no effect when the interval at which the same parameter appears is long or when the parameter continues to change monotonously. That is, when the same parameter appears longer than the lifetime of the RB entry, even when a certain function or loop is registered in the RB, the same parameter appears next for the registered function or loop. The function or loop has already disappeared from the RB entry and cannot be reused. In addition, when the parameter continues to change monotonously, even if the corresponding function or loop is registered in the RB, the parameter cannot be reused because the parameter is different.

  On the other hand, by providing a plurality of SSP1Bs as processors that enable the RB entry by pre-execution of the instruction section separately from the MSP1A as a processor that performs multiple reuse, it is possible to further increase the speed.

  The hardware configuration for performing the parallel pre-execution mechanism is as shown in FIG. As shown in the figure, the RWs 4A and 4B, the arithmetic units 5A and 5B, the registers 6A and 6B, and the caches 7A and 7B are provided independently for each processor, while the instruction section storage unit 2 and the main memory 3 is shared by all processors. In the figure, the broken lines indicate paths through which MSP 1A and SSP 1B register input / output to / from the instruction section storage unit 2.

  Here, there are two problems in realizing parallel pre-execution: (1) how to maintain main memory consistency, and (2) how to predict input. Below, the solution method with respect to these subjects is demonstrated.

(Solutions to main memory consistency issues)
First, the above problem (1) how to maintain main memory consistency will be described. In particular, when an instruction interval is executed based on a predicted input parameter, the value to be written to the main memory is different between MSP1A and SSP1B. In order to solve this, as shown in FIG. 2, the SSP 1B is provided for the instruction section storage unit 2 for the main memory reference to be registered in the RB and for each SSP 1B for other local references. Local 7B is used as a local memory, and writing to Cache 7B and main memory 3 is unnecessary. When the MSP 1A writes to the main memory 3, the corresponding SSP 1B cache line is invalidated.

  Specifically, the address and value are registered in the RB in the same manner as the MSP 1A with reference to the main memory 3 for the address preceded by the reading among the registration targets in the instruction section storage unit 2. Thereafter, by referring to the instruction section storage unit 2 instead of the main memory 3, it is possible to avoid the occurrence of contradiction due to overwriting from another processor. As for local reference, the fact that reading precedes corresponds to using a variable without initializing it, and the value may be indefinite, so it is not necessary to refer to the main memory 3.

  Note that the capacity of the Local 7B as a local memory is finite, and if the execution cannot be continued, such as when the size of the function frame exceeds the capacity of the Local 7B, the pre-execution is aborted. Further, since the result of the pre-execution is not written to the main memory 3, the next pre-execution cannot be performed using the pre-execution result.

(Input prediction method)
Next, the problem (2) how to predict the input will be described. In advance execution, it is necessary to predict a future input based on the usage history of the instruction section storage unit 2 and pass it to the SSP 1B. For this purpose, a small processor is provided for each input pattern stored in the instruction section storage unit 2, and an input predicted value is obtained independently of the MSP 1A and SSP 1B.

  Specifically, stride prediction is performed based on the last appearing argument (B) and the difference (D) between the two most recently appearing arguments. Note that the execution of the instruction interval based on B + D is considered to have already started by MSP 1A. When there are N SSPs 1B, the input predicted values to be prepared are in the range from B + D × 2 to B + D × (N + 1).

  If the input prediction is performed as described above, it is possible to effectively reuse the input parameter based on the result predicted in advance when the above-described input parameter continues to change monotonously.

  The data processing apparatus according to the present invention can be applied to the SPARC processor as described above. Further, like the SPARC processor, the present invention can be applied to many RISC processors having 32 or more general-purpose registers.

It is a figure which shows schematic structure of the instruction area memory | storage part with which the data processor which concerns on one Embodiment of this invention is provided. It is a block diagram which shows schematic structure of the said data processor. It is a figure which shows the specific example of the associative search operation | movement in the said instruction area memory | storage part. FIG. 5B is a diagram showing another specific example of the associative search operation in the instruction section storage unit, and FIG. 6A is a diagram showing the associative search operation in FIG. is there. FIG. 4B is a diagram showing still another specific example of the associative search operation in the instruction section storage unit, and FIG. 4A is a diagram showing the associative search operation in FIG. It is. It is a figure which shows an example of the state where the function and the loop are nested. It is a figure which shows the influence range from which the register input / output of an inner structure turns into the register input / output of an outer structure in the nested structure of a function. It is a figure which shows schematic structure of RF and RB in a comparative example. It is a figure which shows the example of the search operation in a comparative example. It is a figure which shows schematic structure of RW as a 2nd structural example. It is a figure which shows an example of an instruction area. It is a figure which shows the outline of the memory structure in the 1st structural example of RW. It is a figure which shows the state by which the input / output set produced | generated by the 1st structural example of RW was registered as a tree structure. It is a figure which shows the state by which the input / output set produced | generated by the 2nd structural example of RW was registered as a tree structure. FIG. 4A is a conceptual diagram conceptually showing a structure in which the function A calls the function B, and FIG. 4B shows a memory in the main memory when executing the program structure shown in FIG. It is a figure which shows a map. It is a figure which shows the outline | summary of the argument and frame in a memory map when the function A calls the function B. It is a figure which shows the conventional reuse table for reusing one function.

Explanation of symbols

1A MSP
1B SSP
2 Command section storage (command section storage means)
3 Main memory (main memory means)
4A / 4B RW (input / output generation means)
5A / 5B computing unit (first and second computing means)
6A ・ 6B Register 7A ・ 7B Cache
M dependency storage unit MR inter-row AND unit (input / output group setting means)

Claims (11)

In a data processing apparatus that reads a command section from a main storage means and performs a process of writing a result of arithmetic processing to the main storage means,
First arithmetic means for performing an operation based on an instruction section read from the main storage means, a register used when the first arithmetic means reads and writes to the main storage means, and an instruction by the first arithmetic means Input / output generation means for generating an input / output group composed of an input pattern and an output pattern when an interval is calculated, and an instruction interval storage means for storing the input / output group generated by the input / output generation means ,
When the first calculation means executes an instruction section, if the input pattern of the instruction section matches the input pattern stored in the instruction section storage means, the input section corresponds to the input pattern. Reuse processing for outputting the output pattern stored in the instruction section storage means to the register and / or main storage means,
The input / output generation means is
A dependency storage unit that indicates which input element included in the input pattern originates from each output element included in the output pattern;
Input / output group setting for setting an input / output group including an output pattern including one or more output elements and an input pattern including one or more input elements based on information stored in the dependency storage unit And a data processing apparatus.   When the input / output group setting means includes a set of input elements that are the origins of a certain first output element in a set of input elements that are the origins of other second output elements, 2. The data processing apparatus according to claim 1, wherein an input / output group is set in which a set of input elements that are the origin of the output elements is an input pattern, and the first output element and the second output element are output patterns. .   The input / output group setting means has a common input element between a set of input elements that originate from a certain first output element and a set of input elements that originate from another second output element Otherwise, the first input / output group having the input element set that is the origin of the first output element as the input pattern, the first output element as the output pattern, and the input that is the origin of the second output element 2. The data processing apparatus according to claim 1, wherein a second input / output group is set in which a set of elements is an input pattern and a second output element is an output pattern.   The dependency storage unit includes a two-dimensional array memory in which each output element is a row component and each input element is a column component, and each memory element of the two-dimensional array memory is a row component of the memory element. 2. The data processing apparatus according to claim 1, wherein the corresponding output element holds information indicating whether or not the input element corresponding to the column component of the memory element originates. When the instruction section is operated by the first calculation means, and when reading from the register and / or the main storage means is performed, the input / output generation means is
(1) When the address of the read register and / or main storage means is registered in the dependency storage unit as an output element, a temporary matrix composed of the row components of the dependency storage unit corresponding to the output element Processing to temporarily store,
(2) When the address of the register and / or main storage means from which reading has been performed is not registered in the dependency storage unit as an output element, but is registered in the dependency storage unit as an input element, the input A process of temporarily storing a provisional matrix in which a memory element corresponding to a column of a dependency storage unit corresponding to an element is set to 1 and other memory elements are set to 0, and
(3) If the address of the register and / or main storage means from which the reading has been performed is not registered in the dependency storage unit as either an output element or an input element, the address and value depend on the input element Registering in the relationship storage unit, and temporarily storing a temporary matrix in which the memory element corresponding to the column of the dependency storage unit corresponding to the input element is set to 1 and the other memory elements are set to 0,
When writing to the register and / or main storage means is performed, the input / output generation means is
(4) When the address of the register and / or main storage means to which writing has been performed is registered as an output element, the output value corresponding to the registered output element is updated to the value to which writing has been performed. With
Replace the row component of the dependency storage unit corresponding to the already registered output element with the logical sum of all temporary matrices temporarily stored at that time, and then initialize the temporarily stored temporary matrix Processing and
(5) When the address of the re-register and / or main storage means to which writing has been performed is not registered as an output element, the address and value are registered as an output element in the dependency storage unit and correspond to the output element The row component of the dependency relationship storage unit is replaced with a logical sum of all the temporary matrices temporarily stored at that time, and thereafter, the temporarily stored temporary matrix is initialized. Item 5. A data processing apparatus according to item 4. The input / output group setting means includes an inter-row logical product comparison unit that performs a logical product operation between the row components in the two-dimensional array memory,
The input / output group setting means extracts a set of row components in which the logical product of the inversion of a certain first row component and the certain second row component is all zero in the dependency storage unit, and the extracted row component 5. The data processing apparatus according to claim 4, wherein a row component other than the row component including the most input element set is set as an input / output group out of the set. The input / output group setting means includes an inter-row logical product comparison unit that performs a logical product operation between the row components in the two-dimensional array memory,
5. The input / output group setting means sets the row components whose logical products are all 0 with respect to any other row components in the dependency storage unit, respectively, as input / output groups. Data processing equipment.   2. A data processing apparatus according to claim 1, wherein said command section storage means comprises input pattern storage means for storing a plurality of said input patterns as a tree structure in which items to be matched and compared are regarded as nodes. .   9. The tree structure is realized by the input pattern storage means storing the values of items to be compared and matched in the input pattern in correspondence with the items to be compared next. The data processing apparatus described. The input pattern storage means includes an associative search means and an additional storage means,
The associative search means includes one or more search target lines each having a value storage area for storing a value of an item to be matched and a key storage area for storing a key for identifying the item,
10. The data processing according to claim 9, wherein the additional storage means has a search item designation area for storing an item to be subjected to an associative search next for each corresponding line corresponding to the search target line. apparatus. At least one second computing means;
The second calculation means performs calculation of the instruction section based on a predicted input value that is expected to be input in the future with respect to the instruction section being processed by the first calculation means, and the result is used as the instruction section. The data processing apparatus according to any one of claims 1 to 10, wherein registration is performed with respect to a section storage unit.

Images