JP3895314B2 - Data processing apparatus, data processing program, and recording medium on which data processing program is recorded - Google Patents

Description

  The present invention relates to a data processing apparatus that performs a process of reading an instruction section from a main storage unit and writing a result of an arithmetic process into the main storage unit.

  2. Description of the Related Art Conventionally, research and development relating to a technique for increasing the operation speed of a microprocessor such as a CPU (Central Processing Unit) has been actively conducted. Examples of the speed-up technology include pipeline, superscaler, out-of-order execution, and register renaming.

  Pipeline is a technique that decomposes instruction execution processing into several stages, and flows a plurality of instructions and performs simultaneous processing. Superscaler is a technology that prepares two or more instruction execution circuits and executes a plurality of instructions simultaneously in parallel. Out-of-order execution is a technique for ignoring the description order of instructions and searching for the first executable instruction among several consecutive instructions and performing a preceding process. Register renaming is a technique for increasing the probability that parallel processing is performed by increasing the number of general-purpose registers while maintaining compatibility of instructions in a conventional processor, for example, in a CISC (Complex Instruction Set Computer) type processor. .

  Thus, in order to increase the calculation speed in the microprocessor, it is important to execute instructions in parallel. However, most of the programs include a dependency relationship in which different instructions are executed depending on the result of a certain instruction, in other words, a branch. When such a branch is included, if processing is performed in advance by parallel processing, a situation occurs in which the content of the preceding processing is wasted depending on the result of the branch, and the calculation speed is increased. There is a problem that the effect of.

  Therefore, when there is a branch in the program, many studies have been made on a technique for reducing the probability that the preceding process is wasted by predicting the branch destination and improving the effect of parallel processing, so-called branch prediction.

  However, when speculative preceding processing is performed based on branch prediction, there are generally the following problems. The first problem is that the execution time of the preceding instruction sequence itself cannot be reduced because it is necessary to always verify the correctness of the prediction. As a second problem, since it is necessary to invalidate a series of predecessor operation results based on erroneous prediction, in order to increase the number of instructions that can be speculatively processed at once, a corresponding hardware cost is required. That is the point. As the third problem, the more the dependency between instructions, the more it becomes necessary to carry out speculative predecessor processing, and the verification validity verification process and the invalidation process based on erroneous prediction are extremely complicated. Is that it becomes.

  On the other hand, a technique called value reuse has also been proposed as a speed-up technique different from branch prediction. In this value reuse, input values and output values related to a part of the program are registered in the reuse table, and when the same part is executed again, the input values are registered in the reuse table. Is a technique of outputting a registered output value. The effects of this value reuse include the following. (1) If the input value matches the input value registered in the reuse table, there is no need to verify the execution result. (2) The hardware cost is determined only by the total number of input values and output values, and the length of the instruction sequence that can be omitted is not restricted. (3) The degree of dependency between instructions does not affect the complexity of the reuse mechanism. (4) Redundant load / store instructions can be reduced, and power consumption can be reduced accordingly.

  Non-Patent Document 1, which will be described later, shows a technique for reusing values for functions in a program. In this prior art, a load module is generally used in accordance with ABI (Application Binary Interface), and in particular, SPARC (Scalable Processor ARChitecture) ABI is used. Then, value reuse is realized by specifying input / output of a function in this ABI. That is, it is not necessary to embed a dedicated instruction by a compiler for value reuse, and application to an existing load module is possible.

  Also, by dynamically grasping the multiplex structure of functions, local registers in the function and local variables on the stack are excluded from input / output values in value reuse, thereby improving efficiency. For functions in particular, regardless of the complexity of the function, reuse and pre-execution are possible by registering a maximum of 6 register inputs, a maximum of 4 register outputs, and a minimum main memory value that does not include local variables. ing. This prior art will be described in detail below.

  First, for a single function, we will clarify what is input and what is output, and explain the mechanism required to perform one-level reuse. In a program, functions generally form multiple structures. FIG. 10A shows a structure in which the function A (Function-A) calls the function B (Function-B).

  The global variable (Globals) can be an input / output (Ain / Aout) of the function A and an input / output (Bin / Bout) of the function B. The local variable (Locals-A) of the function A is not an input / output of the function A, but can be an input / output of B through a pointer. An argument (Args) from function A to function B can be an input to function B, and a return value (Ret.Val.) From function B to function A can be an output from function B. It is. The local variable (Locals-B) of the function B is not included in the input / output of the function A and the function B.

  In order to reuse the function B without depending on the context, only the input / output Bin / Bout of the function B must be registered as the input / output when the function B is executed. Here, a memory map in the main memory when executing the program structure shown in FIG. 10A is shown in FIG. In this memory map, only the Locals-B area does not include Bin / Bout. Therefore, in order to identify Bin / Bout, the boundary between Globals and Locals-B and the boundary between Locals-B and Locals-A must be determined, respectively. For the former, the OS (Operating System) generally determines the upper limit of the data size and stack size at the time of execution, and the boundary between Globals and Locals-B is determined based on the boundary (LIMIT) set by the OS. It can be confirmed. For the latter, the boundary between Locals-B and Locals-A can be determined by using the value of the stack pointer (SP in A) immediately before B is called.

Next, a method for identifying whether a given main memory address is a global variable or a local variable of which function will be described. It is assumed that the load module satisfies the following conditions specified in SPARC ABI. Note that% fp means a frame pointer, and% sp means a stack pointer.
(1) Of the areas above% sp,% sp + 0 to 63 are register save areas, and% sp + 68 to 91 are argument save areas, which are not function inputs / outputs.
(2) An implicit argument (Implicit Arg.) For returning a structure is stored in% sp + 64 to 67.
(3) An explicit argument (Explicit Arg.) Is placed in an area of registers% o0 to 5 and% sp + 92 or more.

First, in order to distinguish between a global variable and a local variable, generally, the OS determines the upper limit of the data size and stack size at the time of execution, and assumes the following matters.
(1) Global variables are placed in the area below LIMIT.
(2)% sp never falls below LIMIT, and the area from LIMIT to% sp is invalid.

  FIG. 11 shows an outline of arguments and frames in the memory map when the function A calls the function B while satisfying the above conditions. A method for distinguishing the local variable A and the local variable B will be described below with reference to FIG.

  In the figure, (a) shows a state in which A is being executed. Instructions (Instructions) and global variables (Global Vars.) Are stored in a thick frame part less than LIMIT, and valid values are stored above% sp. In% sp + 64, the head address of the structure is stored as an implicit argument when B returns the structure. The first 6 words of the explicit argument for B are stored in registers% o0 to 5 and the seventh and subsequent words are stored in% sp + 92 or more. When an operand% sp + 92 having a base register% sp appears, this area is the seventh word of the argument, that is, a local variable of B. On the other hand, if the operand% sp + 92 does not appear, this area is a local variable of A. Thus, in the state (a), the local variable of A and the local variable of B can be distinguished by verifying the operand.

  On the other hand, (b) shows a state in which B is being executed. Arguments can be input, return values can be output, global variables and A local variables can be input / output. However, since B may accept a variable-length argument, it is generally impossible to determine whether the area of% fp + 92 or more is the local variable area of A or the local variable area of B.

  In order to distinguish local variables, first, the function call that detects the seventh word and the following of the argument at the time of (a) is excluded from the reuse target, and the function call that does not detect the seventh word and later is immediately before% sp + 92. Record the value of. In addition, since the appearance frequency of function calls using the seventh word and later is expected to be low, it is considered that the performance degradation due to the restriction that the function using the seventh word and later is excluded from reuse.

  From the above preparation, it can be seen that when the main memory reference address in (b) is greater than or equal to the previously recorded value of% sp + 92, it is a local variable of A, and if it is smaller, it is a local variable of B. At the time of execution of B, the global variable and the local variable of A are registered in the reuse table while excluding the local variable of B.

  At the time of reuse, since the local variable of B is excluded from input / output, the address of the local variable of B does not need to match. Therefore, any context can be reused as long as the input matches. However, for the global variable referenced by B and the local variable of A, both the address and data need to completely match the contents of the reuse table. That is, the point is how to cover the main memory addresses to be compared before executing B.

  The address of the global variable referred to by B or the local variable of A is originally based on an address constant generated in B or a pointer originating from the global variable / argument. Therefore, first, by selecting an entry in the reuse table whose arguments completely match, by referring to all the related main memory addresses and performing a matching comparison, it is possible to cover the main memory addresses that B should refer to. it can. The registered output (return value, global variable, and A local variable) can be reused only when all the inputs match.

  In order to realize function reuse, a function management table (RF) and an input / output record table (RB) are provided as reuse tables. A hardware configuration necessary for reusing one function is shown in FIG. To make a plurality of functions reusable, a plurality of sets of this configuration are prepared.

  In this table, V held in RF and RB is a flag indicating whether or not an entry is valid, and LRU (least recently used) indicates a hint for entry replacement. In addition to the above V and LRU, the RF holds the start address (Start) of the function and the main memory address (Read / Write) to be referred to. In addition to the above V and LRU, RB includes% sp (SP) immediately before the function call, argument (Args.) (V: valid entry, Val .: value), main memory value (Mask: Read / Write address) Holds valid byte, Value: value), and Return Values (V: valid entry, Val .: value).

  The return value is stored in% i0 to 1 (read as% o0 to 1 in the leaf function) or% f0 to 1, and the return value using% f2 to 3 (extended double precision floating point number) is not included in the target program. Assume that it does not exist. The read address is collectively managed by the RF, and the mask and value are managed by the RB, thereby enabling a configuration in which the contents of the read address and a plurality of entries of the RB are compared at once by a CAM (content-addressable memory).

  To reuse a single function, first, input / output information related to arguments, return values, global variables, and local variables of higher-level functions is registered in the reuse table while excluding local variables when the function is executed. . Here, the argument register preceded by reading is registered as the input / output of the function, and the writing to the return value register is registered as the output of the function. Other register references do not need to be registered. Similarly, in the main memory reference, an address preceded by reading is registered as input and writing as output.

  When the next function is called before returning from the function, or the input / output to be registered exceeds the capacity of the reuse table, the seventh word of the argument is detected, a system call or interrupt occurs in the middle, etc. If no disturbance occurs, the registered I / O table entry is validated when the return instruction is executed.

Hereinafter, with reference to FIG. 12, before calling a function, (1) a function head address is searched, (2) an entry whose arguments completely match is selected, and (3) an associated main memory address, that is, All read addresses for which at least one mask is valid are referred to, and (4) match comparison is performed. When all the inputs match, the execution of the function can be omitted by writing back the registered output (return value, global variable, and A local variable).
IPSJ Transactions: High Performance Computing System, HPS5, pp.1-12, Sep. (2002), "High-speed technology using function value reuse and parallel pre-execution" (Yasuhiko Nakajima, Katsuya Ogata, Shingo Masanishi) Masahiro Goto, Junichiro Mori, Toshiaki Kitamura, Junji Tomita) (issued on September 15, 2002)

  In the above prior art, in RB, the number of items (horizontal length) in each entry is fixed. Therefore, items other than the registered items cannot be added. On the other hand, the memory area corresponding to the item that is not used is an empty area, but this cannot be used effectively.

  Also, each entry must be registered as a separate entry if the contents of even one item are different. Therefore, the memory utilization efficiency in the RB is not good.

  The present invention has been made to solve the above-described problems, and its purpose is to reduce memory redundancy by reducing the redundancy of stored contents in an instruction interval storage means used for value reuse. An object of the present invention is to provide a data processing apparatus, a data processing program, and a recording medium on which the data processing program is recorded.

  In order to solve the above problems, the data processing apparatus according to the present invention is a data processing apparatus for performing a process of reading a command section from a main storage unit and writing a result of arithmetic processing into the main storage unit. Storing a first calculation means for performing an operation based on an instruction section read from a register, a register used when reading and writing to the main storage means by the first calculation means, and an input pattern and an output pattern for a plurality of instruction sections When the first calculation means executes the instruction section, the input pattern of the instruction section matches the input pattern stored in the instruction section storage means. The output pattern stored in the instruction section storage means corresponding to the input pattern is stored in a register and / or main storage means The command section storage means includes input pattern storage means for storing a plurality of input patterns as a tree structure in which items to be matched are regarded as nodes. .

  Further, in the data processing apparatus according to the present invention, in the above configuration, the input pattern storage means stores the value of the item to be compared and matched in the input pattern in correspondence with the item to be compared next. Therefore, the above tree structure may be realized.

  In the data processing device according to the present invention, in the above configuration, the input pattern storage means includes an associative search means and an additional storage means, and the associative search means stores the values of items to be matched and compared. One or more search target lines each having a value storage area for storing the key for identifying the item, and the additional storage means performs the following for each corresponding line corresponding to the search target line: It is good also as a structure which has the search item designation | designated area | region which stores the item which should perform an associative search.

  In the data processing apparatus according to the present invention, in the above configuration, the additional storage unit includes a termination presentation area for storing a termination flag indicating that there is no item to be subjected to associative search next for each of the corresponding lines. Furthermore, it is good also as a structure which has.

  Further, in the data processing apparatus according to the present invention, in the above configuration, the additional storage means needs to perform a value comparison for the item designated in the search item designation area for each corresponding line. It may be configured to further include a comparison required presentation area for storing a comparison required flag indicating that.

  Further, in the data processing device according to the present invention, in the above configuration, the additional storage means includes a comparison required item designation area indicating an item to be subjected to a next value comparison for each corresponding line, and a value next. It may be configured to further include a comparison-required key designation area for storing a key for identifying an item to be compared.

  In the data processing apparatus according to the present invention, in the above configuration, the additional storage unit further includes a parent node storage area indicating the search target line for which the associative search was performed immediately before for each corresponding line. It is good also as composition which has.

  In order to solve the above problems, the data processing apparatus according to the present invention is a data processing apparatus that performs processing for reading a command section from a main storage means and writing a result of arithmetic processing into the main storage means. A first arithmetic unit that performs an operation based on an instruction interval read from the storage unit; a register that is used when the first arithmetic unit reads from and writes to the main storage unit; and an input pattern and an output pattern that relate to a plurality of instruction intervals Instruction section storage means for storing the instruction section, and when the first calculation means executes the instruction section, the input pattern of the instruction section matches the input pattern stored in the instruction section storage means In this case, the output pattern stored in the instruction section storage means corresponding to the input pattern is stored in the register and / or main memory. The command section storage means stores each output pattern for each item to be output, and stores the next item to be output for each item to be output. A first output pattern storage means for storing information for specifying the position where the current position is stored.

  In the data processing device according to the present invention, in the above configuration, the command section storage unit stores the items to be output in the output pattern in a one-to-one correspondence with the plurality of input patterns. An output pattern storage unit may be further provided, and the first output pattern storage unit may store items that could not be stored in the second output pattern storage unit.

  In the data processing device according to the present invention, in the above configuration, the command section storage unit stores each output pattern for each item to be output, and outputs the next for each item to be output. It is good also as a structure provided with the 1st output pattern memory | storage means in which the information which specifies the position where the power item is stored is stored.

  In the data processing device according to the present invention, in the above configuration, the command section storage unit stores the items to be output in the output pattern in a one-to-one correspondence with the plurality of input patterns. An output pattern storage unit may be further provided, and the first output pattern storage unit may store items that could not be stored in the second output pattern storage unit.

  In the data processing device according to the present invention, in the above configuration, the input pattern includes a program count value that specifies a head of an instruction interval, a register input value that is input to the register during execution of the instruction interval, and / or Or a main memory input value input to the main memory means when the instruction section is executed as the item, and the output pattern is a register output value output to the register when the instruction section is executed, and Alternatively, the main memory output value output to the main memory means during execution of the instruction section may be included as the item.

  In the data processing apparatus according to the present invention, in the above configuration, when the first arithmetic unit executes the instruction section, the comparison order of each item in the input pattern stored in the input pattern storage unit In accordance with the above, each item of the input pattern of the command section is matched and compared, and when an unmatched item appears, an arithmetic process is performed without performing a reuse process. And an output pattern as a result of the arithmetic processing may be registered in the instruction section storage means.

  Further, in the data processing apparatus according to the present invention, in the above configuration, when the first arithmetic unit detects that the value in the register or the main storage unit is changed, the item whose value is changed However, if the item is stored as an input pattern item in the input pattern storage unit, the additional storage unit may set the comparison flag as a comparison item for the item.

  Further, the data processing apparatus according to the present invention further includes at least one second calculation means in the above configuration, wherein the second calculation means is an instruction that is processed by the first calculation means. Regarding the section, the instruction section may be calculated based on a predicted input value expected to be input in the future, and the result may be registered in the instruction section storage means.

  As described above, the data processing apparatus according to the present invention, when the first arithmetic means executes an instruction interval, the input pattern of the instruction interval and the input pattern stored in the instruction interval storage means are When they match, the recycle processing is performed to output the output pattern stored in the instruction section storage means corresponding to the input pattern to the register and / or the main storage means. The instruction section storage means is provided with input pattern storage means for storing a plurality of input patterns as a tree structure in which items to be matched and compared are regarded as nodes. Therefore, items that are common in a plurality of input patterns can be stored as one node, so that the redundancy of the stored contents in the input pattern storage means can be reduced. Therefore, since the storage capacity required for the instruction section storage means can be reduced, the cost of the data processing apparatus itself can be reduced.

  In the data processing apparatus according to the present invention, as described above, the input pattern storage means may store the value of the item to be compared and matched with the next item to be compared in the input pattern. . In this case, since it is possible to sequentially match and compare items to be matched, it is possible to realize storing an input pattern as a tree structure in which the items to be matched and compared are regarded as nodes.

  In the data processing apparatus according to the present invention, as described above, the input pattern storage unit may include an associative search unit and an additional storage unit. The associative search means has one or more search target lines each having a value storage area and a key storage area, and the additional storage means has a search item designation area for each corresponding line. May be. In this case, when the value of the item to be matched and compared is input to the associative search means, the search target line whose value and key match is single matched, and the corresponding line in the additional storage means corresponding to the single match search target line Thus, the item to be subjected to the associative search next is determined.

  Here, since each input pattern is stored as a tree structure in which items to be matched and compared are regarded as nodes, in the associative search means, there is one search target that matches for a certain item as described above (single Match). While an associative search memory having only a single match mechanism is generally marketed, an associative search memory that can report multimatches with the same performance as a single match is generally not commercially available. That is, according to the above configuration, since a commercially available associative search memory can be used as an associative search means, the data processing device according to the present invention can be realized in a shorter period of time and at a lower cost.

  In addition, as described above, the data processing apparatus according to the present invention further includes a termination presentation area in which the additional storage unit stores a termination flag indicating that there is no item to be searched next for each corresponding line. It may be the composition which is doing. In this case, the number of items of each input pattern can be made variable by setting a termination flag. That is, in the input pattern, it is possible to flexibly cope with a case where there are many items to be compared and a few items. In addition, when the number of input pattern items is fixed, there is a problem in that when there are few items to be matched and compared, there is a waste of memory areas that are not used, resulting in poor memory use efficiency. According to the above configuration, such a problem can be solved.

  In addition, as described above, the data processing apparatus according to the present invention requires that the additional storage means perform value matching comparison for the items specified in the search item specification area for each corresponding line. It may be configured to further include a comparison required presentation area for storing a comparison required flag. In this case, it is clear that the value matching comparison should be performed only for the item for which the comparison required flag is set, so that the value matching comparison is not performed more than necessary. Therefore, processing efficiency can be improved.

  In the data processing device according to the present invention, as described above, the additional storage means further includes a comparison item specification area and a comparison key specification area for each corresponding line. Also good. In this case, it is possible to perform an associative search in the associative search means by using the value related to the item specified in the comparison required item specifying area and the key specified in the comparison required key specifying area.

  Here, when these comparison required item designation area and comparison required key designation area are not provided, the following problem occurs. That is, when the comparison required flag is not set in the corresponding line, the associative search is performed without performing a value match comparison in the associative search means, and this process is repeated until the corresponding line for which the comparison required flag is set. become. On the other hand, as described above, an associative search operation that does not perform a coincidence comparison of values as described above is performed by providing a comparison required item specifying area and a comparison required key specifying area for each corresponding line. Without this, it is possible to perform matching comparison of input patterns. Therefore, the processing speed can be improved.

  In the data processing apparatus according to the present invention, as described above, the additional storage means further includes a parent node storage area indicating the search target line for which the associative search was performed immediately before for each corresponding line. It may be the composition which is. In this case, for an item in a certain input pattern, for example, a value match comparison is not necessary because of a change in a value in a register or main storage means. In this case, it is possible to perform processing for registering the corresponding item and the corresponding key in the comparison required item specifying area and the comparison required key specifying area in the corresponding line corresponding to the parent node.

  In addition, as described above, the data processing device according to the present invention stores, for each item to be output, information specifying the position where the item to be output next is stored for each item to be output. The first output pattern storage unit may be provided. In this case, items to be output can be stored at arbitrary positions in the first output pattern storage means. Therefore, the memory utilization efficiency can be improved as compared with a configuration in which each item of the output pattern is stored in association with, for example, one line.

  In the data processing device according to the present invention, as described above, the command section storage means stores the items to be output in the output pattern in one-to-one correspondence with the plurality of input patterns. Pattern storage means is further provided, and the first output pattern storage means may be configured to store items that could not be stored in the second output pattern storage means. In this case, when the number of output pattern items is small, the high-speed processing is realized by using only the second output pattern storage means, and when the number of output pattern items is large, the number of items can be made variable. This is dealt with by using possible first output pattern storage means. Therefore, according to the above configuration, it is possible to realize high-speed processing and improvement in memory utilization efficiency.

  In addition, as described above, the data processing apparatus according to the present invention includes a program count value that identifies the beginning of an instruction interval, a register input value that is input to the register when the instruction interval is executed, and / or the instruction interval. The main memory input value that is input to the main memory means at the time of execution is included as the item, and the output pattern is a register output value that is output to the register at the time of execution of the instruction interval, and / or the instruction The main memory output value output to the main memory means at the time of execution of the section may be included as the item. In this case, it is possible to accurately perform the reuse process regardless of whether the instruction section is a function or a loop.

  In addition, as described above, the data processing apparatus according to the present invention follows the comparison order of each item in the input pattern stored in the input pattern storage unit when the first calculation unit executes the instruction section. The items of the input pattern in the command section are compared and compared, and when an unmatched item appears, the calculation process is performed without performing the reuse process, and the unmatched item is stored in the input pattern storage means. It may be configured to register and register an output pattern as a calculation processing result in the instruction section storage means. In this case, when the input pattern is registered in the input pattern storage means, the input pattern items from the time when an item different from the already registered items appears are registered. Therefore, the input pattern can be stored as a tree structure in which items to be matched and compared are regarded as nodes.

  In addition, as described above, when the first arithmetic unit detects that the value in the register or the main storage unit has been changed, the data processing device according to the present invention displays the item whose value has been changed. If the input pattern is stored as an input pattern item in the input pattern storage means, the additional storage means may be configured to set the comparison required flag as a comparison required for the item.

  Here, when the value of the item registered in the input pattern storage unit is changed, the value registered in the input pattern storage unit is different from the value actually stored in the corresponding item. It becomes a state. In such a state, if the instruction section is reused without comparing the corresponding items, an erroneous calculation result may be output. On the other hand, according to the above configuration, when the above state is reached, the comparison required flag corresponding to the corresponding item is set as a comparison required. Therefore, it is possible to accurately perform matching comparison of each item of the input pattern only when necessary.

  In the data processing apparatus according to the present invention, as described above, the second calculation means sets the predicted input value that is expected to be input in the future with respect to the instruction section being processed by the first calculation means. On the basis of the calculation of the instruction section, the result may be registered in the instruction section storage means. In this case, the second arithmetic unit performs an operation based on the predicted input value for the instruction interval currently being processed by the first arithmetic unit, and the result is stored in the instruction interval storage unit. It will be. Therefore, next, when the same command section appears and the same input as the predicted input value is made, the value stored in the command section storage means can be reused. For example, in the case of an instruction interval in which the input value changes monotonously, the predicted input value is likely to be correct, so the effect of the above configuration is high.

  An embodiment of the present invention will be described below with reference to FIGS.

(Configuration of data processing device)
FIG. 2 shows a schematic configuration of the data processing apparatus according to the present embodiment. As shown in the figure, the data processing apparatus includes an MSP (Main Stream Processor) 1A, an SSP (Shadow Stream Processor) 1B, an instruction interval storage unit (instruction interval storage means) 2 as a reuse table, and a main memory ( Main storage means) 3 is provided, which reads out program data and the like stored in the main memory 3, performs various arithmetic processes, and performs a process of writing the arithmetic results into the main memory 3. In the configuration shown in the figure, the configuration includes one SSP 1B, but the configuration may include two or more. Moreover, although the configuration shown in FIG. 6 is provided with the SSP 1B, it may be configured without the SSP 1B. Operations and effects when the SSP 1B is provided will be described later.

  The instruction section storage unit 2 is memory means for storing data for reusing instruction sections such as functions and loops in a program. Details of the command section storage unit 2 will be described later.

  The main memory 3 is a memory as a work area of the MSP 1A and the SSP 1B, and is constituted by, for example, a RAM (Random Access Memory). For example, programs and data are read to the main memory 3 from an external storage means such as a hard disk or an external device such as an external input / output (I / O) device, and the MSP 1A and SSP 1B are read to the main memory 3. The calculation is performed based on the obtained data. Also, the calculation result by the MSP 1A is written in the main memory 3, and the calculation result is sent to the external device.

  The MSP 1A includes a RW (first arithmetic means) 4A, a computing unit (first arithmetic means) 5A, a register 6A, and a Cache 7A as reuse storage means. Similarly, the SSP 1B includes an RW (second arithmetic unit) 4B, a calculator (second arithmetic unit) 5B, a register 6B, and a Cache / Local 7B as reuse storage units. .

  RW4A and 4B are reuse windows, and hold each line of RF (additional storage means) and RB (associative search means) (to be described later) currently being executed and registered as a ring structure stack. . The actual hardware structure of the RWs 4A and 4B includes a set of control lines that activate a specific line in the instruction section storage unit 2.

  The arithmetic units 5A and 5B perform arithmetic processing based on the data held in the registers 6A and 6B, and are called ALUs (arithmetic and logical units). The registers 6A and 6B are storage means for holding data for performing calculations by the calculators 5A and 5B. In this embodiment, it is assumed that the arithmetic units 5A and 5B and the registers 6A and 6B conform to the SPARC architecture. The Caches 7A and 7B function as cache memories between the main memory 3 and the MSP 1A and SSP 1B. In SSP1B, Cache7B includes Local7B as a local memory.

(Configuration of instruction section storage)
FIG. 1 shows a reuse table realized by the instruction interval storage unit 2 in the present embodiment. As shown in the figure, the instruction interval storage unit 2 includes RB, RF, RO1 (second output pattern storage means), and RO2 (first output pattern storage means).

  The RB includes a value (value storage area) for storing a register value or a main memory input value, which is a value to be compared, and a key (key storage area) for storing a key number. There are multiple.

  RF is an end flag E indicating that there is no register number or main memory address to be compared next, a comparison required flag indicating that the contents of the register number or main memory address to be compared next is updated, and then comparing R / M indicating whether the object to be registered is a register or main memory, Adr. (Search item designation area) indicating the register number or main memory address to be compared next, UP indicating the line number referenced immediately before (stored in parent node) Area), Alt. (Comparison item specification area) indicating the register number or main memory address to be compared with priority over the register number or main memory address to be compared next, and necessary for priority comparison DN (comparison key designation area) indicating a correct key is provided corresponding to each line in the RB.

  RO1 and RO2 store an output value to be output to the main memory and / or a register when it is determined that reuse is possible based on the search results by RB and RF. RO1 stores an output value and an address to be output in one-to-one correspondence with each line of RF. RO2 stores output values and addresses to be output when the output values cannot be stored by RO1 alone. When it is necessary to read the output value from RO2, a pointer storing the output value at RO2 is shown in the corresponding line at RO1, and the output value is read from RO2 using this pointer. .

  Further, the RB and the RF are configured by a CAM (content-addressable memory) and a RAM (Random Access Memory), respectively. Generally, when an address is given, a memory that can refer to a value stored at the address is a memory called a RAM. On the other hand, the CAM is a memory called an associative memory, and when a content to be searched is given, a line that matches the content is selected. Normally, CAM is used as a set with RAM.

  Here, the cooperative operation between the CAM and the RAM will be described with a specific example. "5, 5, 5, 5, 5", "1, 3, 1, 1, 1", "1, 3, 3, 5, 2", "6, 6, 6, 6, 6" The data strings “5, 5”, “1, 1”, “1, 2”, “6, 6” are stored in the RAM corresponding to the data strings in the CAM. Suppose that it is registered. Here, when “1, 3, 3, 5, 2” is input to the CAM as the data string to be searched, the matching entry is turned ON, and the corresponding data “1, 2” registered in the RAM is output. Will be. The above RB and RF are realized by the same configuration and operation as this specific example.

(Comparative example)
Here, as a comparative example, the operation by the RF and RB having the configuration shown in FIG. 8 will be described. As shown in the figure, RF indicates a status display flag V indicating whether or not an entry is valid, an LRU indicating an entry replacement hint, an F / L for distinguishing a function from a loop, and a head address of an instruction section. And Start indicating the end address of the instruction section, Read indicating information related to the main memory input address to be referred to, and Write indicating information related to the main memory output address to be referred to.

  RB is a status display flag V indicating whether the entry is valid, an LRU indicating an entry replacement hint, an SP indicating the stack point% sp immediately before calling the instruction section, an end address of the loop (End ), Taken / not indicating the branch direction at the end of the loop, argument (Args.) (V: valid entry, Val .: value) as register input value, and register input value and condition code other than argument (Regs., CC) ), Main memory input valid byte Mask, Main memory input value Value, Main memory output valid byte Mask, Main memory output value Value, Return value Return value as register output value, and register output value and condition code other than return value Regs., CC (V: Valid entry, Val .: Value) are held.

  When a function or loop is executed, it is determined in the following procedure when it is determined whether or not a previously executed instruction section can be reused. First, (1) a search is made as to whether a start address Start of a function or loop entry registered in RF matches the start address of the corresponding function or loop. If there is a match, (2) among the corresponding entries registered in the RB, an entry whose status display flag V indicating a valid entry is set to the registered state, and in the entry Selects one or more entries whose arguments args. And Regs., CC exactly match the corresponding value of the function or loop to call. In the selected entry, (3) the main memory is sequentially referred to using the relevant main memory address, that is, the read address where at least one mask is valid, and (4) the main memory input value of the corresponding function or loop. And the main memory input value registered in the RB. When all inputs match, (5) Return Values stored in the RB are written to the register, and the main memory output value in which each valid flag Mask is sequentially set for the main memory output address. Write Value. As described above, the reuse of the function or loop is realized.

  The operation in the comparative example as described above will be described more specifically with reference to FIG. First, the program counter (PC) and the instruction section start address (Region) registered in the RF are compared, and the register contents (Reg.) And the register input values (Args.,. Regs., CC). At this time, it is assumed that entry 03 and entry 04 are determined to match among entries 01 to 04 in RB. That is, at this point, it is a multi-match.

  Next, comparison is made with respect to the main memory address A1, but for the main memory address A1, a flag (0) indicating that it is not necessary to perform a coincidence comparison is shown in RF. Is not done. That is, entry 03 and entry 04 remain as candidates.

  Next, a comparison is made with respect to the main memory address A2. Here, in the RF, the flag (1) indicating that it is necessary to perform a coincidence comparison with respect to the main memory address A2 is shown, so the coincidence comparison is performed. As a result, only the entry 03 whose content is “00” remains as a candidate. Thereafter, there are main memory addresses A3 and A4 as items to be subjected to coincidence comparison. However, since both of them indicate a flag indicating that it is not necessary to perform coincidence comparison, entry 03 includes all of the items requiring comparison. The item matches. Therefore, the main memory output value and the register output value as the output values corresponding to the entry 03 are output to the main memory and the register.

  The points of operation in this comparative example are as follows. (A) When comparing each value registered in the RB with the corresponding value in the function or loop to be reused, the vertical columns in the RB are sequentially checked for coincidence. It is allowed that multiple entries with the same content exist (multi-match). (B) Although multi-matching is permitted during the search, one entry may be finally selected. (C) Since the order in which the columns in the RBs are checked for coincidence is arbitrary, it is possible to compare, for example, register input values together first.

  In addition, this comparative example has the following problems. (D) In RB, the number of items (horizontal length) in each entry is fixed. Therefore, items other than the registered items cannot be added. On the other hand, the memory area corresponding to the item that is not used is an empty area, but this cannot be used effectively. (E) Each entry must be registered as a separate entry if the contents of one item are different. Therefore, the memory utilization efficiency in the RB is not good.

  In the case of the comparative example as described above, the memory constituting the RF and RB has a horizontally long structure. For example, if this memory capacity is 2 Mbytes, the horizontal width is 2 Kwords and the vertical length is 256 entries.

(Associative search operation in this embodiment)
Next, an associative search operation in the instruction interval storage unit 2 in the present embodiment will be described. In the above comparative example, the horizontal row as each entry in the RB includes all items of input values to be subjected to matching comparison. That is, all input patterns are registered in the RB as one entry.

  On the other hand, in this embodiment, items of input values to be subjected to matching comparison are divided into short units, each comparison unit is regarded as a node, and an input pattern is registered in RF and RB as a tree structure. Yes. Then, when reusing, by sequentially selecting matching nodes, it is determined whether or not reusable is finally possible. In other words, portions common to a plurality of input patterns are combined into one and associated with one line of RF and RB.

  As a result, redundancy can be eliminated and the utilization efficiency of the memory constituting the instruction section storage unit 2 can be improved. Also, since the input pattern has a tree structure, it is not necessary to associate one input pattern with an entry as one row in the RB. Therefore, it is possible to vary the number of input value items to be subjected to coincidence comparison.

  Also, since RF and RB register their input patterns as a tree structure, multimatching is not performed when matching comparison is performed. That is, the instruction interval storage unit 2 can be realized as long as it is an associative search memory having a single match mechanism. Here, while an associative search memory having only a single match mechanism is generally marketed, an associative search memory capable of reporting multimatches with the same performance as a single match is not generally marketed. That is, according to the instruction section storage unit 2 in the present embodiment, a commercially available associative search memory can be used, so that the data processing apparatus according to the present embodiment can be realized in a shorter period of time and at a lower cost. It becomes.

  Next, a specific example of the associative search operation in the instruction interval storage unit 2 in the present embodiment will be described with reference to FIG. First, when execution of an instruction interval is detected, a program counter (PC) and register contents (Reg.) Are input to the RB. Then, in the RB, these values inputted by the associative search are compared with the instruction section start address and the register value registered in the Value column of the RB, and the only line (line) in which the values match is found. Selected as a candidate (match line). In this example, the “01” line in the RB is selected as the match line.

  Next, “01”, which is the address in the RB of the line selected as the match line, is transmitted to the RF as an encoding result, and the line in the RF corresponding to the key 01 is referred to. In the RF line corresponding to the key 01, the comparison required flag is “0”, and the main storage address to be compared is A1. That is, it is not necessary to perform a coincidence comparison on the main memory address A1.

  Next, using the key 01, a search is performed on the Key column in the RB. In this example, the line “03” in RB is selected as the match line. Then, the key 03 is transmitted to the RF as an encoding result, and the line in the RF corresponding to the key 03 is referred to. In the RF line corresponding to the key 03, the comparison required flag is “1”, and the main storage address to be compared is A2. That is, it is necessary to perform a coincidence comparison on the main memory address A2. Here, the value of the main memory address A2 in the main memory 3 is read via the Cache 7A, and in RB, the value is the value read from the main memory 3, and the key is “03”. A line is searched. In the example shown in FIG. 3, there are two lines “04” and “05” whose Key is “03”. However, since the value read from the main memory 3 is “00”, “05” "Is selected as a match line, and the key 05 is transmitted to the RF as an encoding result.

  When the above processing is repeated and a termination flag E indicating that there is no register number or main memory address to be compared next is detected in RF, it is determined that all the input patterns match, and the corresponding instruction section Is determined to be reusable. Then, a “Select Output” signal is output from the line in which the termination flag E is detected, and output values corresponding to the lines stored in RO1 and RO2 are output to the register 6A and the main memory 3.

As described above, the associative search operation by the instruction interval storage unit 2 in the present embodiment has the following characteristics. First, since there is only one match line in the RB indicating that the contents match, it is only necessary to transmit one encoded result when propagating the search operation to the next column. Therefore, one set (N) of signal lines connecting the RB and the RF may be sufficient as the result of address encoding. On the other hand, in the comparative example described above, since multi-matching is allowed in the RB, the signal lines that connect the columns in the RB must be provided for each line (2 ^N lines). . That is, according to the configuration of the present embodiment, the number of signal lines in the associative search memory constituting the instruction interval storage unit 2 can be significantly reduced.

  Further, since only a single match is allowed during the search, the comparison order of items to be compared is limited to the reference order in the tree structure. That is, it is necessary to compare the register value and the memory contents while mixing them in the reference order.

  The input pattern is registered in RB and RF by a tree structure by linking each item in the form of Key to be referred to. Further, the end of the input pattern item is indicated by the end flag. Therefore, since the number of input pattern items can be made variable, the number of input pattern items can be flexibly set in accordance with the state of the command section to be registered in the reuse table. In addition, since the number of items in the input pattern is not fixed, the unused area does not occupy the memory area unnecessarily, and the use efficiency of the memory area can be improved.

  In addition, since the input pattern is registered by the tree structure, it is possible to share one line with a plurality of input patterns for portions where the contents of the items overlap. Therefore, the utilization efficiency of the memory area can be further improved.

  In the case of the above configuration, the memory constituting the RF and RB has a vertically long structure. For example, when the memory capacity is 2 Mbytes, the horizontal is 8 words and the vertical is 65536 lines.

(Another example of associative search)
In the above example, the items UP, Alt., And DN are not used in the RF shown in FIG. That is, in the above example, it is not necessary to provide these items in the RF. On the other hand, a configuration and operation for further speeding up the associative search operation by using items of UP, Alt., And DN will be described below.

  First, in FIG. 4B, only the program counter (PC) and the register contents (Reg.) Are compared, and if they match, the section can be reused without comparing the main memory values. The state when it can be determined that it exists is shown. In this state, first, PC and Reg. Are registered in Value in the RB “01” line. In the RF “01” line, the termination flag is “E” and the comparison required flag is “0”. The main storage address to be compared is “A1”, and the UP indicating the parent node number is “FF”. In the RB “03” line, the Key is “01” without the Value value, and in the RF “03” line, the termination flag is “E”, the comparison required flag is “0”, The main storage address to be compared is “A2”, and the UP indicating the parent node number is “FF”. Thereafter, similarly, the “05” line and the “07” line in the RB and RF are registered, the termination flag is “E”, and the comparison required flag is “0”, respectively.

  In this state, when execution of a certain instruction section is detected, PC and Reg. Are input to the RB, and the line “01” in the RB is selected as a match line. Then, “01” which is the address in the RB of the line selected as the match line is transmitted to the RF as an encoding result, and the line in the RF corresponding to the key 01 is referred to. Since the end flag is “E” in the line corresponding to the key 01, it can be seen that there is no main memory address to be compared next. Further, since the comparison required flag is “0”, it can be seen that it is not necessary to compare the main memory address A1.

  Therefore, as shown in the tree structure of FIG. 4A, when the coincidence of PC and Reg. Is confirmed in S1, comparison is performed at main memory addresses A1, A2, and A3 as in the node indicated by Tr1. Instead, the corresponding output value is output.

  When RF and RB are in this state, it is assumed that writing has been performed on the main memory address A2. In this case, it is not necessary to perform a coincidence comparison of the main memory address A2 at the time of registering the input pattern in the RF and RB. There will be a need. Therefore, in this case, RF and RB are changed as shown in FIG.

First, using A2 which is the main memory address whose contents are changed as a key, Adr.
A search is performed on the columns. As a result, the line “03” in RF is selected. Then, in the selected line “03”, the comparison required flag is set to “1” and the end flag “E” is deleted.

  Next, by referring to the UP in the “03” line, the “01” line as the parent node is recognized. In the line “01”, A2 which is the main storage address whose contents are changed is written to Alt. Indicating the main storage address to be compared with priority over the main storage address to be compared next. The termination flag “E” is deleted. Further, in the “01” line, “03” is written in the DN indicating the key required for the priority comparison.

  The associative search operation when RF and RB are rewritten as described above is as follows. When a certain instruction section is detected, first, PC and Reg. Are input to RB. Then, in the RB, these values input by the associative search are compared with the instruction section start address and register value registered in the Value column of the RB, and the “01” line in the RB is used as a match line. Selected.

  Next, “01”, which is the address in the RB of the line selected as the match line, is transmitted to the RF as an encoding result, and the line in the RF corresponding to the key 01 is referred to. In the RF line corresponding to the key 01, the comparison required flag is “0”, and the main storage address to be compared is A1. That is, it can be seen that it is not necessary to perform a coincidence comparison with respect to the main memory address A1.

  Also, the main memory address A2 is registered in Alt. Indicating the main memory address to be compared with priority over the main memory address to be compared next, and DN indicating the key required for the priority comparison It is confirmed that “03” is registered in. In this case, the value of the main memory address A2 in the main memory 3 is read through the Cache 7A, and in RB, Value is the value read from the main memory 3, and Key is indicated in DN. A line with “03” is searched.

  In the example shown in FIG. 5B, there are two lines “04” and “05” with Key “03”, but the value read from the main memory 3 is “00”. , “05” is selected as a match line, and key 05 is transmitted to RF as an encoding result. In the line in RF corresponding to the key 05, since the termination flag is “E”, it is determined that all the input patterns match, and the corresponding command section is determined to be reusable. Then, a “Select Output” signal is output from the line in which the termination flag E is detected, and output values corresponding to the lines stored in RO1 and RO2 are output to the register 6A and the main memory 3.

  According to the associative search operation as described above, in RF, Alt. Indicating the main memory address to be compared with priority over the main memory address to be compared next, and the key necessary for the priority comparison Therefore, it is possible to skip the search by the contents of the main storage address A1 and the key 01 and the search by the contents of the main storage address A2 and the key 03. Accordingly, the processing steps of the search operation can be reduced, and the processing speed can be increased.

(Output value storage means)
In the above description, the input pattern of the instruction section is registered in RF and RB, and the associative search operation is performed. However, in the following, the output value output as reuse is stored after the input pattern match is confirmed. The means to do will be described. As described above with reference to FIG. 1, the instruction interval storage unit 2 stores an output value for storing an output value to be output to the main memory and / or the register when it is determined that reuse is possible. RO1 and RO2 are provided as storage means.

  The output value can be obtained by referring to storage means such as a RAM for storing the output value based on the address output from the RF and RB. However, like the input pattern, it is preferable that the number of output value items be variable for the output pattern, and thus a device for storing the output value needs to be devised.

  The input pattern is registered in a tree structure in RF and RB. Then, it is determined that reuse is possible in the line that is the end of the tree structure, that is, the line in which the end flag E is registered. Therefore, by registering a pointer in the output value storage means for storing the output value to be output in each line in which the termination flag E is registered, it is possible to perform an output operation at the time of reuse. .

  However, when the storage position in the output value storage unit is specified based on the pointer storing the output value when it is confirmed that all the input patterns match, the storage position is specified based on the pointer. Conversion processing is required, which causes a reduction in processing speed.

  Therefore, in the present embodiment, two storage means, RO1 and RO2, are provided as output value storage means. RO1 stores an output value and an address to be output in a one-to-one correspondence with each line of RF. That is, when it is determined that the RF line in which the termination flag E is registered can be reused, the RO1 line corresponding to the line is selected and the output value is output.

  However, in this way, when the output value storage means stores the output value and the address to be output in one-to-one correspondence with each line of the RF, the RF in which the termination flag E is not registered in the RF A memory area is secured in RO1 for these lines. Further, since the output value is stored in RO1 corresponding to all the lines of the RF in which the termination flag E is registered, there is a redundancy that the same contents are stored in a plurality of places. Become. Therefore, RO1 is excellent in terms of processing at high speed, but it is not good in terms of memory utilization efficiency.

  In order to solve this problem, the number of items that can be registered in RO1, that is, the number of pairs of output values and output addresses is set to be small (two in the example of FIG. 1), and output that cannot be registered in RO1. A set of a value and an output address is registered in RO2 having a configuration in which a storage area is designated using a pointer.

  In RO2, since the storage area is indicated by the pointer, there is almost no unused memory area. Also, when registering multiple sets of output values and output addresses, you can connect them sequentially using pointers, so the number of sets of output values and output addresses that can be registered can be made variable. It is. Furthermore, since a pointer indicating the same storage position in RO2 can be designated from a plurality of lines in RO1, storage information in RO2 can also be shared by a plurality of lines in RO1. Therefore, in RO2, the redundancy of stored contents can be reduced.

  As described above, by providing two output value storage units, RO1 and RO2, when the number of output value items is small, the processing speed can be increased by using only RO1, and the number of output value items is large. The case is dealt with by using RO2, which can change the number of items. Therefore, according to the above configuration, it is possible to realize high-speed processing and improvement in memory utilization efficiency.

(Registration processing for the command section storage unit)
In the above, the operation in the case of reusing when executing a certain instruction section has been described. In the following, an operation when registering input / output in an instruction section in RF, RB, RO1, and RO2 when it is determined that reuse cannot be performed when executing a certain instruction section will be described.

  First, when execution of a certain instruction section is detected, the values of PC and Reg. Are input to RB. Then, in the RB, these values inputted by the associative search are compared with the instruction section start address and the register value registered in the Value column of the RB. Here, if it is determined that there is no RB Value column that matches the input value, it is determined that the instruction section cannot be reused, and the arithmetic unit 5A performs arithmetic processing. Is called. Then, the register input value, the main memory input value, the main memory output value, and the register output value that are used until the calculation process of the corresponding instruction section is completed are registered in RB, RF, RO1, and RO2 as necessary. . Here, when registering in RB and RF, registration is performed so that each item corresponds to one line so as to have the tree structure as described above. Then, in the line where the last item of the input pattern to be registered is registered, the RF termination flag is set to “E”, and the registration of the input pattern is completed.

  On the other hand, if an item that matches the entered PC and Reg. Values is registered in the RB Value column, the next item to be compared is compared in the same manner as the associative search operation described above. A match comparison is performed. In this way, the comparison between the input pattern registered in RB and RF and the input pattern in the corresponding instruction section is continued, and a new node is added when an unmatched item occurs. Then, registration is performed in the RB and RF for the mismatched items. Then, in the line where the last item of the input pattern to be registered is registered, the RF termination flag is set to “E”, and the registration of the input pattern is completed.

  When the registration of the input pattern is completed, the output value and the output address are registered in the line in RO1 corresponding to the line in RF whose end flag is “E”. When items to be registered as output values cannot be registered in RO1, registration is performed for RO2 using a pointer. Thus, the instruction section registration process is completed.

(Details of register values)
Register input / output values include arguments, return values (Args.), And registers and condition codes (Regs., CC) other than arguments and return values. In the present embodiment, among the SPARC architecture registers, general-purpose registers% g0-7,% o0-7,% l0-7,% i0-7, floating point register% f0-31, condition code register ICC, floating point condition code The register FCC is used (details will be described later). Of these, the leaf function input is general-purpose register% o0-5, the output is general-purpose register% o0-1 or% f0-1, the non-leaf function input is general-purpose register% i0-5, and the output is general-purpose register% i0 -1 or% f0-1, and the input is registered in arg [0-5] and the output is registered in rti [0-1] or% rtf [0-1]. According to the SPARC-ABI regulations, registers other than these are not input / output of functions, and therefore, for functions, Args. Is registered in RB and RO1 / RO2 as register input / output values.

  On the other hand, according to the SPARC-ABI rules, the type of register used cannot be specified for loop input / output. Therefore, in order to specify loop input / output, all types of registers must be registered in the RB. There is. Therefore, for the loop, register input / output values corresponding to Regs., CC,% g0-7,% o0-7,% l0-7,% i0-7,% f0-31, ICC, FCC are registered. Will be.

(Multiple reuse)
When the reuse mechanism as described above is used at one level, in the example shown in FIG. 10A, the function B as the leaf function, the loop C inside the function B, etc. are reused. It becomes possible. On the other hand, multiple reuse is a mechanism for performing registration so that all instruction sections including functions and loops included in the function can be reused by executing a function once. For example, in the above example, according to multiple reuse, all the instruction sections of A, B, and C that are nested can be reused by executing the function A once. The function expansion required for realizing multiple reuse will be described below.

  FIG. 6 shows a conceptual structure of the function A and the function D as an example. In the example shown in the figure, a loop B exists inside the function A, a loop C exists inside the loop B, and the function D is called in the loop C. A loop E exists inside the function D, and a loop F exists inside the loop E.

  7, in the nested structure of functions A and D and loops B, C, E, and F shown in FIG. 6, the register input / output (thick frame cell region) of the inner structure becomes the register input / output of the outer structure. The influence range (arrow) is shown. For example,% i0 to 5 referred to as an input in the loop F is also an input to the loop E and the function D, and further, an input to the loop C and the loop B that called the function D (but replaced with% o0 to 5) It is also. On the other hand, for function A,% o0 to 5 correspond to local variables, so% i0 to 5 (% o0 to 5) are not register inputs for function A. That is, the influence range of% i0 to 5 (% o0 to 5) is up to loop B. From another point of view, if% i0-5 is referenced inside function D,% o0-5 is input to loop B even if loop B does not directly reference% o0-5. Must be registered as a value. The same applies to% i0-1 output in the loop F.

  Since the floating point register is not included in the register window, the output% f0 to 1 is output of all layers including the function A. On the other hand, other register inputs and outputs have no effect beyond functions. That is, input / output in the loop F, that is,% i6-7,% g, l, o,% f0-31,% icc,% fcc as register inputs, and% I2-7,% g as register outputs , l, o,% f2 to 31,% icc,% fcc range up to loop E. For the input / output to / from the main memory, the influence range can be specified by applying the above-described method of comparison with% sp (SP) immediately before the function call to all nested hierarchies.

  Here, according to the configuration of the RW 4A, the RW 4B, and the instruction section storage unit 2 as described above, input / output of a plurality of instruction sections can be individually recorded, so that multiple reuse can be realized. It becomes possible.

(Parallel pre-execution)
The multiple reuse of functions and loops described above has no effect when the interval at which the same parameter appears is long or when the parameter continues to change monotonously. That is, when the same parameter appears longer than the lifetime of the RB entry, even when a certain function or loop is registered in the RB, the same parameter appears next for the registered function or loop. The function or loop has already disappeared from the RB entry and cannot be reused. In addition, when the parameter continues to change monotonously, even if the corresponding function or loop is registered in the RB, the parameter cannot be reused because the parameter is different.

  On the other hand, by providing a plurality of SSP1Bs as processors that enable the RB entry by pre-execution of the instruction section separately from the MSP1A as a processor that performs multiple reuse, it is possible to further increase the speed.

  The hardware configuration for performing the parallel pre-execution mechanism is as shown in FIG. As shown in the figure, the RWs 4A and 4B, the arithmetic units 5A and 5B, the registers 6A and 6B, and the caches 7A and 7B are provided independently for each processor, while the instruction section storage unit 2 and the main memory 3 is shared by all processors. In the figure, the broken lines indicate paths through which MSP 1A and SSP 1B register input / output to / from the instruction section storage unit 2.

  Here, there are two problems in realizing parallel pre-execution: (1) how to maintain main memory consistency, and (2) how to predict input. Below, the solution method with respect to these subjects is demonstrated.

(Solutions to main memory consistency issues)
First, the above problem (1) how to maintain main memory consistency will be described. In particular, when an instruction interval is executed based on a predicted input parameter, the value to be written to the main memory is different between MSP1A and SSP1B. In order to solve this, as shown in FIG. 2, the SSP 1B is provided for the instruction section storage unit 2 for the main memory reference to be registered in the RB and for each SSP 1B for other local references. Local 7B is used as a local memory, and writing to Cache 7B and main memory 3 is unnecessary. When the MSP 1A writes to the main memory 3, the corresponding SSP 1B cache line is invalidated.

  Specifically, the address and value are registered in the RB in the same manner as the MSP 1A with reference to the main memory 3 for the address preceded by the reading among the registration targets in the instruction section storage unit 2. Thereafter, by referring to the instruction section storage unit 2 instead of the main memory 3, it is possible to avoid the occurrence of contradiction due to overwriting from another processor. As for local reference, the fact that reading precedes corresponds to using a variable without initializing it, and the value may be indefinite, so it is not necessary to refer to the main memory 3.

  Note that the capacity of the Local 7B as a local memory is finite, and if the execution cannot be continued, such as when the size of the function frame exceeds the capacity of the Local 7B, the pre-execution is aborted. Further, since the result of the pre-execution is not written to the main memory 3, the next pre-execution cannot be performed using the pre-execution result.

(Input prediction method)
Next, the problem (2) how to predict the input will be described. In advance execution, it is necessary to predict a future input based on the usage history of the instruction section storage unit 2 and pass it to the SSP 1B. For this purpose, a small processor is provided for each input pattern stored in the instruction section storage unit 2, and an input predicted value is obtained independently of the MSP 1A and SSP 1B.

  Specifically, stride prediction is performed based on the last appearing argument (B) and the difference (D) between the two most recently appearing arguments. Note that the execution of the instruction interval based on B + D is considered to have already started by MSP 1A. When there are N SSPs 1B, the input predicted values to be prepared are in the range from B + D × 2 to B + D × (N + 1).

  If the input prediction is performed as described above, it is possible to effectively reuse the input parameter based on the result predicted in advance when the above-described input parameter continues to change monotonously.

  The data processing apparatus according to the present invention can be applied to the SPARC processor as described above. Further, like the SPARC processor, the present invention can be applied to many RISC processors having 32 or more general-purpose registers.

It is a figure which shows schematic structure of the instruction area memory | storage part with which the data processor which concerns on one Embodiment of this invention is provided. It is a block diagram which shows schematic structure of the said data processor. It is a figure which shows the specific example of the associative search operation | movement in the said instruction area memory | storage part. FIG. 5B is a diagram showing another specific example of the associative search operation in the instruction section storage unit, and FIG. 6A is a diagram showing the associative search operation in FIG. is there. FIG. 4B is a diagram showing still another specific example of the associative search operation in the instruction section storage unit, and FIG. 4A is a diagram showing the associative search operation in FIG. It is. It is a figure which shows an example of the state where the function and the loop are nested. It is a figure which shows the influence range from which the register input / output of an inner structure turns into the register input / output of an outer structure in the nested structure of a function. It is a figure which shows schematic structure of RF and RB in a comparative example. It is a figure which shows the example of the search operation in a comparative example. FIG. 6A is a conceptual diagram conceptually showing a structure in which the function A calls the function B, and FIG. 6B is a memory in the main memory when executing the program structure shown in FIG. It is a figure which shows a map. It is a figure which shows the outline | summary of the argument and frame in a memory map when the function A calls the function B. It is a figure which shows the conventional reuse table for reusing one function.

Explanation of symbols

1A MSP
1B SSP
2 Command section storage (command section storage means)
3 Main memory (main memory means)
4A / 4B RW (first and second calculation means)
5A / 5B computing unit (first and second computing means)
6A ・ 6B Register 7A ・ 7B Cache

Claims (14)

In a data processing apparatus that reads a command section from a main storage means and performs a process of writing a result of arithmetic processing to the main storage means,
A first arithmetic unit that performs an operation based on an instruction section read from the main storage unit; a register used when reading and writing to the main storage unit by the first arithmetic unit; an input pattern for a plurality of instruction sections; Command section storage means for storing the output pattern,
When the first calculation means executes an instruction section, if the input pattern of the instruction section matches the input pattern stored in the instruction section storage means, the input section corresponds to the input pattern. Reuse processing for outputting the output pattern stored in the instruction section storage means to the register and / or main storage means,
The command section storage means includes an input pattern storage means for storing a plurality of the input patterns as a tree structure in which items to be matched are regarded as nodes ,
The input pattern storage means realizes the tree structure by storing the value of the item to be matched and compared in the input pattern in correspondence with the item to be compared next, and
The input pattern storage means includes an associative search means and an additional storage means,
The associative search means includes one or more search target lines each having a value storage area for storing a value of an item to be matched and a key storage area for storing a key for identifying the item,
The data processing apparatus , wherein the additional storage means has a search item designation area for storing an item to be subjected to an associative search next for each corresponding line corresponding to the search target line . 2. The data according to claim 1, wherein the additional storage means further includes a terminal presentation area for storing a terminal flag indicating that there is no item to be searched next for each corresponding line. Processing equipment. The additional storage means further includes a comparison required presentation area for storing a comparison required flag indicating that it is necessary to perform a value matching comparison for the item specified in the search item specifying area for each corresponding line. The data processing apparatus according to claim 1, wherein the data processing apparatus is a data processing apparatus. The additional storage means stores, for each of the corresponding lines, a comparison required item designating area indicating an item to be subjected to the next value matching comparison, and a comparison item for storing a key for identifying an item to be subjected to the next value matching comparison. The data processing apparatus according to claim 1, further comprising a key designation area . 5. The data processing apparatus according to claim 4, wherein the additional storage means further includes a parent node storage area indicating the search target line for which an associative search has been performed immediately before, for each corresponding line . In a data processing apparatus that reads a command section from a main storage means and performs a process of writing a result of arithmetic processing to the main storage means,
A first arithmetic unit that performs an operation based on an instruction section read from the main storage unit; a register used when reading and writing to the main storage unit by the first arithmetic unit; an input pattern for a plurality of instruction sections; Command section storage means for storing the output pattern,
When the first calculation means executes an instruction section, if the input pattern of the instruction section matches the input pattern stored in the instruction section storage means, the input section corresponds to the input pattern. Reuse processing for outputting the output pattern stored in the instruction section storage means to the register and / or main storage means,
The command section storage means stores each output pattern for each item to be output, and for each item to be output, information for specifying a position where an item to be output next is stored. First output pattern storage means,
The command section storage means further includes second output pattern storage means for storing items to be output in the output pattern in one-to-one correspondence with the plurality of input patterns.
The first output pattern storage means stores items that could not be stored in the second output pattern storage means . The command section storage means stores each output pattern for each item to be output, and for each item to be output, information for specifying a position where an item to be output next is stored. 6. The data processing apparatus according to claim 1, further comprising first output pattern storage means . The command section storage means further includes second output pattern storage means for storing items to be output in the output pattern in one-to-one correspondence with the plurality of input patterns.
8. A data processing apparatus according to claim 7, wherein said first output pattern storage means stores items that could not be stored in said second output pattern storage means . The input pattern is input to the main memory means at the time of execution of the program count value specifying the head of the instruction interval, the register input value input to the register when the instruction interval is executed, and / or the instruction interval. The main memory input value is included as the above item,
The output pattern includes a register output value output to the register during execution of the instruction section and / or a main storage output value output to the main storage means during execution of the instruction section as the item. The data processing device according to claim 1, wherein the data processing device is a data processing device. When the first arithmetic means executes the instruction section, the items of the input pattern of the instruction section are compared and compared according to the comparison order of the items in the input pattern stored in the input pattern storage means. Then, when an unmatched item appears, the calculation process is performed without performing the reuse process, and the unmatched item is registered in the input pattern storage unit, and the output pattern as the calculation process result is stored in the instruction section storage unit. The data processing apparatus according to any one of claims 1 to 5 and 7 to 9 . When the first calculation means detects that the value in the register or the main storage means has been changed, the item whose value has been changed is stored as an input pattern item in the input pattern storage means. 4. The data processing apparatus according to claim 3, wherein the additional storage means sets the comparison required flag as a comparison required for the item . At least one second computing means;
The second calculation means performs calculation of the instruction section based on a predicted input value that is expected to be input in the future with respect to the instruction section being processed by the first calculation means, and the result is used as the instruction section. The data processing apparatus according to any one of claims 1 to 11, wherein registration is performed with respect to the section storage unit . 13. A data processing program for causing a computer to execute a process performed by a first arithmetic means included in the data processing apparatus according to claim 1. A computer-readable recording medium on which the data processing program according to claim 13 is recorded.

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