JPH03147036A - Variable length data processor - Google Patents

Abstract

PURPOSE:To speed up the extraction processing or a record which fits a condition by executing the specific processing of data concerned in the setting of the condition, and the discrimination processing of a condition compatibility as to specified data in a process where word constitution data in respective variable length records are sequentially read one by one. CONSTITUTION:A comparator 44 compares a count value from a counter CNT with the number of digits from a comparison digit number register Ra. When they coincide, the comparator outputs the coincidence signal to a condition comparison circuit 43 as a comparison termination instruction signal. The condition comparison circuit 43 compares read data from a read data buffer Bu with a comparison word from a comparison word register Rc with the detection signal of a record start code from a delimiter detection circuit 42 as a comparison start instruction signal, and discriminates whether the compared result satisfies the condition from a condition setting register Rb. Then, the discriminated result is outputted to an address generation circuit 41.

Description

DETAILED DESCRIPTION OF THE INVENTION II. INDUSTRIAL APPLICATION FIELD The present invention relates to a processing device that processes variable length data divided by delimiter data such as delimiter coats.

[Summary of the Invention] The present invention provides a circuit for specifying data based on condition settings in a variable-length data processing device that extracts a record in which a predetermined word satisfies a predetermined condition from among a plurality of variable-length records. and a comparison circuit that determines whether the data specified by this circuit conforms to the conditions. There are 14 ways to quickly extract records that meet the conditions by being executed during the reading process.

[Prior Art] Conventionally, when extracting a record that satisfies a predetermined condition from among a large number of records, this has been achieved using software.

That is, if the record has a fixed length, (1) each code is read out repeatedly to determine whether the extraction conditions are satisfied.

(This was achieved by outputting records that satisfy the extraction conditions.

In addition, if the record is variable length, ■ Find the record delimiter code, ■ Extract one variable length record based on the found record delimiter code, ■ Check whether the extracted variable length record satisfies the extraction conditions. This was accomplished through the following steps: 1) If there is a variable-length code that satisfies the extraction conditions, output that variable-length record.

``Problem to be solved by the invention 1 In this way, in the case of variable-length records, the processing speed is lower than in the case of fixed-length records because the number of steps increases.''9 The reason for this is that This is due to the fact that the record identification process and the process of extracting records that match the extraction conditions can only be executed in chronological order. do.

Considering this, record identification processing is more strict; ÷ 4; if we can perform the identification processing of the data subject to judgment of compatibility with the extraction conditions and the record extraction processing in a 4L manner, it will be faster. It is clear that IA is applied.

An object of the present invention is to enable data identification processing for which extraction conditions are set and record extraction processing to be executed in an af=- row manner.

[Means to solve the problem J The means of this invention are as follows.

First storage means A (see function 11777 diagram in FIG. 1,
(the same applies hereinafter) stores a plurality of variable length records in which each record and each word in each record is separated by predetermined delimiter data.

The second storage means B stores the conditions of a predetermined word of the variable length record to be extracted from the first storage means A.

The readout circuit C continuously reads out the delimiter codes constituting each variable length code and each word configuration data of each word from the first storage means A one by one.

The detection circuit sequentially checks the data sequentially read out by the reading circuit C and detects word delimiter data related to condition setting.

The comparison circuit E compares the word configuration data of the word related to the condition setting read out subsequent to the delimiter data detected by the detection circuit with the condition stored in the second storage r-stage H.
Data! Compare at rank b.

When the conditions match as a result of the comparison by the comparator circuit H, the output means F sequentially outputs an i'if change record that includes the word in question. 9 Now, assume that the first storage means A stores a plurality of variable length records, each record separated by a record start code, and each word in each record separated by a word delimiter code. do.

In addition, the second storage means B stores keywords (2-digit decimal numerical data stored immediately after each record start code) of the variable-length record to be extracted from the first storage L stage A as a condition. , P25~h'' are stored.

In this state, the delimiter codes constituting each variable length 1° code and the word configuration data of each word are successively read out one by one by the reading circuit C from the first storage means A. Then, the detection circuit 1] sequentially checks the data and detects the record start code in order to determine the keyword related to the condition setting. That is, the reading process and the detection process I'1g are being carried out simultaneously and in parallel.

When the start code of record 1 is detected by the detection circuit E, the comparison circuit E stores the word configuration data of the keyword read out subsequently and the second storage stage B.
The conditions stored in the data are compared on a data-by-data basis. That is, first, the numerical data of the 10" digit read out first is compared with the numeric data "2" of the 10" digit of the condition 25 to L".

Then, the next read numerical data in the 1°° position is compared with the numerical data in the 5th place under the condition ``25 or more. ,
This is being carried out concurrently with the detection process.

Output means (7) outputs when the conditions match as a result of the comparison by the comparison circuit E, that is, the read keyword is "2".
If it is 525 or more words, variable-length records containing that keyword are sequentially output.9 This output process is also the above-mentioned read process and detection process.

In other words, the readout process, detection process, comparison process, and output process are also being performed at the same time in the process in which the readout process is being performed continuously without interruption. , the target record extraction process is also completed almost simultaneously with the completion of the continuous read process.

b, specifying data for which extraction conditions have been set,
Record extraction processing can be executed in parallel.

[Example] Hereinafter, an example will be described with reference to FIGS. 2 to 5.

C. FIG. 2 is a schematic block diagram of a variable length data processing device according to an embodiment.

This variable length data processing device is under the control of the CPUI.
Various data processing operations such as file processing are performed in the RAM 21 in variable length data format. When performing these processes, the local RAM 3 and the data extraction unit 4 are utilized to extract an IIR variable length record that satisfies the designated conditions from among the variable length records Y forming the file.

In a variable-length record format file, each variable-length record and variable-length word is separated by a delimiter code that indicates data separation. This delimiter code includes symbols such as "(°゛" shown in Figure 3, where "(" indicates the record start code and ° indicates the word end code. 9CP LJ 1 satisfies the above specified conditions. The file from which variable-length records are to be extracted is RAM2 or t)
Transfer to l''77-Cal RM 3 and develop.

The data extraction unit 4 executes the record extraction processing described above for the file expanded to 1 m in the local RAM 3.

The data extraction section 4 includes an address generation circuit 41, a read buffer B11-delimiter detection circuit 42, a condition comparison circuit 43, a counter CNT, a comparator 44, a comparison digit number register Ra, a condition register Rb, and a comparison word register Rc.
have.

The address generation circuit 41 generates an access address to access the variable length record data of the file developed in the local RAM 3. This access address is transferred to the local RAM 3 via the address bus AB.
The data in the address area is stored in the read buffer Bu via the data bus DB, and is output to the delimiter detection circuit 42 and the condition comparison circuit 43.

When the delimiter detection circuit 42 detects the record start code, it outputs a signal to that effect to the counter CN1' and the condition comparison circuit 43, and also outputs various delimiter codes to the address generation circuit 41. Then, the condition comparison circuit 43 starts a predetermined condition comparison process based on the record start code detection signal.

The counter CNT is reset by the detection signal of the record start code from the delimiter detection circuit 42, and for the next word, that is, the keyword, the number of data (
(number of digits, number of words), and compares the count value with comparator 4.
Output to 4.

In comparison digit number register Ra, condition register Rb, and comparison word register Rc, the number of comparison digits, condition, and comparison word are set respectively under the control of CPUI.1For example, the keyword is 2-digit decimal numerical data. 25 or more in case of
If you do not want to extract a record for the target keyword, use the key manual section (not shown) to set the number of digits for comparison to '2°' and the condition to 'co'.

, 25'' as the comparison word is set in the corresponding register under the control of c P LJ i. In other words, the number of comparison digits in the comparison digit number register Ra is output to the comparator 44. , condition register r(b, condition and comparison word in comparison word register Rc are output to condition comparison circuit 43.

Therefore, the comparator 44 compares the count value from the counter CN_T and the number of digits from the comparison digit number register Ra,
When a match occurs, the match signal is output to the condition comparison circuit 43 as a comparison end instruction signal. That is, the delimiter detection circuit 42, the ILI articulator '14, the counter CN'F,
and comparison digit number register 17;l performs processing for specifying keywords for which extraction conditions are set.

On the other hand, the condition comparison circuit 43 is connected to the delimiter detection circuit 42.
The read data from the read data bar Sofa Bu is compared with the comparison word from the comparison word register Rc using the detection signal of the record start coat from the buffer as a comparison start instruction signal, and the comparison result is stored in the condition setting register l
) is satisfied. And F
The JIj-specific results are output to the address generation circuit 41.

Based on this determination result, the address generation circuit 41 generates a write address in order to extract (write) only the record F that includes the keyword that satisfies the condition into a predetermined area of the local RAM 3. At this time, the write address registers WAI, ~■A2 are utilized. In addition, when reading, use read address register F (A).
The address generation circuit 41 starts generating an address based on the instruction from the CP LJ 1, and the delimiter detection circuit /'
12, address generation is stopped when a delimiter detection signal is desired to be input for a predetermined period of time or more.

Data access processing by the address generation circuit 4I,
Delimiter detection circuit 42, comparator 44'! ! The process of specifying a keyword for which an extraction condition has been set, the process of checking the suitability of the extraction condition, etc. by F are executed simultaneously in parallel.

Next, the operation of the embodiment will be specifically explained with reference to FIGS. 3 to 5.

Currently, variable length record data as shown in FIG. 3(a) is stored in the local RAM 3.

As shown in FIG. 4, the comparison digit number register Ra, condition register Rb, and comparison word register Rc each contain the comparison digit number "" in order to extract records with keywords of 25 or more.
2", the condition "≧", and the comparison word "25"° are set. Note that the numbers outside the frame in FIG. 3 indicate addresses on the local RAMB, and in FIG. 3(a) they mean read addresses and in FIG. 3(b) they mean write addresses. is generated and set in the read address register RA or single address ''
Based on 0°°, 1 cocal F? The record start code "(") is read from A M 3 and stored in the read buffer Bu (see Figure 5 "a" and "b", Figure 3)
, At this time, the comparison start instruction signal is 1?1 when the limiter is detected.
Conditional comparison times fl from 2? It is output to f43. Also, the write address is 100°.

is saved in the write address register WAI and the write address register WA2 (see "C" in FIG. 5).

Then, at the next read address “1”, the actual data “2”° is read.
is read out and stored in the read buffer Bu (see FIG. 5, "°d, e", and FIG. 3).The condition comparison circuit 43 then starts comparison processing based on the comparison start instruction signal.

That is, the condition comparison circuit 43 compares the third digit "2" of the comparison word "25" inputted through the read buffer Bu and the comparison word "25" from the comparison word register Rc.
° and determines whether the condition ゛≧°゛ from the condition register Rb is satisfied (see "e" and "f" in Figure 5). In this case, since the conditions match, the condition comparison circuit 4
3 outputs a match signal to the address generation circuit 41. Then, in the next write period, the address generation circuit 41
Generates the next write address "°101°" and sets it in the write address register WAI (see Figure 5 "g"). The lower digit ``5'' of ``25'' is compared, but the lower digit ``5'' does not satisfy the condition ``≧°'', so the condition comparison circuit 43 sends a mismatch signal to the address generation circuit 41. Then, in the next write period, the address generation circuit 41 outputs the write address that has been saved in the write address register WA2. The address "100" is not returned to the write address register WAI (see "k" in FIG. 5).

In this embodiment, since the extraction condition is set only for the keyword next to the record start code, the write address is not updated until the next record start code is read, and the write address is returned to the write address register WAI. The write address "t o o" is in a locked state (see Figure 5 °''!°').

Then, when the next record start code is read by the read address "10°", it is written to the locked write address "100", and the write address "100°" is transferred from the write address register WAI to the write address register. It is saved to WA2 (see "rnnO" in Figure 5).

The next leading keyword “” 28 ” has the comparison word “°” in both the upper digit (tens digit) and lower digit (1s digit).
The value is greater than or equal to the value of each digit of 25°°, and the comparison condition “≧
Since °゛ is satisfied, the upper digit "2" of the keyword "28"
", when the lower digit "8" is read, the condition comparison circuit 43 outputs a match signal, so the write address is not locked as described above, and each data of the record is The record start code is sequentially written to addresses after the written write address ゛°100°°.

In other words, when a keyword that does not satisfy the extraction conditions is read, the write address is fixed to the write address of the current record start code, and the extraction is performed by writing the next record start code to the fixed write address. Only records containing keywords that satisfy the conditions are written into a predetermined area of the local RAM 3.

Although not shown in Figure 5, the keyword “1”
If the numerical value in the digit ``0'' is not equal to ``2°,'' it is obvious that the extraction condition of 2525 or more cannot be added, so the comparison process in the digit ``l'' is omitted and the above Handling the case of mismatch.

As is clear from the above explanation and FIG. 5, processing for accessing variable length data, processing for identifying keywords for which extraction conditions have been set, processing for comparing and detecting matches between the keywords and extraction conditions, and keywords that satisfy the extraction conditions. The processing for extracting records containing keywords that satisfy the extraction conditions is all executed in parallel.In other words, when the reading of variable-length data from the local RAMB is completed, the processing for extracting records containing keywords that satisfy the extraction conditions is almost complete. They are completed simultaneously, achieving high-speed processing. Furthermore, since it is implemented using hardware, speed-up is achieved in that respect as well.

Note that the present invention is not limited to the above-mentioned embodiments, and for example, 5000
When the extraction condition “°゛” is set, “
It is also possible to further speed up the comparison by comparing only part of the word, such as comparing only numerical data in the digit ``1000''.Also, if the extraction condition is ``'1''
000°'' and the word to be set is a variable length word, the suitability of the extraction condition can also be checked based on the number of digits.

In addition, the word for which the extraction conditions are set may be any word in the second record, multiple words, or data types other than numerical values. Counter register, r?b/condition register, Rc, . . . comparison register.

[Effects of the Invention] According to the present invention, the process of specifying data for which extraction conditions have been set and the record extraction process can be executed in parallel, and even if the record format is variable length, the extraction conditions can be met at high speed. Records can be extracted quickly.

1-7 applicant Casio Computer Co., Ltd.

[Brief explanation of the drawing]

Fig. 1 is a functional diagram of the present invention, Fig. 2 is a block diagram of the embodiment, Fig. 3 is an IA showing an example of data in the local RAM, Fig. 4 is a diagram illustrating extraction conditions, Fig. 5 The figure is a time chart showing the extraction operation corresponding to FIGS. 3 and 4. 3...Local RAM, 4...-Data detection unit, 41
--Address generation circuit, 42...Data detection circuit,
Figure 4 ((L) (b) Figure 4

Claims (1)

[Claims] A first storage means for storing a plurality of variable length records in which each record and each word in each record are separated by predetermined delimiter data; a second storage means for storing the conditions of a predetermined word of the variable length record to be stored; and a second storage means for storing the conditions of a predetermined word of the variable length record;
A readout circuit that sequentially reads data one by one, a detection circuit that sequentially checks the data read out sequentially by this readout circuit and detects word delimiter data related to condition setting, and a comparison circuit that compares the word configuration data of the word related to the condition setting read out subsequent to the delimited data with the conditions stored in the second storage means in units of data; and the results of the comparison by the comparison circuit; When the conditions match,
A variable length data processing device comprising: output means for sequentially outputting variable length records including the word.