JPH02133831A - Error information storing circuit - Google Patents

Abstract

PURPOSE:To store many syndrome signals with no omission by comparing a newly produced syndrome signal with all syndrome signals which are already stored and storing the new syndrome signal only when no coincidence is obtained from the comparison. CONSTITUTION:A syndrome signal 103 is set at a syndrome register 4 via a bit error signal 102. The read signals 107 which are successively read out of a register file 6 storing the signal 103 are compared with the signal 103 of the register 4 via a comparator 7. When no coincidence is obtained from this comparison, a coincidence register 8 outputs logic '1'. Then an AND gate circuit 9 secures an AND between the output signal of the register 8 and a carry signal 104 (logic '1'). When the logic '1' is secured as a result, an instruction is given to the file 6 to write the signal 103 of the register 104 into the address position which is designated by a write address counter 10. In such a manner, many syndrome signals can be stored with no omission.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used in an error information storage circuit of a storage device, and in particular, when a 1-bit error occurs in read data, a syndrome signal for pointing out the error bit position is stored. The present invention relates to an error information storage circuit for a storage device.

〔overview〕

The present invention provides an error information storage circuit for a storage device that includes a bit error detection circuit that detects a bit error and outputs a bit error signal and a syndrome signal related to the bit position, including syndrome storage means for storing the syndrome signal. The syndrome signal is stored in the syndrome storage means by comparing all the newly generated syndrome signals with the already stored syndrome signals, and if they are different, storing a new one. The syndrome signal can be stored without exception.

[Conventional technology]

Conventionally, when a 1-bit error occurs in read data, this type of storage device stores and holds a syndrome signal indicating the error bit position in a syndrome register, and sends a bit error signal indicating the occurrence of a 1-bit error to a diagnostic device. do.

The diagnostic device that receives this bit error signal reads out the contents of the syndrome register in the storage device and stores it in a storage area within the diagnostic device. When the storage is completed, the syndrome register in the storage device is reset, and the storage device can reset the newly generated 1-bit error in the syndrome register. The cycle shown above is repeatedly executed, and in a typical computer system, the cycle is repeated once every several hours.

[The problem that the invention attempts to solve.

Therefore, in the conventional error information storage circuit described above, a new 1-bit error occurs during several hours after detecting a 1-bit error and storing the syndrome signal in the syndrome register until the syndrome register is reset. However, the drawback is that the syndrome signal cannot be maintained.

An object of the present invention is to provide an error information storage circuit that can store many syndrome signals without exception by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides an error information storage circuit for a storage device including a bit error detection circuit that detects a bit error and outputs a bit error signal and a syndrome signal related to the bit error, comprising means for storing the syndrome signal; The storage of the syndrome signal in the storage means is characterized by comprising means for comparing all of the randomly generated signals with already stored syndrome signals and, if different, storing the syndrome signal anew.

A third error information storage circuit of the present invention includes a register file of n words (n is a natural number) that stores the syndrome signal, and a readout device that sequentially outputs read addresses of the register file starting from address 0 using the bit error signal as a trigger. an address counter, a write address counter that outputs a write address of the register file, a syndrome register that takes in the syndrome signal in response to the bit error signal, a read signal that is sequentially read out from the register file according to the read address, and the syndrome register. a comparison circuit that compares the syndrome signal taken in and outputs a match signal when they match; a match register that captures and holds the match signal;
The carry signal output when the read address counter counts up to the final address and the complement output of the match register are input, and when both signals are significant, the register file is loaded into the syndrome register. a gate circuit that outputs a write signal for writing a syndrome signal; and a gate circuit that receives the write signal as input, monitors the write to the register file, and after the write operation is completed, resets the syndrome register and increments the write address counter by +1. It is also possible to include a write monitoring register that outputs an operation end signal.

Further, the second error information storage circuit of the present invention compares the syndrome signal and the output signal of each syndrome register with n syndrome registers each storing the syndrome signal and the output signal of each syndrome register. n comparison circuits each outputting a match signal at the same time; n counters each connected to the output of each comparison circuit and counting up each time the match signal is output; The syndrome signal and the mismatch signal are inputted to a gate circuit that outputs a mismatch signal when the match signal is not output as an input, and to each syndrome register using the bit error signal and the mismatch signal as inputs. and a set signal generation circuit that outputs set signals that are sequentially shifted for each set signal.

[Effect]

In the first error information storage circuit of the present invention, an n-word register file is provided to store the generated syndrome signal, and the syndrome signal is stored in this register file, and the newly generated syndrome signal is read out from the stored syndrome signal. The comparison circuit compares the syndrome signal with the syndrome signal read out according to the read address indicated by the counter, and only if they do not match, the signal is stored in a new address location indicated by the write address counter.

In addition, in the second error information storage circuit of the present invention, n syndrome registers are provided for storing generated syndrome signals, and the newly generated syndrome signal and the output signal of each syndrome register are respectively detected by respective comparison circuits. The comparison is made, and only if they do not match, an instruction is given by a set signal from the set signal generation circuit, and the syndrome signal is stored in the next syndrome register in which the syndrome signal is not yet stored.

Therefore, since the stored syndrome signals are not duplicated, the storage capacity of the storage means is small, and storage of the syndrome signals can be controlled at high speed within the storage device without using a diagnostic device, and error information can be It becomes possible to store everything without exception.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The present embodiment detects a bit error and generates a bit error signal 102 and a syndrome signal 103 indicating the bit position.
In an error information storage circuit of a storage device equipped with a bit error detection circuit 3 that outputs a syndrome signal 103
a register file 6 of n words (n is a natural number) that stores , a read address counter 5 that sequentially outputs read addresses 105 of the register file 6 from address 0 using the bit error signal 102 as a trigger, and a register file 6.
A write address counter 10 outputs a write address 106, a syndrome register 4 receives a syndrome signal 103 according to a bit error signal 102, a read signal 107 is read out sequentially from a register file 6 according to a read address 105, and a syndrome register 4 receives a comparison circuit 7 which outputs a match signal 108 when the syndrome signal 103 is compared with the syndrome signal 103, a match register 8 which captures and holds the match signal 108, and a carry signal which is output when the read address counter 5 counts up to the final address. An AND gate that receives the signal 104 and the complement output of the match register 8 as input, and outputs a write signal 109 for writing the syndrome signal 103 taken into the syndrome register 4 to the register file 6 when both signals are significant. A circuit 9 and a write monitoring register which inputs a write signal 109, monitors the writing of the register file 6, and outputs a write operation end signal 110 which resets the syndrome register 4 and causes the write address counter 10 to count up by +1 after the write operation is completed. 11. In FIG. 1, 1 is a memory array and 2 is a read data register that stores read data 101 thereof.

The features of the present invention are as shown in FIG.
, comparison circuit 7, match register 8, AND gate circuit 9,
This is because a write address counter lO1 and a write monitoring register 11 are provided.

Next, the operation of the present embodiment will be explained.

The read data read from the memory array 1 is stored in the read data register 2, and the bit error detection circuit 3 performs an error check on the read data. When a 1-bit error is detected, a bit indicating the existence of a 1-bit error is detected. Error signal 102 and syndrome signal 10 indicating error bit position
Outputs 3.

A syndrome signal 103 is set and held in the syndrome register 4 by the bit error signal 102.

Further, due to the bit error signal 102, the read address counter 5 is set from address 0 to address (n-1) (register file 6
It starts counting up sequentially up to the number of words) and sequentially designates and outputs read addresses 105 to the register file 6.

A read signal 107 is sequentially outputted from the register file 6 according to the read address 105. In this case, since the syndrome signal 103 is not stored in the register file 6, the read signal 107 is all "0" for all address positions. The read signal 107 read out sequentially from the register file 6 is compared with the syndrome signal 103 of the syndrome register 4 by the comparison circuit 7, and if they match, a match signal (logic "1") is output. In this case, since they do not match, no match signal is output.

The match register 8 that has received the match signal outputs a complement signal to the AND gate circuit 9.

If there is no match in the comparison circuit 7, the output of the match register 8 becomes logic "1". On the other hand, the read address counter 5 is
After counting up the read address 105 to address (n-1), the carry signal (logical 'I J) 104
, returns itself to address 0, and temporarily stops counting up until the next bit error signal 102 is received.

The AND gate circuit 9 performs a logical product of the output signal (logic "1") of the match register 8 and the carry signal (logic "1") 104, and if the result is logic "1", writes the write address to the register file 6. The syndrome signal 103 held by the syndrome register 4 is instructed to be written to the address position specified by the counter 10 (address 0 because it is in the initial state). That is, if the comparison result of the comparison circuit 7 does not match, writing is performed, and if they match, writing is inhibited.

In addition, a write signal 109 output from the AND gate circuit 9
After the write operation is completed, the write monitoring register 11, which receives this and monitors the write cycle of the register file 3, resets the syndrome register 4 and at the same time outputs a write end signal 110 that instructs the write address counter 10 to count up the address by +1. do.

With the above explanation, storage of the first syndrome signal 103 is completed. The syndrome signal 103 for the second and subsequent 1-bit errors is compared with the previously written contents of the register file 6, and if they do not match, the syndrome signal 103 is written to the next address of the register file 6.

Further, as in the past, the diagnostic device periodically reads the register file in the storage device, for example, once every few hours, stores it in a storage area in the diagnostic device, and provides it to a maintenance person as necessary.

As explained above, this embodiment has a register file of multiple words that stores a syndrome signal indicating the error bit position when a 1-bit error occurs, and the syndrome signal detected after the second one is previously written. By using a method that compares all the syndrome signals in the registered register file and writes to a different address than the previous one if they do not match, the register file can be configured with a small number of words, and it can be written inside the storage device without going through a diagnostic device. Since the storage of error signals (syndrome signals) can be controlled at high speed, more information can be stored without omission.

FIG. 2 is a block diagram showing a second embodiment of the present invention.
A case is shown in which there are two sets of syndrome registers.

The second embodiment includes two syndrome registers 12 and 13 each storing a syndrome signal 103;
Syndrome signal 103 and each syndrome register 1
Comparing circuits 14 and 15 simultaneously output match signals 112 and 113, respectively, when the output signals of 2 and 13 match, and are connected to the outputs of each of the comparison circuits 14 and 15 to output match signals 112 and 113, respectively. Two counters 16 and 17 count up each time 113 is output, and a NOR gate receives the outputs of the comparison circuits 14 and 15, respectively, and outputs a mismatch signal 114 when there is no match signal 112 and/or 113 output. circuit 18 and bit error signal 102
Syndrome signal 103 is input to each syndrome register 12 and 13 by inputting
and a set signal generation circuit 22 that outputs set signals 115 and 116, respectively, which sequentially shift the data each time the mismatch signal 114 is input. The set signal generation circuit 22 includes an AND gate circuit 19 that receives the bit error signal 102 and the mismatch signal 114 and performs a logical product thereof, a mismatch register 20 that inputs and stores the mismatch signal 114, and an AND gate circuit. 19, and a decoding circuit 21 that decodes the contents of the mismatch register 20 using the output of 19 and outputs set signals 115 and 116. Note that the syndrome register 12, the comparison circuit 14, and the counter 16 constitute a first block, and the syndrome register 13, the comparison circuit 15, and the counter 17 constitute a second block.

A feature of the present invention is that, in FIG. This is because a set signal generation circuit 22 is provided.

Next, the operation of the second embodiment will be explained.

Read data read from memory array 1 is stored in read data register 2, and a bit error detection circuit 3 checks for errors in the read data. When a 1-bit error is detected, a bit error signal 102 and a syndrome signal 103 indicating the error bit position are output.

Syndrome signal 103 is input to first syndrome register 12, second syndrome register 13, first comparison circuit 14, and second comparison circuit 15, respectively. In the initial state, syndrome registers 12 and 13 and comparison circuits 13 and 14 are all "0".
It has been reset to .

When the syndrome signal 103 is input to each block,
The first comparison circuit 14 is connected to the first syndrome register 12.
(in this case "0") data and the syndrome signal from the bit error detection circuit 3 are compared, and if they match, a match signal (logic r I J 012 is outputted and the first counter 1
6 counts +1. Thereafter, the second comparator circuit 15 also compares in the same way, and if they match, the 20th counter 17 counts +1. In the initial state, all comparison circuits 14 and 15
Since the match signals 112 and 113 do not match, the match signals 112 and 113
are all logical "0".

Nant gate circuit 18 connects all coincidence signals 14 and 1
Input 5 and perform a negative OR. In this case, the mismatch signal 114, which is the output signal of the Nant gate circuit 18, is a logic "1".
Then, the AND gate circuit 19 outputs the bit error signal 102.
If the result is logical rl-,L, the decode circuit 21 decodes the contents of the mismatch register 20. In the initial state, the mismatch register 20 is “0”
Therefore, the output of the decoding circuit 21 generates a set signal 115 only to the syndrome register 12. The first syndrome register 12 that has received the set signal 115 captures and holds the syndrome signal 102 output from the bit error detection circuit 3. At the same time, mismatch register 20 receives a logic "0" mismatch signal 114 from Nants gate circuit 18.

Note that in an error information storage circuit having a plurality of syndrome registers, the mismatch register 20 is connected to the NOR gate circuit 18.
The counter may be configured to count when the output becomes logic "0".

Next, a case will be described in which a 1-bit error newly occurs and the syndrome signal 103 is the same as the first syndrome signal 103, that is, the error bit position is the same. In this case, the first comparison circuit 14 generates a coincidence signal 112 and causes the first 0 counter 16 to count +1. Also, match signal 1
12 becomes logic "1", the output of NOR gate circuit 18 becomes logic "0" and mismatch register 20 and decoding circuit 21 do not operate.

Next, a case will be described in which a third one-bit error occurs and its syndrome signal is different from the first and second syndrome signals. In this case, since the first and second comparison circuits 14 and 15 do not match, the match signals 112 and 113 both become logic "0", and the mismatch signal 114 from the NOR gate circuit 18 becomes logic "1" and the mismatch register 20 And the decoding circuit 21 operates. Since the mismatch register 20 is already at logic “1”, the decoding circuit 21 sends the set signal 116 to the second syndrome register 13. The second syndrome register 13 that has received the set signal 116 captures and holds the third syndrome signal 102 output from the bit error detection circuit 3.

Also, as in the past, the diagnostic device periodically reads out the syndrome register and counter in the storage device, for example, once every few hours, stores it in the storage area of the diagnostic device, and provides it to maintenance personnel as necessary. .

As explained above, the second embodiment has a plurality of syndrome registers that store syndrome signals indicating the error bit position when a 1-bit error occurs, and stores a newly generated syndrome signal into an already stored syndrome signal. By using a method that compares all syndrome signals and counts the number of occurrences if they match, and stores a new syndrome signal in another syndrome register if they do not match, it can be configured with fewer syndrome registers, and moreover, it can be configured with a small number of syndrome registers without using a diagnostic device. Since the storage of error signals (syndrome signals) can be controlled internally at high speed, more information can be stored without omission.

〔Effect of the invention〕

As explained above, the present invention provides a syndrome storage means for storing a syndrome signal, and stores the syndrome signal in the syndrome storage means so that a newly generated syndrome signal can be stored in all the syndrome signals that have already been stored. By newly storing the syndrome signal only when there is a difference, the scale of the syndrome storage means can be reduced, and the syndrome signal can be stored at high speed within the storage device without using a diagnostic device. This has the effect of being able to store a lot of error information without exception.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a block diagram showing a second embodiment of the present invention. 1... Memory array, 2... Read data register, 3... Bit error detection circuit, 4.12.13...
Syndrome register, 5... Read address counter, 6... Register file, 7.14.15...
Comparison circuit, 8... Match register, 9.19... AND gate circuit, 10... Write address counter, 1
1... Write monitoring register, 16.17... Counter, 18... NOR gate circuit, 20... Mismatch register, 21... Decode circuit, 101... Read data, 102... Bit error Signal, 103...Syndrome signal, 104...Carry signal, 105...
・Read address, 106...Write address, 10
7... Read signal, 108.112.113... Match signal, 109... Write signal, 110... Write end signal, 114... Mismatch signal, 115.116...
...Set signal.

Claims (1)

[Scope of Claims] 1. In an error information storage circuit of a storage device including a bit error detection circuit that detects a bit error and outputs a bit error signal and a syndrome signal related to the bit position, the syndrome signal is stored. a register file of n words (n is a natural number); a read address counter that uses the bit error signal as a trigger to sequentially output read addresses of the register file starting from address 0; and a write address counter that outputs write addresses of the register file. , a syndrome register that captures the syndrome signal based on the bit error signal, and a syndrome register that compares the read signal sequentially read from the register file according to the read address with the syndrome signal captured in the syndrome register, and outputs a match signal when they match. a match register that captures and holds the match signal, and a carry signal output when the read address counter counts up to the final address and a complement output of the match register as inputs, and both signals are significant. a gate circuit that outputs a write signal to write the syndrome signal taken into the syndrome register to the register file when An error information storage circuit comprising: a write monitoring register that outputs a write operation end signal that resets the syndrome register and causes the write address counter to count up by +1 address. 2. In an error information storage circuit of a storage device equipped with a bit error detection circuit that detects a bit error and outputs a bit error signal and a syndrome signal related to the bit position, n pieces (n is comparing the syndrome signal with the output signal of each syndrome register (a natural number), and outputting a match signal at the same time if they match;
n counters each connected to the output of each comparison circuit and counting up each time the coincidence signal is output; a gate circuit that outputs a mismatch signal if the bit error signal and the mismatch signal are not present, and a set signal that receives the bit error signal and the mismatch signal and sequentially shifts the syndrome signal to each of the syndrome registers each time the mismatch signal is input. An error information storage circuit comprising: a set signal generation circuit that outputs each set signal.