SU1566411A1 - Logic memory device - Google Patents

Abstract

The invention relates to computing and can be used in systems of complex logical information processing. The purpose of the invention is to expand the functionality of the device by ensuring that the original form of the array of information recorded in a compressed form is read. The device contains memory block 1, address multiplexer 14, bit number register 15, first 31, second 18 and third 21 counters, address shaper 27, priority block 41, array information analysis unit 42, first 46 and second 51 shift registers, block 50 priority encoders, priority encoder 55, block 56 controls. Memory block 1 contains a block 2 write-read column, input 5 and output 37 word registers, blocks of amplifiers read column 7 and row 36, register 8 columns, block 10 write-read lines, address decoder 13, block 39 search for groups of units. 2 Il.

Description

T |, r «u I« J § |

| Dms ptmvn

0uil

0uil

31. The second 18 and third 21 counters, the address driver 27, the priority block 41, the array information analysis block 42, the first 46 and second 51 shift registers, the priority encoder block 50, the priority encoder 55, the control block 56. Memory block 1 contains a block 2 write-read column, input 5 and output 37 word registers, blocks of amplifiers read column 7 and row 36, register 8 columns, block 10 write-read lines, address decoder 13, block 39 search for groups of units. 2 Il.

The invention relates to computing and can be used in systems of complex logical data processing.

The purpose of the invention is to expand the functionality of the device by ensuring that the original form of the array of information recorded in a compressed form is read.

Figure 1 shows the functional diagram of the logical storage device; figure 2 - the initial array (a), the compressed array (b) and the placement of information in the drive (C).

The device contains (Fig. 1) memory block 1, which includes a column write-read block 2 with a column read input 3 and a column write input 4, a word input register 5 with information input 6, a column read amplifier section 7, a column register 8 with input 9 reset, block 10 write-read line with input 11 read line and input 12 write line, the decoder address 13. The device also contains an address multiplexer 14, a bit number register 15 with reset inputs 16 and entries 17, a second counter 18 with summing input 19 and initial setup input 20, a third counter 21 with information receiving permission input 22, summing input 23 and subtracting input 24 , block 25 compared with output 25 Completion of the analysis of the stack words, address driver 27 with control input 28, device address input 29 and indicator output 30, first counter 31 with totaling input 32, subtractive input 33, initial installation input 34 and output 35 Gras Itza stack. The memory unit 1 also contains a string reading amplifier section 36, a word output register 37, a drive 38, a unit group search unit 39 with an output of 40.

The device also contains a priority block 41, an array information analysis block 42 with outputs 43 to 45, a first shift register 46 with a reset input 47, a recording input 48 and a shift input 49, a priority encoder block 50, a second shift register 51 with a reset input 52, the input 53 of entry and the input 54 of the shift, the priority encoder 55, block 56 control.

The device works as follows.

During the operation of the device, the N first words (rows) of the accumulator 38 capable of being read and written in rows and columns are used to store

arrays of information whose length does not exceed N. The following (last) 0.75 n words of accumulator 38, which allow reading and writing of information only in rows, are used as a stack area,

moreover, the n-bitness of words (lines) stored in the accumulator, i.e. number of columns.

In the initial state of the device in the accumulator 38 a compressed (compressed) array of information is recorded, in which

matching columns, as well as information about matching columns, is located in the stack area. Moreover, each word of the stack contains more than one unit and indicates a certain group of coincident columns.

the original array, which is indicated by the positions of the units of the stack word, which are located in the bits corresponding to the matching columns.

The initial array (Fig. 2a) consists of five six-bit words, with the first (left) and third columns and the second, fifth and sixth columns coinciding with the array. Therefore, the compressed array (Fig.26) contains only three columns: by

one for each group and unmatched with any of the other column (the fourth in the original array).

The corresponding placement of information in the drive 38 is shown in

figv. The first words of the accumulator are occupied by a compacted array, and the contents of columns with numbers 0, 1, and 2 (the numbering starts from zero and goes from right to left) is indifferent. Last four

words (0.75 n, where bits) the accumulator occupies the stack area, in which the first two lines contain information about matching groups, two units in the first word of the stack are located in the bits corresponding to the left and third (left)

columns of the original array, and indicate the coincidence of these columns, similarly, and the second word of the stack contains three units in the bits corresponding to the matching columns of the second group. The state of the last two words of the stack is indifferent.

In Fig. 2b, the arrows also show the stack word whose address is set in the counter 31, and the rightmost column (lower boundary) of the compressed array, the address (number) of which is stored in the shaper 27, at the time the compression operation of the original array is completed. This moment is taken as the initial state of the proposed device.

Restoration of the original form of the array occurs in two stages. At the first stage, the initial array columns are restored to the original array that did not coincide with any other columns, as well as the first (supporting) columns of each group (since they could also be shifted during compaction). In the second stage, the remaining columns are restored to the original positions.

The first step is to obtain in the register 46 stack information a word equal to the disjunction of all the stack words with zero left bits, which is accomplished by alternately reading the stack words to the output register 37 words with their subsequent transfer to the register 46 through block 41. gas left units (bars 1–5, described below). Then alternately shifting the contents of register 46 are viewed, starting from the right, all bits of the resulting disjunction. Moreover, the zero values of bits indicate mismatched columns or reference columns of groups. These columns are read from the compressed array and written into their original places (bars 6-11).

The implementation of the second stage consists in alternately reading the stack words to register 51 and comparing these words with their previously obtained disjunction stored in register 46 (after the first stage, the contents of register 46 take the original form, since the shift in it is cyclic). At the same time, when the values of the bits 00, 01 and 10 being compared, indicating that the columns corresponding to the analyzed bits have already been restored, the contents of the registers 46 and 51 shift to the right and the next pair of bits is analyzed. If the pair of bits has a value of 11, then the reference column of the group recorded at the address of the leftmost unit in the stack word entered in register 51 is restored by overwriting the original place corresponding to the bit being analyzed (cycles 12-20).

The procedure for restoring the original array includes the following measures.

First beat The input 33 of the counter 31 from block 56 is supplied with a control signal,

As a result, it sets the address code of the word that was last written to the stack (since, after completing the compacting operation of the array of information, counter 31 is set to the address code following

5 address of the last word written to the stack).

Second beat A signal is sent from block 56 to line 11 input 11, resulting in the output register 37 of the word entering the word read at the address set in the counter 31 of the stack pointer.

The third beat. A signal is sent from block 56 to input 48 of the input of information that

5 results in the transfer of a word from register 37 to register 46, in the process of which the high order (left) unit of the transmitted word is zeroed by block 41.

Speed limit A signal is sent from block 56 to the reset input, as a result of which register 37 is cleared.

Fifth cycle Analyzed by block 56 the signal at the output 35 of the counter 31. The presence of a unit at this output indicates

5 that the last word was read from the stack. In this case, the transition to the sixth clock cycle is performed, otherwise to the first one.

The sixth beat. Signal from unit

0 56 to the input 34 of the initial setup, as a result of which the counter 31 is set to the address code of the word written to the stack last. At the same time, signals from input 56 for information reception and input 20 of the initial installation are sent from block 56, as a result of which counter 18 is reset to zero, and the address of the lower (right) boundary of the compressed array is transmitted to counter 21 from the former 27.

0

Seventh beat. The signal at output 43 of block 42 is analyzed by block 56. The single value of the signal at this output, generated when a zero signal from the lower (right) bit of register 46 arrives at block 42, corresponds to a column of the original array that does not coincide with one of the groups (left a) group column. In this case, the transition to the eighth clock cycle is performed, and at the zero signal at output 43, to the tenth clock cycle.

The eighth beat. A signal is sent from block 56 to input 3, as a result of which the register of column 8 from accumulator 38 reads the column whose address is set on counter 21.

Ninth time. A signal is sent from block 56 to input 4, as a result of which the drive 38 records the contents of register 8 of a column whose address is set on counter 18. At the same time, a signal is sent to input 23, as a result of which the contents of counter 21 are increased by one.

The tenth beat. The signals are input to the input 49 of the shift register 46 and the input 19 of the counter 18, as a result of which the contents of the register 46 are shifted (cyclically) to the right by one bit, and the contents of the counter 18 are incremented by one.

Eleventh bar. The signal at output 26 is analyzed by block 56. At a single value of the signal at this output, generated if the contents of counter 18 coincide with the contents of counter 21, the transition to the twelfth clock cycle is performed, otherwise to the seventh clock cycle.

As a result of the sixth-eleventh clock cycles, the columns of the original array, which did not coincide with one of the columns, as well as the leftmost (supporting) columns of all groups of coinciding columns, were restored in their places in the accumulator 38.

The twelfth beat. The word is read from the stack to register 37, which is produced in the same way as in the second cycle. At the same time, from block 56, signals are sent to the reset inputs 9 and the initial installation 20, which nullify the register of the 8th column and the counter 18.

Thirteenth time. A signal is fed from block 56 to the input 53 of entering information, as a result of which the word read in the previous cycle is transferred to register 51 from register 37.

Fourteenth tact. A signal is fed from block 56 to the input 17 of entry, with the result that from the output of the priority encoder 55 to register 15 the number of the most senior (left) bit of register 51 containing one is entered. Simultaneously, from block 56, a signal is supplied to the reset input, which resets the register 37 (the zero input of the register 37 is not shown).

Fifteenth cycle. Block 56 analyzes the signal at output 44 of block 42. The single value of the signal at this output, generated when entering block 42 of the lower bits of registers 46 and 51 of any combination of values except two units, corresponds to those cases when accumulator 38 is missing in groups matching columns, determined by the analyzed bit of the word of the stack read in the twelfth cycle, or by the already restored columns. With a single value

the signal at output 44 goes to the nineteenth cycle, otherwise, to the sixteenth.

The sixteenth cycle. Block 56 analyzes the signal at output 45 of block 42.

0 The single value of the signal at this output, generated when single signals from the lower bits of registers 46 and 51 arrive at block 42, corresponds to the fact that in drive 38 there is a group of matching columns defined by single bits of the stack word read to register 51 In such a case, the transition to the seventeenth clock cycle is performed, otherwise the operation of the device is completed by

0 crashing.

The seventeenth beat. A signal is sent from block 56 to input 3, as a result of which the register of column 8 from accumulator 38 reads a column whose address is set

5 on the register 15.

The eighteenth beat. A signal is sent from block 56 to input 4. As a result, the contents of register 8 are written to drive 38 in a column whose address is set on counter 18.

Virgo thirteenth time. A signal is fed from block 56 to input 19, increasing the content of counter 18 by one. At the same time, signals are sent from block 56 to

5, the shift inputs 49 and 54, which causes the contents of the registers 46 and 51 to be shifted one bit to the right, and the shift in register 46 is cyclic.

Twentieth beat. If the content of the counter is equal to 18 and the number of word bits of the accumulator 38, the transition to the twenty first cycle takes place. Otherwise - to the nth step.

5 As a result of execution of the twelfth - twentieth clock cycles in the drive 38, the columns of the initial array of the coinciding group of columns defined by the single bits of the word located on register 51 are restored in their places.

Twenty-first tact. Block 56 analyzes the signal at the output 35 of the counter 31. The presence of a unit at this output indicates

5 that the last word was read from the stack, which indicates the completion of the restore operation of the original array in drive 38. Otherwise, a signal is fed to the input 33 of the counter 31 and the transition to the twelfth cycle is performed. Next, the twelfth to twenty-first cycles are repeated until the procedure is completed (i.e., until a single signal appears at output 35).

Claims (1)

Invention Formula Logical memory containing a memory block, a first counter, an address multiplexer, a priority block, an address builder, a first shift register, a priority encoder block, and a control block, the information input of the memory block being the information input of the device, the first output of the memory block connected to the input of the priority block is the information output of the device, the address input of the memory block is connected to the output of the multiplexer, the first information input of which is connected to the output of the address generator Ca, the second information input of the address multiplexer is connected to the first output of the first counter, the first information input of the address former is connected to the output of the priority encoder block whose input is connected to the output of the first shift register, the second information input of the address former is the address input of the device, the first and the second information inputs of the first shift register are connected respectively to the output of the priority block and the second output of the memory block, the start, synchronization, and mode settings of the block the memory are the same-name device inputs, the presence of a group of units in the array word of the control unit is connected to the third output of the memory unit, the first and second outputs of the control unit are connected respectively to the first and second write-read inputs of the memory unit, the third, fourth and n The outputs of the control unit are connected respectively to the control input of the address generator and the summing and subtracting inputs of the first counter; the sixth and seventh outputs of the control unit are connected respectively to the input of the input and information of the first shift register, the input The stack boundary of the control unit is connected to the second output of the first counter, which is different in order to expand the device’s functionality by providing a readout of the original form of the information recorded in the device in a compressed form, a second shift register, a priority encoder, an array information analysis unit, a bit number register, second and third counters, and a comparison unit, and the information the input of the second shift register is connected to the first output of the memory block, the output of the second shift register is connected to the input of the priority encoder and the first information input of the information analysis block about the assortment, the second information input of which is connected to the output of the first shift register, the output of the priority encoder is connected to the information input of the discharge number register, the output of which is connected to the control input of the address multiplexer, the third and fourth information inputs of which are connected respectively to the outputs of the second and third counters, the information input of the third counter is connected to the output of the address driver, the outputs of the second and third counters are connected respectively to the first and second inputs of the unit Comparison, the output of which is connected to the input. The completion of the analysis of the stack of the control unit, the inputs and the shift information of the second shift register are connected respectively to the eighth and ninth outputs of the control unit, the input information of the register of the bit number and the counting input of the second count are connected respectively the tenth and eleventh outputs of the control unit, the write enable input, the summing and subtracting counting inputs of the third counter are connected to the twelfth, thirteenth and fourteenth respectively Atomic control unit outputs, inputs Presence of groups of identical array columns. The absence of groups of identical array columns and the Absence of identical columns of the array of the control unit are connected respectively to the first, second and third outputs of the array information analysis block, the second output of the first counter is the End output output of the device array. Atipec of the lower array border (block 27) 100 oyu 010 110 101 Numbers dod (columns) Array storage area Stack area - The initial position of the stack pointer (block 31) FIG. 2