JPS63115379A - Thin-film transistor and manufacture thereof - Google Patents
Thin-film transistor and manufacture thereofInfo
- Publication number
- JPS63115379A JPS63115379A JP61261260A JP26126086A JPS63115379A JP S63115379 A JPS63115379 A JP S63115379A JP 61261260 A JP61261260 A JP 61261260A JP 26126086 A JP26126086 A JP 26126086A JP S63115379 A JPS63115379 A JP S63115379A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- solid solution
- thin film
- film transistor
- cdse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000006104 solid solution Substances 0.000 claims abstract description 26
- 229910004613 CdTe Inorganic materials 0.000 claims abstract description 9
- 239000012298 atmosphere Substances 0.000 claims abstract description 8
- 150000001875 compounds Chemical class 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 20
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 239000000470 constituent Substances 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 14
- 239000011521 glass Substances 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000011282 treatment Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ファクシミリ等の読み取りに用いられるイメ
ージセンサや、ＥＬ表示装置、液晶表示パネル、液晶テ
レビ等の駆動回路に用いられる薄膜トランジスタ（以下
ＴＰＴと略す）の構成およ３ ・・−／
びその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to thin film transistors (hereinafter abbreviated as TPT) used in image sensors used for reading facsimiles, EL display devices, liquid crystal display panels, liquid crystal televisions, etc. ), the structure of 3...-/, and the manufacturing method thereof.
従来の技術
従来のＴＰＴの半導体材料として、特開昭５８−７４０
７９号公報に示されているＴｅ薄膜や特開昭５３−２６
５８６号公報に示されているＣｄＳｅ薄膜がある。その
基本的構成は、ピーケーノζ（２−（Ｐ 、 Ｋ 、
Ｗｅ ｉｍｅｒ）等によって示された、スタガーとコプ
ラナー構造があり、本発明も同様であるので第１図の本
発明のＴＰＴ構成を用いて具体的に示す。Conventional technology As a conventional TPT semiconductor material, Japanese Patent Application Laid-Open No. 58-740
Te thin film shown in Publication No. 79 and JP-A-53-26
There is a CdSe thin film disclosed in Japanese Patent No. 586. Its basic structure is Pikenoζ(2-(P, K,
There is a staggered structure and a coplanar structure as shown by Weimer et al., and the present invention is similar to this structure, so the TPT structure of the present invention shown in FIG. 1 will be specifically illustrated.
すなわち、ガラス等の絶縁性基板１上に所定の幅と長さ
を有する、Ｃｒ、Ａｎ、Ｔａ等の金属からなるゲート電
極２を設け、その上部にゲート電極２を覆う厚さ数１０
００オングストロームで、陽極酸化膜、例えばＡｉ Ｏ
、Ｔａ２０６やスパッタ法による、例えば、Ｓ ｚ ０
２ 、 Ａβ２０３等やプラズマＣＶＤ法による、例え
ば、Ｓｉ３Ｎ４等をゲート絶縁層３として形成し、その
表面に、Ｔｅ、ＣｄＳｅ等の半導体層を真空蒸着やスパ
ッタリング法等で数１００〜数１０ｏＯオングストロー
ムの厚さに形成する。さらに半導体層上に数ミクロンか
ら数１００ミクロン程度で所定の間隔を隔ててドレイン
電極５およびリース電極６を形成している。動作原理は
、ソース−ドレイン電極間を流れるドレイン電流をゲー
ト電極２に印加する電圧により制御する、いわゆる電界
効果型トランジスタである。That is, a gate electrode 2 made of a metal such as Cr, An, Ta, etc. having a predetermined width and length is provided on an insulating substrate 1 made of glass or the like, and a thickness of several tens of tens of meters is provided on the top of the gate electrode 2, which is made of a metal such as Cr, An, or Ta.
00 angstroms, anodized film, e.g. AiO
, Ta206 or sputtering, for example, S z 0
2. A gate insulating layer 3 is formed of Aβ203 or the like by plasma CVD, for example Si3N4, and a semiconductor layer of Te, CdSe, etc. is formed on the surface by vacuum evaporation or sputtering to a thickness of several hundred to several tens of angstroms. to form. Further, a drain electrode 5 and a lease electrode 6 are formed on the semiconductor layer at a predetermined interval of about several microns to several hundred microns. The operating principle is a so-called field effect transistor in which the drain current flowing between the source and drain electrodes is controlled by the voltage applied to the gate electrode 2.
発明が解決しようとする問題点
しかし、上記の様な構成のＴＰＴでは、半導体層にＴｅ
やＣｄＳｅなどのＩＩ−ＶＩ族化合物材料が用いられて
いるが、一般的にこれらは構成元素の蒸気圧が高いため
欠陥や組成ズレを生じやすく、また、再蒸発のために膜
厚の制御が困難である。さらに、不活性ガス雰囲気中で
の熱処理条件により、ドレイン電流が大きく変動し、例
えば、３０喘口の基板上に形成した場合にその均一性や
コントロールに問題がある。Problems to be Solved by the Invention However, in the TPT having the above structure, Te is not included in the semiconductor layer.
Group II-VI compound materials such as CdSe and CdSe are used, but these generally have high vapor pressure of their constituent elements, which makes them prone to defects and compositional deviations, and it is difficult to control the film thickness due to re-evaporation. Have difficulty. Furthermore, the drain current varies greatly depending on the heat treatment conditions in an inert gas atmosphere, and there are problems with its uniformity and control when it is formed on a 30-hole substrate, for example.
また、ＴｅやＣｄＳｅの場合、膜中の欠陥等によシ浅い
トラップが生じるだめ、温度特性が悪く、ドレイン電流
が４０’Ｃ位から急激に低下するという問題がある。さ
らに、ゲート電圧が印加されな５ ベー／゛
い状態におけるオフ電流が大きく、高いＳ／Ｎ比の必要
なシステムに応用する場合に問題となっている。In addition, in the case of Te or CdSe, shallow traps occur due to defects in the film, resulting in poor temperature characteristics and a problem in that the drain current drops rapidly from about 40'C. Furthermore, the off-state current is large when no gate voltage is applied, which is a problem when applied to a system that requires a high S/N ratio.
そして、Ｔｅの場合、移動度が１０ｃｄ／ｖ−友と小さ
いために高速動作駆動が制限される。In the case of Te, high-speed operation is limited because the mobility is as small as 10 cd/v.
問題点を解決するための手段
本発明は、上記問題点を解決するために、薄膜トランジ
スタの半導体層としてＩＩ−ＶＩ族化合物半導体の固溶
体膜を用い、特に好ましくはＣｄＳ 。Means for Solving the Problems In order to solve the above problems, the present invention uses a solid solution film of a II-VI group compound semiconductor as a semiconductor layer of a thin film transistor, and particularly preferably CdS.
ＣｄＳｅ、ＣｄＴｅの内少なくとも２種から成る固溶体
膜を、さらにはＣｕを含有し、Ｃｎ雰囲気中で熱処理し
た膜を用いるものである。A solid solution film made of at least two of CdSe and CdTe is used, which further contains Cu and is heat-treated in a Cn atmosphere.
作 用
本発明は、上記の様に半導体層に固溶体膜を用いる事に
より、膜中の欠陥を少なくし、かつコントロールを容易
にすると共に、温度特性を改善することができ、同時に
、オフ電流を小さくできるものである。そして、Ｃｕお
よびＯｎのドーピングは、この効果をさらに高めるもの
である。Function: By using a solid solution film for the semiconductor layer as described above, the present invention can reduce defects in the film, facilitate control, improve temperature characteristics, and at the same time reduce off-current. It can be made small. Doping with Cu and On further enhances this effect.
また、結晶性を改善するだめの５００’Ｃ以上のｅ”−
／
Ｃｆｉ雰囲気中での熱処理により、膜の安定性やドレイ
ン電流の均一性が得られるものである。In addition, e”-
The heat treatment in a /Cfi atmosphere provides stability of the film and uniformity of drain current.
実施例 以下に、本発明の第１の実施例について説明する。Example A first embodiment of the present invention will be described below.
第１図は、本発明による薄膜トランジスタの断面図であ
る。同図において、ガラス等の絶縁性基板１上に、例え
ばＣｒを約１０００人程度、電子ビーム法等で形成しゲ
ート電極２として所定の巾と長さに形成する。次に、ゲ
ート電極２と半導体層４との絶縁のために、例えば、５
ｉ０２．Ａβ２ｏ３゜Ｓ Ｉ Ｎ 、 Ｔ ａ ２０
ｓ等を約数１００〜数１０００ Ａ程度の膜厚でゲー
ト絶縁層３を形成する。さらに、ゲート絶縁層３上に、
例えば、Ｃｄ５−ＣｄＳｅ 。FIG. 1 is a cross-sectional view of a thin film transistor according to the present invention. In the figure, about 1000 Cr layers are formed on an insulating substrate 1 made of glass or the like by an electron beam method or the like to form a gate electrode 2 having a predetermined width and length. Next, in order to insulate the gate electrode 2 and the semiconductor layer 4, for example,
i02. Aβ2o3゜S I N , T a 20
The gate insulating layer 3 is formed with a film thickness of approximately several hundred to several thousand amps. Furthermore, on the gate insulating layer 3,
For example, Cd5-CdSe.
Ｃｄ５−ＣｄＴｅやＣｃｌＳ−ＣｄＳｅ−ＣｄＴｅ等の
ｎ−ｖｒ族化合物半導体の固溶体を半導体層４として約
数１００〜数１０００人の膜厚で形成する。そして、そ
の半導体層４上に所定の間隔を設けてソース電極５およ
びドレイン電極６を、例えば、Ｃｒ／Ａｕ。A solid solution of an n-vr compound semiconductor such as Cd5-CdTe or CclS-CdSe-CdTe is formed as the semiconductor layer 4 to a thickness of about several 100 to several 1000 layers. A source electrode 5 and a drain electrode 6 are formed on the semiconductor layer 4 at a predetermined interval, for example, using Cr/Au.
Ｉ ｎ／Ａｕ 、Ｃｒ 、Ａｎ 、 Ｉｎ等の半導体層
４とオーミノ７ベーー
り電極を形成できる金属で形成する。It is formed of a metal such as In/Au, Cr, An, In, etc., which can form an electrode based on the semiconductor layer 4 and the ohmino 7 base.
本構成によれば、半導体層４にＣｄＳ、ＣｄＳｅ。According to this configuration, the semiconductor layer 4 includes CdS and CdSe.
ＣｄＴｅの内少なくとも２種の成分からなる固溶体膜と
する事によシ、高温での処理が可能となるため、膜の安
定性が増すとともに、−２０〜８０’Ｃの間で特性も余
シ変わらず温度特性も大巾に改善されるものである。By forming a solid solution film consisting of at least two components of CdTe, it becomes possible to process at high temperatures, which increases the stability of the film and also maintains its characteristics between -20 and 80'C. The temperature characteristics are also greatly improved.
また、半導体層４として、Ｃｕを０．０１〜０．５モル
チ含有した例えばＣｄ５−ＣｄＳｅ固溶体をＣｆ！。Further, as the semiconductor layer 4, for example, a Cd5-CdSe solid solution containing 0.01 to 0.5 mol of Cu is used as Cf! .
を含む雰囲気中、５００〜ｅｏｏ°Ｃの温度で熱処理す
る事により、ゲート絶縁層３と半導体層４との界面にお
いて、結晶性の向上により界面準位や欠陥等が大巾に減
少し、ドレイン電流の安定性が著しく増すとともに、Ｃ
ｕおよびＣｕ２がドーパントとなり、ドレイン電流が大
きくかつオフ電流も同時に少さくできるもので、コント
ロール性に優れ、かつ大面積にわたって均一な特性が得
られるものである。By heat treatment at a temperature of 500 to eoo°C in an atmosphere containing The stability of the current increases significantly, and C
U and Cu2 serve as dopants, and the drain current can be large and the off-state current can be reduced at the same time, and it is possible to obtain excellent controllability and uniform characteristics over a large area.
以下に、第２図（ａ）〜（ｑ）を用いて、そのＴＰＴの
製造方法について詳細に述べる。The method for manufacturing the TPT will be described in detail below with reference to FIGS. 2(a) to (q).
まず、例えば、コーニング社の７ｏ５９ガラス等の絶縁
性基板１を洗浄し、後工程の熱処理における熱歪をさけ
るために処理温度以上、例えば６５０’Ｃで熱処理した
後、第２図（、）に示す様Ｋ、Ｃｒ等の金属を１０００
人程度電子ビーム蒸着法等で全面に被着後、（ｂ）の様
に、ゲート電極２を、エツチング法によシ所定のパター
ンに形成する。次に第２図（ｃ）の様に、ゲート絶縁層
３として、５００〜５ｏｏｏ人程度の膜厚に、スパッタ
リング法、電子ビーム法、プラズマＣＶＤ法等で形成す
る。その場合、半導体層との界面となるゲート絶縁層３
の表面の膜質が欠陥の少ない膜とするために、形成条件
を考える必要がある。さらに第２図（ｄ）の様にゲート
絶縁層３上全面に、Ｃｄ５−ＣｄＳｅ固溶体を全面に真
空蒸着法によｐ５００〜５０００への膜厚に形成し、（
ｅ）の様に、ドライエツチング法を用いてフォトリソ法
で形成した所定のパターンの半導体層４にする。その後
、半導体層４とゲート絶縁層３との欠陥、界面欠陥によ
る特性、温度特性改善するために、３００〜６００°Ｃ
程度の熱９ パ＼−／
処理を行う。First, an insulating substrate 1 made of Corning's 7o59 glass, for example, is cleaned and heat treated at a temperature higher than the processing temperature, for example 650'C, in order to avoid thermal distortion in the post-process heat treatment. 1000 of metals such as K and Cr as shown
After being deposited on the entire surface by electron beam evaporation or the like, the gate electrode 2 is formed into a predetermined pattern by etching, as shown in FIG. 3(b). Next, as shown in FIG. 2(c), a gate insulating layer 3 is formed to a thickness of approximately 500 to 500 nm by sputtering, electron beam, plasma CVD, or the like. In that case, the gate insulating layer 3 serving as the interface with the semiconductor layer
In order to obtain a film with few defects on its surface, it is necessary to consider the formation conditions. Furthermore, as shown in FIG. 2(d), a Cd5-CdSe solid solution is formed on the entire surface of the gate insulating layer 3 to a thickness of p500 to 5000 by vacuum evaporation.
As shown in e), a dry etching method is used to form a semiconductor layer 4 having a predetermined pattern formed by photolithography. Thereafter, in order to improve the characteristics due to defects, interface defects, and temperature characteristics between the semiconductor layer 4 and the gate insulating layer 3,
Treat at a temperature of 9 degrees.
次に第２図（ｆ）の様に、フォトリン法により、所定の
間隔を有する電極を形成するために、７オトレジスト７
のパターンを形成し、（ｑ）の様に、Ｃｒ／Ａｕ 、
Ｉｎ／Ａｕ 、Ｃｒ 、ＡＩ！、、ＮｉＣｒ等を全面に
被着後、リントオフ法によシ、ソース電極５およびドレ
イン電極６を形成するものである。Next, as shown in FIG. 2(f), in order to form electrodes having predetermined intervals by the photorin method, 7 photo resists 7 are applied.
As shown in (q), Cr/Au,
In/Au, Cr, AI! After depositing NiCr, etc. on the entire surface, a source electrode 5 and a drain electrode 6 are formed by a lint-off method.
上記構成の様に、半導体層４に、例えばＣｄ５−ＣｄＳ
ｅ固溶体膜を用いることにょシ、高温処理が可能となシ
、ＴＰＴ特性における温度特性が大巾に改善されるとと
もに、非常に特性の安定したＴＰＴを作製できるもので
ある。As in the above structure, the semiconductor layer 4 is made of, for example, Cd5-CdS.
By using a solid solution film, high-temperature treatment is possible, the temperature characteristics of TPT characteristics are greatly improved, and TPT with extremely stable characteristics can be produced.
また、上記Ｃｄ５−ＣｄＳｅ固溶体膜等にＣｕを所定量
、例えば０．０１〜０．５モルチ程度含有させた半導体
層を用い、Ｃｄ、Ｃｎ２等のＣｎ雰囲気中５００〜６０
０’Ｃにおいて、半密閉容器中で、熱処理を行う事によ
シ、よシ半導体層とゲート絶縁層との界面欠陥を減少さ
せるとともに、上記熱処理による再結晶化によシ、絶縁
層中のみならず半導体層中の欠陥の減少に伴なうキャリ
ア数の増加に１０′−７
よるドレイン電流の増加、さらには、Ｃｕや０℃のドー
ピングによるオフ電流の著しい減少をもたらすものであ
る。In addition, using a semiconductor layer containing a predetermined amount of Cu, for example, about 0.01 to 0.5 molti, in the above-mentioned Cd5-CdSe solid solution film, etc.
By performing heat treatment in a semi-closed container at 0'C, interface defects between the semiconductor layer and the gate insulating layer can be reduced, and recrystallization caused by the above heat treatment can reduce defects only in the insulating layer. However, due to the increase in the number of carriers due to the decrease in defects in the semiconductor layer, the drain current increases due to 10'-7, and furthermore, the off-state current significantly decreases due to the doping of Cu and 0 DEG C.
次に第２の実施例とその製造方法を述べる。第３図に示
す様に、第１図のゲート絶縁層３と半導体層４との間に
、ゲート電極２材料の拡散や、ピンホール等を防ぐため
に、絶縁層８を設け、多層膜構成とするものであシ、さ
らには、最上層の絶縁層８を、半導体層４例えばＣｄ５
−ＣｄＳｅ固溶体との熱膨張係数が同程度の層、例えば
、コーニング社の７０５９ガラス等をスパッタリング法
等により、数１００〜数１０００八形成することにより
、熱処理工程における半導体層４とゲート絶縁層３との
界面に生じるクラックや界面欠陥を著しく減少させると
ともに、半導体層４成分のゲート絶縁層３中への拡散を
同時に防ぐことができるものである。熱膨張係数が同程
度というのは後の熱処理で特性に有害なりラックを半導
体層に生じない程度であることを意味する。その他の構
成、工程は第１図および第２図と同様である。Next, a second embodiment and its manufacturing method will be described. As shown in FIG. 3, an insulating layer 8 is provided between the gate insulating layer 3 and the semiconductor layer 4 in FIG. 1 in order to prevent diffusion of the gate electrode 2 material and pinholes, etc., resulting in a multilayer film structure. Furthermore, the uppermost insulating layer 8 is made of a semiconductor layer 4 such as Cd5.
- By forming a layer having a thermal expansion coefficient similar to that of the CdSe solid solution, such as Corning's 7059 glass, by sputtering, etc., the semiconductor layer 4 and the gate insulating layer 3 can be formed in a heat treatment process. It is possible to significantly reduce cracks and interface defects occurring at the interface with the gate insulating layer 3, and at the same time prevent diffusion of the four components of the semiconductor layer into the gate insulating layer 3. The fact that the coefficients of thermal expansion are about the same means that the thermal expansion coefficients are at a level that will not cause racks in the semiconductor layer that would be detrimental to the properties during subsequent heat treatment. Other configurations and steps are the same as those in FIGS. 1 and 2.
１１ ベーン
まだここで、上記構成にこだわる必要はなく、ＴＰＴ特
性の得られる構成であれば、どの構成でも良い事は言う
までもない。さらに、半導体層はＣｄ５−ＣｄＳｅ固溶
体にかぎらず、Ｃｄ５−ＣｄＴｅやＣｄ５−Ｃｄ５ｅ−
ＣｄＴｅ 固溶体でも良いことは言うまでもなく、他の
■−■族化合物半導体材料の固溶体を使用することもで
きる。11 Vane It is needless to say that there is no need to be particular about the above configuration, and any configuration may be used as long as the TPT characteristics can be obtained. Furthermore, the semiconductor layer is not limited to Cd5-CdSe solid solution, but also Cd5-CdTe, Cd5-Cd5e-
It goes without saying that a CdTe solid solution may be used, but also a solid solution of other ■-■ group compound semiconductor materials may also be used.
発明の効果 本発明によれば、従来の半導体層材料のＴｏ。Effect of the invention According to the invention, To of the conventional semiconductor layer material.
ＣｄＳｅ等から例えばＣｄ５−ＣｄＳｅ固溶体とする事
によシ、高温処理が可能となシ、温度特性が大巾に安定
するとともに、組成ズレを生じにくいので、膜中や界面
の欠陥に起因する特性が改善され、ドレイン電流の均一
性とコントロールが容易となる。For example, by making a Cd5-CdSe solid solution from CdSe, etc., high-temperature processing is possible, the temperature characteristics are largely stable, and composition deviations are less likely to occur, so characteristics caused by defects in the film or at the interface can be improved. This improves the uniformity and control of drain current.
さらには、Ｃｕ含有した固溶体膜を０℃雰囲気中で処理
する事により、結晶性の改善や界面欠陥の減少がより得
られるので、特性の制御が容易にしかも大面積にわたっ
て均一にでき、生産性、信頼性への効果が大きいもので
ある。Furthermore, by treating the Cu-containing solid solution film in a 0°C atmosphere, it is possible to further improve crystallinity and reduce interface defects, making it easier to control properties and making them uniform over a large area, increasing productivity. , which has a large effect on reliability.
また、ゲート絶縁層を多層膜構成とし、最上層を熱膨張
係数が固溶体膜と同程度の絶縁層とする事により、クラ
ック、ピンホールによるＴＰＴ素子の絶縁破壊やゲート
電極材料等の不純物の拡散の防止、さらには、ゲート絶
縁層と半導体層間の界面状態による特性が安定するので
、工業的価値が太きｂものである。In addition, by making the gate insulating layer a multilayer film structure and making the top layer an insulating layer with a coefficient of thermal expansion similar to that of the solid solution film, it is possible to prevent dielectric breakdown of the TPT element due to cracks and pinholes, and to prevent diffusion of impurities such as gate electrode materials. It is of great industrial value because it prevents this and further stabilizes the characteristics due to the state of the interface between the gate insulating layer and the semiconductor layer.
第１図は本発明の第１の実施例を示す薄膜トランジスタ
の断面図、第２図は第１の実施例における製造工程を示
す断面図、第３図は本発明の第２の実施例を示す薄膜ト
ランジスタの断面図である。
２・・−・ゲート電極、３・・ ゲート絶縁層、４・・
−・Ｃｄ５−ＣｄＳｅ固溶体等からなる半導体層、６・
・・ソース電極、６・・・−・ドレイン電極、８・・−
・・絶縁層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名２−
一−ゲ′−ト１包襲氏
ａ−一一ゲート秒１
４−一一半等４橘
第１図FIG. 1 is a cross-sectional view of a thin film transistor showing a first embodiment of the invention, FIG. 2 is a cross-sectional view showing the manufacturing process in the first embodiment, and FIG. 3 is a second embodiment of the invention. FIG. 2 is a cross-sectional view of a thin film transistor. 2... Gate electrode, 3... Gate insulating layer, 4...
- Semiconductor layer made of Cd5-CdSe solid solution, etc., 6.
...Source electrode, 6...--Drain electrode, 8...-
...Insulating layer. Name of agent: Patent attorney Toshio Nakao and 1 other person2-
1-gate 1 raid Mr. a-11 gate second 1 4-11 and a half etc. 4 Tachibana Fig. 1
Claims (8)
縁層と半導体層とソースおよびドレイン電極とを基本要
素としてなる薄膜トランジスタにおいて、前記半導体層
がII−VI族化合物半導体の固溶体でなる事を特徴とする
薄膜トランジスタ。(1) In a thin film transistor formed on an insulating substrate and consisting of a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes as basic elements, the semiconductor layer may be made of a solid solution of a II-VI group compound semiconductor. Features of thin film transistors.
なくとも２種の構成成分からなる事を特徴とする特許請
求の範囲第１項に記載の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein the solid solution consists of at least two constituents among CdS, CdSe, and CdTe.
特許請求の範囲第１項記載の薄膜トランジスタ。(3) The thin film transistor according to claim 1, wherein the solid solution contains a small amount of Cu.
を特徴とする特許請求の範囲第１項に記載の薄膜トラン
ジスタ。(4) The thin film transistor according to claim 1, wherein the solid solution is heat-treated in an atmosphere containing Cl.
層が、半導体層と熱膨張係数が同程度である事を特徴と
する特許請求の範囲第１項に記載の薄膜トランジスタ。(5) The thin film transistor according to claim 1, wherein the gate insulating layer is made of a multilayer film, and the uppermost insulating layer has a coefficient of thermal expansion comparable to that of the semiconductor layer.
し、ゲート電極を形成する工程と、ゲート絶縁層を形成
する工程と、II−VI族化合物半導体の固溶体でなる半導
体層を形成する工程と、リースおよびドレイン電極を形
成する工程とを含む事を特徴とする薄膜トランジスタの
製造方法。(6) When forming a thin film transistor on an insulating substrate, there are a step of forming a gate electrode, a step of forming a gate insulating layer, a step of forming a semiconductor layer made of a solid solution of a II-VI compound semiconductor, and a lease. and a step of forming a drain electrode.
事を特徴とする特許請求の範囲第６項に記載の薄膜トラ
ンジスタの製造方法。(7) The method for manufacturing a thin film transistor according to claim 6, which includes a heat treatment step for improving crystallinity of the semiconductor layer.
徴とする特許請求の範囲第７項に記載の薄膜トランジス
タの製造方法。(8) The method for manufacturing a thin film transistor according to claim 7, wherein the heat treatment step is performed in an atmosphere containing Cl.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61261260A JPH0828508B2 (en) | 1986-10-31 | 1986-10-31 | Thin film transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61261260A JPH0828508B2 (en) | 1986-10-31 | 1986-10-31 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63115379A true JPS63115379A (en) | 1988-05-19 |
| JPH0828508B2 JPH0828508B2 (en) | 1996-03-21 |
Family
ID=17359357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61261260A Expired - Lifetime JPH0828508B2 (en) | 1986-10-31 | 1986-10-31 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828508B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5626468A (en) * | 1979-08-09 | 1981-03-14 | Sharp Corp | Structure of membrane transistor |
| JPS5994460A (en) * | 1982-11-19 | 1984-05-31 | Matsushita Electric Ind Co Ltd | Manufacture of thin film transistor |
-
1986
- 1986-10-31 JP JP61261260A patent/JPH0828508B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5626468A (en) * | 1979-08-09 | 1981-03-14 | Sharp Corp | Structure of membrane transistor |
| JPS5994460A (en) * | 1982-11-19 | 1984-05-31 | Matsushita Electric Ind Co Ltd | Manufacture of thin film transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0828508B2 (en) | 1996-03-21 |
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