JPS5889867A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS5889867A JPS5889867A JP18807881A JP18807881A JPS5889867A JP S5889867 A JPS5889867 A JP S5889867A JP 18807881 A JP18807881 A JP 18807881A JP 18807881 A JP18807881 A JP 18807881A JP S5889867 A JPS5889867 A JP S5889867A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- films
- oxide
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 239000010408 film Substances 0.000 claims abstract description 79
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000000919 ceramic Substances 0.000 claims abstract description 7
- 239000011521 glass Substances 0.000 claims abstract description 6
- 238000000926 separation method Methods 0.000 claims abstract 2
- 239000012212 insulator Substances 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 21
- 239000002184 metal Substances 0.000 abstract description 21
- 230000001590 oxidative effect Effects 0.000 abstract description 20
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 6
- 150000004706 metal oxides Chemical class 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- AQCDIIAORKRFCD-UHFFFAOYSA-N cadmium selenide Chemical compound [Cd]=[Se] AQCDIIAORKRFCD-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- -1 kermanium (Ge) Chemical compound 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- 229910001935 vanadium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、薄膜トランジスタのスイッチフグ素子形成に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to formation of a switching element of a thin film transistor.
スイッチング素子、例えば、絶縁ゲート薄膜トランジス
タの代表的な構造としては、基板−半導体膜一絶縁層一
導電層より成る。スイッチング素子を積層した液晶パネ
ルとして要求される事Ｉｉ。A typical structure of a switching element, such as an insulated gate thin film transistor, includes a substrate, a semiconductor film, an insulating layer, and a conductive layer. Requirements for liquid crystal panels with stacked switching elementsIi.
大面積化及び低コスト及び性能の向上であ゛す、その一
方法としては、基板として、ガラス或は、セラミックス
な使用する事が考えられるが、その場合、現在一般に利
用されて（する半導体製造技術におい工は、１０００℃
以上での高温処理工程を必要とする゛ため、基板の耐熱
性等の関係から難しくなる。現在実際に半導体技術−に
使用されて（・るゲート絶縁膜としては、シリコンの熱
酸化膜（Ｓｉ Ｏｘ ）が主である。基板により熱酸化
の温度の制約を受ける場合に現在考えられるゲート絶縁
膜の形成方法としては、物理蒸着法（ＰＶＤ）及び化学
蒸着法（ＣＶＤ）が有るが、熱−酸化膜に比較すると」
膜の均一性、絶縁性、膜中の欠陥、不純物密度、界面準
位密度等の点で劣っているのが現状で乏る。さらに、高
性能、低消電型薄膜トラノジスタの製造゛と６う関点か
らすると、絶縁層を薄くするか、誘電率の大きな膜を利
用し、かつ絶縁性の向上が必要になり、半導体膜−電極
間及び。One way to increase the area, lower costs, and improve performance is to use glass or ceramics as the substrate, but in that case, it is currently commonly used (in semiconductor manufacturing). Technical odor control is 1000℃
Since the above-mentioned high-temperature treatment process is required, it becomes difficult due to factors such as the heat resistance of the substrate. Currently, the main gate insulating film actually used in semiconductor technology is silicon thermal oxide film (SiOx). There are physical vapor deposition (PVD) and chemical vapor deposition (CVD) methods for forming films, but compared to thermal oxidation films.
Currently, it is poor in terms of film uniformity, insulation, defects in the film, impurity density, interface state density, etc. Furthermore, from the perspective of manufacturing high-performance, low-power consumption thin-film transistors, it is necessary to make the insulating layer thinner or use a film with a high dielectric constant, and to improve the insulation properties. - Between the electrodes and.
電極−電極間及び素子間のリークが問題となる。Leakage between electrodes and between elements becomes a problem.
そこで上記面題の解決法”とし、本発明では、酸化膜の
均一性、絶縁性、膜中の欠陥、不純物密度。Therefore, the present invention aims to solve the above problems by improving the uniformity of the oxide film, insulation properties, defects in the film, and impurity density.
界面準位密度等の電気的、物理的特性において現在使用
されているシリコノの熱酸化膜以上の膜を金属酸化物例
えば、タノ゛タル或は、・−バナジウム等の酸化物を利
用し、低温でかつ、素子間分離を金１４酸化物を利用し
行ない、薄膜トランジスタの素子間及び、半導体膜−電
極間の横方向リークを防止し、高性、能薄膜トランジス
タを提供する事を目−的と゛している。In terms of electrical and physical properties such as interfacial state density, it is possible to develop films using metal oxides such as tantalum or -vanadium oxides at low temperatures, which have better electrical and physical properties than the silicon thermal oxide films currently used. Furthermore, the purpose is to provide a high-performance thin film transistor by using gold-14 oxide to isolate elements, thereby preventing lateral leakage between elements of a thin film transistor and between a semiconductor film and an electrode. ing.
ガラス及びセラミックス基板上へ半導体膜を形成する方
法としては、プラズマ或は低圧化学蒸着及び、物理蒸着
、さらに高真空を利用した分子線蒸着（ＭＢＤ）法等が
有゛るが、一般のガラス及びセラミックスの耐熱温度以
内で、半導体膜を熱酸化する事は難しく、薄膜トランジ
スタの性能の低下につながっている。そこで本発明では
、低温酸化性膜、何えば夕／タル或は、バナジウム等の
金属膜を半導体膜或は、基板上に形成し、該低温酸化性
の金属膜上べ耐熱性膜をパターニングし、耐熱性膜をマ
スクとして、低温酸化性金属膜を熱酸化し、半導体膜上
に、マスクされた金属部分゛より、薄膜トランジスタと
して当然必要であるソース或はドレイ／電極として利用
し、該低温酸化性金属の熱酸化膜をゲート絶縁膜として
利用すると、ともに、半導体膜間、例えばスイッチング
素子間等を低温酸化性金属の酸化物により分離する構造
を有する薄−トランジスタ構造である。Methods for forming semiconductor films on glass and ceramic substrates include plasma or low-pressure chemical vapor deposition, physical vapor deposition, and molecular beam deposition (MBD) using high vacuum. It is difficult to thermally oxidize semiconductor films within the heat resistance temperature of ceramics, leading to a decline in the performance of thin film transistors. Therefore, in the present invention, a low-temperature oxidizing film, such as a metal film such as aluminum or vanadium, is formed on a semiconductor film or a substrate, and a heat-resistant film is patterned on the low-temperature oxidizing metal film. Using the heat-resistant film as a mask, the low-temperature oxidizing metal film is thermally oxidized, and the masked metal portion is used as a source or drain/electrode, which is naturally necessary for a thin film transistor, on the semiconductor film, and the low-temperature oxidation is performed. When a thermally oxidized metal film is used as a gate insulating film, a thin transistor structure is obtained in which semiconductor films, such as switching elements, are separated by a low-temperature oxidizable metal oxide.
本構造を有する事により１、工程数を減らす事を可能と
し、基板上に形成された低温酸化性金属酸化物により、
スイッチング素子間の分離ができ、薄膜トランジスタの
スイッチング特性の改善、高集積化及び、消電に対し−
て悪影響を及ぼす横方向リークを防止そる事を可能とす
る。現在、シリコ／の熱酸化の際に利用しにくいとされ
てぃ−た耐熱性樹脂、例えば、ポリイミド樹脂等の利用
を可能にし、エツチング精度の向上等に、より、歩留り
の向上もできる。By having this structure, 1. It is possible to reduce the number of steps, and the low-temperature oxidizing metal oxide formed on the substrate allows
Can separate switching elements, improve switching characteristics of thin film transistors, increase integration, and reduce power consumption.
This makes it possible to prevent lateral leakage that can have an adverse effect. This makes it possible to use heat-resistant resins, such as polyimide resins, which are currently difficult to use in thermal oxidation of silico, and improves etching accuracy and yield.
さ、うに、本発明の構造を利用し、液晶表示用スイッチ
ングパネルを作製する場合に、該構造中の基板上に形成
された、低温酸化性金属酸化物の素子間分離に利用され
た部分の一部分を島状に分離し、電極を形成し、・スイ
ッチング素子用のキャパシタと見て利用する事も可能と
なる。下電檜°としては、例えば、スイッチング素子と
同一工程により形成した膜、或は、金属膜を形成する事
も可能であり、上電極としては、例えば、ゲート電極と
同時に配線する事により、配線の面積及び、工程の短縮
に寄与する。Now, when manufacturing a switching panel for a liquid crystal display using the structure of the present invention, the portion of the low-temperature oxidizing metal oxide formed on the substrate used for isolation between elements, It is also possible to separate a portion into an island shape, form an electrode, and use it as a capacitor for a switching element. For the lower electrode, for example, it is possible to form a film formed in the same process as the switching element, or a metal film, and for the upper electrode, for example, by wiring at the same time as the gate electrode, it is possible to form the wiring. This contributes to reducing the area and process.
ゝ−
次に本発明の薄膜トランジスタの一実施例を図を用いて
詳細に説明する。第１図は、本発明により構成される薄
膜トランジスタであり、ｌは基板であり、２が基板上に
パターニングされた半導体膜であり、３が、ソース或は
ドレイ／電極で、５は、低温酸化性金属を酸化して形成
した酸化物により形成されたゲート絶縁膜で、５′は、
５と同時に形成された、低温酸化性金属酸化物による素
子間分離部分であり、６はゲート電極である。- Next, one embodiment of the thin film transistor of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a thin film transistor constructed according to the present invention, where l is a substrate, 2 is a semiconductor film patterned on the substrate, 3 is a source or drain/electrode, and 5 is a low-temperature oxidation film. 5' is a gate insulating film formed of an oxide formed by oxidizing a metal.
5 is an inter-element isolation portion made of a low-temperature oxidizable metal oxide, which was formed at the same time as 5, and 6 is a gate electrode.
第２図は、第１図の素子間分離部分５′の一部を島状に
分離し、スイッチング素子のキャパシタとして利用した
薄膜トランジスタの一例を示した構造を示す断面図で１
は基板であり、２は基板上にパターニングされた半導体
膜であり、３はソース或は、ドレイ／電極であり、５は
、低温酸化性金属を酸化して形成した酸化物より成るゲ
ート絶縁膜であり、５′は、５と同一に形成された素子
間分離用酸化膜の一部分を島状にし、下電極２′と上電
極６′を形成する事により構成されたキャパシタの誘電
体膜部分である。FIG. 2 is a cross-sectional view showing a structure of an example of a thin film transistor in which a part of the isolation portion 5' of FIG. 1 is separated into islands and used as a capacitor of a switching element.
is a substrate, 2 is a semiconductor film patterned on the substrate, 3 is a source or drain/electrode, and 5 is a gate insulating film made of an oxide formed by oxidizing a low-temperature oxidizing metal. 5' is a dielectric film portion of a capacitor constructed by making a part of the oxide film for isolation between elements formed in the same manner as 5 into an island shape, and forming a lower electrode 2' and an upper electrode 6'. It is.
次に本発明の薄膜トランジスタの製法の一実施例を図を
用いて説明する。第３図は、本発明の薄膜トランジスタ
の製造工程の一実施例である。第３図Ａに於いて、１は
ガラス或はセラミックス基板であり、２は、シリコン（
Ｓｔ）、 カドミウムセレノ（ＣｄＳｅ）、ケルマニ
ウム（Ｇｅ）或はガリウムヒ素（Ｇａ Ａｓ ）等によ
る半導体膜であり。Next, one embodiment of the method for manufacturing a thin film transistor of the present invention will be described with reference to the drawings. FIG. 3 shows an embodiment of the manufacturing process of the thin film transistor of the present invention. In FIG. 3A, 1 is a glass or ceramic substrate, and 2 is a silicon (
It is a semiconductor film made of cadmium selenium (CdSe), kermanium (Ge), gallium arsenide (GaAs), or the like.
半導体の形成法としては、プラズマ或はプラズマＣＶＤ
及びＰＶＤ、ＥＢＤ法等が有り、半導体膜をパターニン
グする方法は、半導体技術として一般に利用されている
糸トリソゲラフイー及びエツチング等によって行なう。As a method for forming semiconductors, plasma or plasma CVD is used.
There are also methods such as PVD, EBD, etc., and methods for patterning the semiconductor film include thread trisograying and etching, which are commonly used in semiconductor technology.
第３図Ｂは、該基板上に低温酸化性金属膜を形成した図
であり、３が、酸化しようとする低温酸化性金属は、例
えば、タノタル（Ｔａ ） 等である。金属膜の形成
法と・しては、ＰＶＤ、プラズマ蒸着、スパッタ蒸着或
は、有機金属を利用した化学蒸着法（ＭＯＣＶＤ）等が
有る。第３１図Ｃは、該低温酸化性金属膜３上へ耐熱膜
４、例えば、ＣＶＤ或はＰＶＤシリコン酸化膜、シリコ
ン窒化膜或は、ポリイミド樹脂環バターニノグした図を
示す。該耐熱性膜４は、スイッチング素子を構成するソ
ース或は、ドレイノミ種部分を該低温酸化性金属膜に形
成するためのマスクとして作用し、かつ、耐熱性膜とし
て絶縁性物質、例えば、ＣＶＤ或は％ＰＶＤシリコン酸
化膜、シリコン窒化膜、或はボリイミード樹脂等をコー
トして多層構造にした場合ソース及びドレイン電極部多
層素子間の絶縁膜とすることができる。FIG. 3B shows a low-temperature oxidizing metal film formed on the substrate, and the low-temperature oxidizing metal 3 to be oxidized is, for example, tantalum (Ta). Methods for forming the metal film include PVD, plasma deposition, sputter deposition, and chemical vapor deposition using organic metals (MOCVD). FIG. 31C shows a diagram in which a heat-resistant film 4, such as a CVD or PVD silicon oxide film, a silicon nitride film, or a polyimide resin ring butter is formed on the low-temperature oxidizing metal film 3. The heat-resistant film 4 acts as a mask for forming a source or drain seed portion constituting a switching element in the low-temperature oxidizing metal film, and is made of an insulating material such as CVD or %PVD silicon oxide film, silicon nitride film, or polyimide resin, etc. to form a multilayer structure, it can be used as an insulating film between the source and drain electrode parts of the multilayer element.
第３図りは、該耐熱性膜４付き基板を酸化処理、例えば
石英チューブを利用し、酸素雰囲気中で低温酸化性金属
膜酸化処理を示す。第３図りに於いて、５は、ソース或
はドレイ／電極間における該低温酸化性膜の酸化物であ
り、スイッチング素子のゲート絶縁膜として利用する部
分であ°る。５′は、５と同一酸化処理により形成され
た酸化膜であり、素子間分離用絶縁膜として利用される
部分厚ある。The third diagram shows an oxidation treatment of the substrate with the heat-resistant film 4, for example, a low-temperature oxidizing metal film oxidation treatment in an oxygen atmosphere using a quartz tube. In the third diagram, 5 is an oxide of the low-temperature oxidation film between the source or drain/electrode, and is a portion used as the gate insulating film of the switching element. 5' is an oxide film formed by the same oxidation process as 5, and has a partial thickness that is used as an insulating film for isolation between elements.
６は、石英チューブである。第３図Ｅは、該ゲート絶縁
膜上５ヘゲート電極６、例えば、アルミニウム（Ｍ）、
ニッケル（Ｎｉ）等を形成した図であり、半導体膜２、
ソース−ドレイン電極３．酸化膜５及び５′、及びゲー
ト電極６より構成されているスイッチング素子を示して
いる。6 is a quartz tube. FIG. 3E shows a gate electrode 6 on the gate insulating film 5, for example, aluminum (M),
It is a diagram in which nickel (Ni) or the like is formed, and the semiconductor film 2,
Source-drain electrode 3. A switching element composed of oxide films 5 and 5' and a gate electrode 6 is shown.
この構造は、本発明の薄膜トランジスタ構造に示したご
とく、半導体膜が絶縁体により分離されており、素子間
のリークが防止できを構造になっている。In this structure, as shown in the thin film transistor structure of the present invention, the semiconductor film is separated by an insulator, and leakage between elements can be prevented.
本発明を利用する事により、薄膜トランジスタの製造工
程数を少なくでき、コスト低価になるとともに、低温酸
化性金属を利用する事により、ガラス或はセラミックス
基板等の利用を可能にし。By utilizing the present invention, the number of manufacturing steps for thin film transistors can be reduced, resulting in lower costs, and by using low-temperature oxidizing metals, it is possible to use glass or ceramic substrates, etc.
薄膜トランジスタの′特性の向上にも寄与する。また、
液晶等を用いた表示パネル基板上への薄膜トランジスタ
の作製に有効な技−術であり、腕時計等の小型携帯用機
器への表示装置作製に適している。It also contributes to improving the characteristics of thin film transistors. Also,
This technique is effective for manufacturing thin film transistors on display panel substrates using liquid crystals, etc., and is suitable for manufacturing display devices for small portable devices such as wristwatches.
なお、本発明による薄膜トランジスタの構゛造は低温酸
化性金属に限らす；耐熱性膜として、ＣＶＤ或はＰＶＤ
シリコン酸化膜或はシリコン窒化膜を利用し、さらに耐
熱温度の高い基板を使用する事により、高温酸化性金属
膜、例えばＭ２Ｏ３等の利用にも適用できる。Note that the structure of the thin film transistor according to the present invention is limited to low-temperature oxidizing metal; as a heat-resistant film, CVD or PVD is used.
By using a silicon oxide film or a silicon nitride film and using a substrate with a high heat resistance temperature, it is also possible to use a high temperature oxidizing metal film such as M2O3.
第一１図は、本発明の薄膜トランジスタのスイッチング
素子の構造を示す断面図、第２図は、キャパシタ部分の
構造を示す断面図。第３図Ａ、Ｂ、Ｃ１Ｄ、Ｅは、本発
明の薄膜トランジスタの製造工程？示す工程図である。
１：基板、２：半導体膜 ３：金属或は酸化性膜。
４：耐熱性膜、５：ゲート絶縁膜、５′：素子間分離部
或は、キャパシタの容器部の酸化膜。
６：〜ゲート電極、６′：キャパシタ上電極第１［
第２図FIG. 11 is a sectional view showing the structure of a switching element of a thin film transistor of the present invention, and FIG. 2 is a sectional view showing the structure of a capacitor portion. 3A, B, C1D, and E are the manufacturing steps of the thin film transistor of the present invention? FIG. 1: Substrate, 2: Semiconductor film, 3: Metal or oxidizing film. 4: heat-resistant film, 5: gate insulating film, 5': oxide film of element isolation section or capacitor container section. 6: ~gate electrode, 6': capacitor upper electrode 1st [Fig.
Claims (1)
膜によりスイッチ、ノブ素子を形成する薄膜トランジス
タに於いて、該トランジスタ間ト絶縁膜及びトランジス
タ間の絶縁体分離を形成する絶縁体膜をタンタル或は、
ノくナジウム等の酸化膜で構成した事を一徹とする薄膜
トランジスタ。In thin film transistors in which switches and knob elements are formed using semiconductor thin films formed on substrates such as glass and ceramics, the insulator films that form the inter-transistor insulating films and the insulator separation between the transistors are made of tantalum or
Thin film transistors are made entirely of oxide films such as Nadium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18807881A JPS5889867A (en) | 1981-11-24 | 1981-11-24 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18807881A JPS5889867A (en) | 1981-11-24 | 1981-11-24 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5889867A true JPS5889867A (en) | 1983-05-28 |
Family
ID=16217314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18807881A Pending JPS5889867A (en) | 1981-11-24 | 1981-11-24 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5889867A (en) |
-
1981
- 1981-11-24 JP JP18807881A patent/JPS5889867A/en active Pending
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