JPS5914673A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS5914673A JPS5914673A JP12386282A JP12386282A JPS5914673A JP S5914673 A JPS5914673 A JP S5914673A JP 12386282 A JP12386282 A JP 12386282A JP 12386282 A JP12386282 A JP 12386282A JP S5914673 A JPS5914673 A JP S5914673A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- insulator
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010410 layer Substances 0.000 claims abstract description 56
- 239000012212 insulator Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000002344 surface layer Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- 238000000354 decomposition reaction Methods 0.000 abstract description 10
- 230000001590 oxidative effect Effects 0.000 abstract 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 18
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000002048 anodisation reaction Methods 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
本発明は薄膜シリコン半導体層を有する薄膜トランジス
タの製造方法に関し、特にコプレーナ電極構造薄碑トラ
ンジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a thin film transistor having a thin silicon semiconductor layer, and more particularly to a method for manufacturing a thin transistor having a coplanar electrode structure.
従来、薄膜トランジスタの電極構造番こはスタガ電極構
造とコプレーナ電極構造とが知られている。Conventionally, the electrode structures of thin film transistors are known as a staggered electrode structure and a coplanar electrode structure.
コプレーナ電極構造はスタガ電極構造に比較して、薄膜
トランジスタの電気的特性に半導体層の膜厚が関係しな
い点が優れている。The coplanar electrode structure is superior to the staggered electrode structure in that the thickness of the semiconductor layer does not affect the electrical characteristics of the thin film transistor.
第1図は僻来のスタガ電極構造の薄膜トランジスタの一
例の断面図である。FIG. 1 is a cross-sectional view of an example of a thin film transistor with a conventional staggered electrode structure.
このトランジスタは次のようにして製造される。This transistor is manufactured as follows.
絶縁体基板1の上にゲート電極2を形成し、ゲート電極
2を含む基板の全面に絶縁体層3として酸化ヒリコン膜
を低圧プラズマ分解法により形成する。次ζ9、非晶質
のシリコン半導体層4を低圧プラズマ分解法により形成
する。このシリコン半導体層4の上にソース電極5とド
レイン電極6とを所定間隔をおいて形成し、、薄膜トラ
ンジスタとする。このトランジスタのの一寸法の一例を
示すと、チャンネル長は10μm、 チャンネル幅は
100μm、非晶質シリコン膜厚は500nm、酸化
シリコン膜厚は200nm である。A gate electrode 2 is formed on an insulating substrate 1, and a silicon oxide film is formed as an insulating layer 3 on the entire surface of the substrate including the gate electrode 2 by a low pressure plasma decomposition method. Next ζ9, an amorphous silicon semiconductor layer 4 is formed by a low pressure plasma decomposition method. A source electrode 5 and a drain electrode 6 are formed at a predetermined interval on this silicon semiconductor layer 4 to form a thin film transistor. As an example of dimensions of this transistor, the channel length is 10 μm, the channel width is 100 μm, the amorphous silicon film thickness is 500 nm, and the silicon oxide film thickness is 200 nm.
このようにして製造した薄膜トランジスタは、耐電圧性
が低く、ゲート電圧10■、ドレイン・ソース間電圧1
0Vのオン状態の電圧条件でも数%の割合で絶縁破壊を
起す。絶縁破壊を起さなかった素子は、オン状態でソー
ス・ドレイン間抵抗が10’Ω以下、ゲート電圧Ov、
ソース・ドレイン間電圧10vのオフ状態で1010Ω
以上−と液晶素子のスイッチングに満足できる値が得ら
れるが;電気的特性にドリフトやヒステリシスが大きい
という問題がある。また、ゲート電圧をIOVとした場
合、ゲート電極からソース電極への漏洩電流−bs 1
0 ’Aと高いものも多い。電気的特性のドリフトやヒ
ステリシスは、絶縁体膜に低圧プラズマ分解法による酸
化シリコン膜を用いたため、酸化シリコン膜と非晶質シ
リコン膜との界面に界面準位が多数存在することによる
と考えられる。また、漏洩電流が大会いことや耐絶縁性
が低いことは、絶縁体層を低圧プラズマ放電分解法によ
り形成したため、絶縁体膜中に水素が多く存在するのが
原因と考えられる。The thin film transistor manufactured in this way has low voltage resistance, with a gate voltage of 10μ and a drain-source voltage of 1
Even under the on-state voltage condition of 0V, dielectric breakdown occurs at a rate of several percent. Elements that did not cause dielectric breakdown had a source-drain resistance of 10'Ω or less in the on state, a gate voltage of Ov,
1010Ω in off state with source-drain voltage 10V
Although a satisfactory value can be obtained for the switching of the liquid crystal element as described above, there is a problem that the electrical characteristics have large drift and hysteresis. Also, when the gate voltage is IOV, the leakage current from the gate electrode to the source electrode -bs 1
Many are as high as 0'A. The drift and hysteresis in the electrical characteristics are thought to be due to the presence of many interface states at the interface between the silicon oxide film and the amorphous silicon film, since a silicon oxide film produced by low-pressure plasma decomposition was used as the insulator film. . Furthermore, the large leakage current and low insulation resistance are thought to be due to the presence of a large amount of hydrogen in the insulator film because the insulator layer was formed by a low-pressure plasma discharge decomposition method.
第2図は従来のスタガ構造の薄膜トランジスタの他の例
の断面図である。FIG. 2 is a cross-sectional view of another example of a conventional staggered structure thin film transistor.
このトランジスタも第1図に示したトランジスタと同様
の方法で製造される。即ち、絶縁体基板1の上番こソー
ス電極5.ドレイン電極6を形成し、全表面にシリコン
半導体層4を形成し、その上に絶縁体層3を設け、その
上にゲート電極2を設ける。製造条件は第1図に示した
例と同様である。This transistor is also manufactured in the same manner as the transistor shown in FIG. That is, the upper source electrode 5 of the insulator substrate 1. A drain electrode 6 is formed, a silicon semiconductor layer 4 is formed on the entire surface, an insulator layer 3 is provided thereon, and a gate electrode 2 is provided thereon. The manufacturing conditions are similar to the example shown in FIG.
第3図は従来のコプレーナ電極構造の薄膜トランジスタ
の一例の断面図である。FIG. 3 is a cross-sectional view of an example of a conventional thin film transistor having a coplanar electrode structure.
絶縁体基板1の上にゲート電極2を設け、全表面に絶縁
体層3を形成し、その上に所定の間隔をおいてソース電
極5とドレイン電極6とを形成する。そして全表面にシ
リコン半導体層4を形成してこのトランジスタを作る。A gate electrode 2 is provided on an insulating substrate 1, an insulating layer 3 is formed on the entire surface, and a source electrode 5 and a drain electrode 6 are formed thereon at a predetermined interval. Then, a silicon semiconductor layer 4 is formed on the entire surface to produce this transistor.
製造条件は第1図。The manufacturing conditions are shown in Figure 1.
第2図に示したスタガ電極構造のトランジスタと同様で
ある。This is similar to the staggered electrode structure transistor shown in FIG.
第4図は従来のコプレーナ電極構造の薄膜トランジスタ
の他の例の断面図である。FIG. 4 is a sectional view of another example of a conventional thin film transistor having a coplanar electrode structure.
このトランジスタはソース電極5.ドレイン電極6の形
成工程とシリコン半導体層4の形成工程とが第2図化示
す例と逆になっている他は第2図に示す例と同じであ乞
。製造条件も前記3例と同様である。This transistor has a source electrode 5. The process is the same as the example shown in FIG. 2, except that the steps for forming the drain electrode 6 and the silicon semiconductor layer 4 are reversed from the example shown in FIG. The manufacturing conditions were also the same as in the three examples above.
上記4例とも絶縁体層3の形成にはプラズマ放電分解法
が用いられている。これはシラン、酸素等を含む混合ガ
スを低圧プラズマ放電によって基板上に酸化シリコンの
膜を形成する方法である。In all of the above four examples, the plasma discharge decomposition method is used to form the insulator layer 3. This is a method of forming a silicon oxide film on a substrate by low-pressure plasma discharge using a mixed gas containing silane, oxygen, etc.
この低圧プラズマ放電分解法による酸化シリコン膜は、
熱分解法による酸化シリコン膜に比べて、低温で形成で
きるため、絶縁基板としてガラス等の耐熱性の低い安価
な基板が使用できる利点がある。しかしながら、この低
圧プラズマ放電分解法によって形成された酸化シリコン
膜は、それ以前番こ使用されていたスパッタ法、蒸着法
、ゲート電極酸化法等によって形成された酸化シリコン
と比較してシリコン半導体層4との界面における準位が
少くなったとはいえ、熱酸化による酸化シリコン膜と比
較するとまだ単位が多い。また、シラン。The silicon oxide film produced by this low-pressure plasma discharge decomposition method is
Since it can be formed at a lower temperature than a silicon oxide film formed by thermal decomposition, it has the advantage that an inexpensive substrate with low heat resistance, such as glass, can be used as an insulating substrate. However, the silicon oxide film formed by this low-pressure plasma discharge decomposition method is different from the silicon oxide film formed by the sputtering method, vapor deposition method, gate electrode oxidation method, etc. that was used previously. Although the number of levels at the interface with the silicon oxide film has decreased, there are still many units compared to a silicon oxide film formed by thermal oxidation. Also, silane.
酸素を含む混合ガスをプラズマ放電によって分解するた
め、酸化シリコン膜中に水素が入り易く形成条件の微妙
な変化によって薄膜トランジスタの特性が大きく変化す
るという問題点がある。一方。Since a mixed gas containing oxygen is decomposed by plasma discharge, there is a problem in that hydrogen easily enters the silicon oxide film and the characteristics of the thin film transistor change greatly due to subtle changes in the formation conditions. on the other hand.
薄膜トランジスタを低いゲート電圧で動作させるには、
絶縁体層3の厚みを薄くする必要があるが。To operate thin film transistors with low gate voltage,
However, it is necessary to reduce the thickness of the insulator layer 3.
絶縁体層3を薄くすると、低圧プラズマ分解法による酸
化シリコン膜は水素を含んでいるために、酸化シリコン
膜の耐電圧性が低い、ゲート電極からドレイン電極への
漏洩電流が多い等の電気的特性を悪化させる問題□を生
ずるという欠点があった。If the insulator layer 3 is thinned, the silicon oxide film produced by low-pressure plasma decomposition contains hydrogen, so electrical problems such as low voltage resistance of the silicon oxide film and large leakage current from the gate electrode to the drain electrode occur. This had the disadvantage of causing the problem □ which deteriorates the characteristics.
本発明の目的は:上記欠点を除去し、漏洩電流が少なく
耐電圧性が高く、かつ耐久性の高い絶縁体層を有する電
気的特性の優れたコプレーナ電極構造の薄膜トランしス
タの製造方法を提供することにある。The purpose of the present invention is to provide a method for manufacturing a thin film transistor with a coplanar electrode structure that eliminates the above drawbacks, has low leakage current, high voltage resistance, and has an insulator layer with high durability and excellent electrical characteristics. It is about providing.
本発明の薄膜トランジスタの製造方法は、絶縁体基板の
上にシリコン半導体層を形成する工程と、該シリコン半
導体層の上に所定間隔をおいてソース電極とドレイン電
極とを形成する工程と、前記シリコン半導体層の表面層
を直接プラズマ酸化して酸化物の絶縁体層を形成すると
同時に前記ソース電極及びドレイン電極の表面層を直接
陽極プラズマ酸化して酸化物の絶縁体層を形成する工程
と、前記絶縁体層の上にかつ前記ソース電極とドレイン
電極とに両端近傍が重畳するようにゲート電極を形成す
る工程とを含んで構成される。The method for manufacturing a thin film transistor of the present invention includes a step of forming a silicon semiconductor layer on an insulating substrate, a step of forming a source electrode and a drain electrode at a predetermined interval on the silicon semiconductor layer, and a step of forming a silicon semiconductor layer on the silicon semiconductor layer. Direct plasma oxidation of the surface layer of the semiconductor layer to form an oxide insulator layer, and at the same time direct anodic plasma oxidation of the surface layer of the source electrode and the drain electrode to form the oxide insulator layer; The method includes the step of forming a gate electrode on the insulating layer so that the vicinity of both ends thereof overlap the source electrode and the drain electrode.
次に、本発明の実施例について図面を用・いて説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第5図は本発明の一実施例を説明するための薄膜トラン
ジスタの断面図である。FIG. 5 is a sectional view of a thin film transistor for explaining one embodiment of the present invention.
絶縁体基板1にバリウム硼珪酸ガラスを用いるが、これ
に限定される訳ではなく、他の絶縁体の基板でも使用で
きることはもちろんである。絶縁体基板1の上化シリコ
ン半導体層4を形成する。Although barium borosilicate glass is used for the insulator substrate 1, it is not limited thereto, and it goes without saying that substrates made of other insulators can also be used. A silicon semiconductor layer 4 on top of the insulator substrate 1 is formed.
低圧プラズマ放電分解法を用いると非晶質のシリコン半
導体層が得られる。形成条件の一例を示すと、シラン流
量20 cc/n1in、水素流量f3 Q cc/m
In、圧力0.3torr、 高周波電力50W、基
板温度300℃である。シリコン半導体層4は非晶質に
限定されず、多結晶でも良いことはもちろんである。An amorphous silicon semiconductor layer can be obtained using a low-pressure plasma discharge decomposition method. An example of the formation conditions is silane flow rate 20 cc/n1in, hydrogen flow rate f3 Q cc/m
In, the pressure was 0.3 torr, the high frequency power was 50 W, and the substrate temperature was 300°C. The silicon semiconductor layer 4 is not limited to being amorphous, and may of course be polycrystalline.
次に、シリコン半導体層4の上置所定間隔をおいてソー
ス電極5.ドレイン電極6を形成する。Next, a source electrode 5. is placed above the silicon semiconductor layer 4 at a predetermined interval. A drain electrode 6 is formed.
電極材料は陽極酸化できる金属を用いる。陽極酸化でき
る金属にはkl、8i、Ta、Nb等多数あるが、この
実施例ではAtを使用することにする。The electrode material uses a metal that can be anodized. There are many metals that can be anodized, such as Kl, 8i, Ta, and Nb, but in this example, At will be used.
尚、後の工程で高温熱処理を行う場合には融点の高い陽
極酸化可能な金属を選ぶ必要がある。Note that when high-temperature heat treatment is performed in a later step, it is necessary to select a metal that has a high melting point and can be anodized.
次に、プラズマ陽極酸化法を用いてシリコン半導体層4
の表面を直接陽極プラズマ酸化して酸化シリコン層7を
形成するのと同時にソース電極5及びドレイン電極6の
、表面を直接陽極酸化して酸化アルミニウムの絶縁体層
8,9を形成する。プラズマ陽極酸化の一例を示すと、
酸素流量 200cc/mln、圧力0.5torr、
高周波電力100W。Next, a silicon semiconductor layer 4 is formed using plasma anodic oxidation.
At the same time, the surfaces of the source electrode 5 and drain electrode 6 are directly anodized to form aluminum oxide insulator layers 8 and 9. An example of plasma anodization is:
Oxygen flow rate 200cc/mln, pressure 0.5torr,
High frequency power 100W.
基板温度300℃である。ソース電極5とドレイン電極
6との間の酸化シリコン層7の上から酸化アルミニウム
8. 9の上にかかるようにゲート電極2を形成する。The substrate temperature is 300°C. Aluminum oxide 8. from above silicon oxide layer 7 between source electrode 5 and drain electrode 6. A gate electrode 2 is formed so as to cover the gate electrode 9.
これによりコプレーナ電極構造の薄膜トランジスタが得
られる。As a result, a thin film transistor with a coplanar electrode structure is obtained.
このよ、うにして製造された薄膜トランジスタは、ゲー
ト電極2とソース電極5.ドレイン電極6との間で漏洩
電流が少なく、すべての素子でゲート電圧10Vのとき
1O−12A以下であった。また、耐電圧性が高くゲー
ト電圧20■、ソース・ドレイン間電圧20Vを印加し
た場合にも絶縁破轡を起すものはなかった。各素子とも
ゲート竜・圧10 ′■、ソース・ドレイン間電圧10
Vのオン状態で。The thin film transistor thus manufactured has a gate electrode 2, a source electrode 5. The leakage current between the drain electrode 6 and the drain electrode 6 was small, and was less than 1O-12A when the gate voltage was 10V in all devices. In addition, the voltage resistance was high, and no insulation failure occurred even when a gate voltage of 20 cm and a source-drain voltage of 20 V were applied. Gate voltage 10'■, source-drain voltage 10 for each element
With V on.
106Ω以下の抵抗であり、ゲート電圧Ov、ソース・
ドレイン間電圧10vのオフ状態で1010Ω以上と液
晶素子のスイッチングに十分な値であ 。The resistance is 106Ω or less, and the gate voltage Ov, source voltage
In the off-state with a drain-to-drain voltage of 10 V, the resistance is 1010 Ω or more, which is sufficient for switching the liquid crystal element.
つた。また、電気的特性にドリフトやヒステリシスは全
(見られなかった。これは半導体層を直接プラズマ酸化
させると同時にソース電極とドレイン電極を直接プラズ
マ陽極酸化するため、絶縁体層と半導体層との界面での
準位が少ないこと、ゲート電極と半導体層との間の絶縁
膜が薄いのにもかかわらず、ソース電極およびドレイン
電極とゲート電極との間の絶縁物を厚くできしかもソー
ス電極とドレイン電極の端を完全に絶縁体層により被覆
したためと考えられる。Ivy. In addition, no drift or hysteresis was observed in the electrical characteristics.This is because the semiconductor layer is directly plasma oxidized and at the same time the source and drain electrodes are directly plasma anodized. Despite the fact that there are few levels at This is thought to be due to the fact that the edges of the insulator were completely covered with an insulator layer.
以上詳細に説明したように、本発明によれば、絶縁体層
がシリコン゛半導体層及びソース電極、ドレイン電極の
プラズマ酸化により形成されるので、絶縁体層中への水
素の混入がなく、またゲート電極と半導体層との間の絶
縁体層を薄くして動作ゲート電圧を低くしてもゲート電
極とソース電極及びドしイシ電極との間の絶縁体層を厚
くして漏洩電流を低く抑えることができ、また、電気的
特性番こドリフトやヒステリシスなどがなく安定性、信
頼性の高い薄膜トランジスタが得られrのでその効果は
大中い。As explained in detail above, according to the present invention, since the insulating layer is formed by plasma oxidation of the silicon semiconductor layer and the source and drain electrodes, no hydrogen is mixed into the insulating layer. Even if the insulator layer between the gate electrode and the semiconductor layer is made thinner to lower the operating gate voltage, the insulator layer between the gate electrode and the source and drain electrodes is made thicker to keep leakage current low. In addition, a thin film transistor with high stability and reliability without electrical characteristic drift or hysteresis can be obtained, so the effect is very large.
第1図は従来のスタガ電極構造の薄膜トランジスタの一
例の断面図、第2図は従来のスタガ電極構造の薄膜トラ
ンジスタの他の例の断面図、第3図は従来のコプレーナ
電極構造の薄膜トランジスタの一例の断面図、第4図は
従来のコプレーナ電極構造の薄膜トランジスタの他の例
の断面図、第5図は本発明の一実施例を説明するための
薄膜トランジスタの断面図である。Figure 1 is a cross-sectional view of an example of a thin film transistor with a conventional staggered electrode structure, Figure 2 is a cross-sectional view of another example of a thin film transistor with a conventional staggered electrode structure, and Figure 3 is a cross-sectional view of an example of a thin film transistor with a conventional coplanar electrode structure. 4 is a sectional view of another example of a conventional thin film transistor having a coplanar electrode structure, and FIG. 5 is a sectional view of a thin film transistor for explaining an embodiment of the present invention.
Claims (1)
、該シリコン半導、体層の上に所定間隔をおいてソース
電極とドレイ、ン電極とを形成する工程と、前記シリコ
ン半導体層の表面層牽直接プラズマ酸化して酸化物の絶
縁体層を!成すると同時に前記ソース電極及びドレイン
電極の表面層を直接陽極プラズマ酸化して酸化物の絶縁
体層を形成する工程と、前記絶縁、体層の上にかつ前記
ソース電極とドレイン電極と壷、こ両端近傍が重畳する
ようにゲート電極を形成する工程とを含むことを特徴と
する薄膜トランジスタの製造方法。a step of forming a silicon semiconductor layer on an insulating substrate; a step of forming a source electrode, a drain electrode, and a drain electrode at predetermined intervals on the silicon semiconductor layer; Direct plasma oxidation of the surface layer to create an oxide insulator layer! At the same time, the surface layer of the source electrode and the drain electrode is directly anodic plasma oxidized to form an oxide insulating layer, and the source electrode, the drain electrode and the pot are formed on the insulating layer and the source electrode and the drain electrode. 1. A method of manufacturing a thin film transistor, comprising the step of forming a gate electrode so that the vicinity of both ends thereof overlap.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12386282A JPS5914673A (en) | 1982-07-16 | 1982-07-16 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12386282A JPS5914673A (en) | 1982-07-16 | 1982-07-16 | Manufacture of thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5914673A true JPS5914673A (en) | 1984-01-25 |
Family
ID=14871221
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12386282A Pending JPS5914673A (en) | 1982-07-16 | 1982-07-16 | Manufacture of thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5914673A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5326712A (en) * | 1991-12-03 | 1994-07-05 | Samsung Electronics Co., Ltd. | Method for manufacturing a thin film transistor |
US5470769A (en) * | 1990-03-27 | 1995-11-28 | Goldstar Co., Ltd. | Process for the preparation of a thin film transistor |
-
1982
- 1982-07-16 JP JP12386282A patent/JPS5914673A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470769A (en) * | 1990-03-27 | 1995-11-28 | Goldstar Co., Ltd. | Process for the preparation of a thin film transistor |
US5326712A (en) * | 1991-12-03 | 1994-07-05 | Samsung Electronics Co., Ltd. | Method for manufacturing a thin film transistor |
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