JPH0487341A - Polycrystalline silicon thin-film transistor - Google Patents

Abstract

PURPOSE:To obtain a substrate at low cost, small coefficient of thermal expansion and which is heat-resistant by a method wherein a material which contains silicon oxide in a specific amount is used as the substrate. CONSTITUTION:As a substrate to form a polycrystalline silicon TFT, a material 7913 which contains about 80 to 99.5% of SiO2 is used. As other compositions, boron oxide, aluminum oxide and barium oxide are contained. As shown in the table, the material is not inferior to a quartz substrate with regard to a coefficient of thermal expansion and the mobility of electrons in a polycrystalline silicon layer for the TFT; the TFT whose cost is about 1/10 of the quartz substrate can be obtained. The mobility of the electrons in the polycrystalline silicon layer of the TFT is decided approximately by a heat- treatment condition to solid-grow an amorphous silicon layer at the manufacturing process of the TFT. It is considered that the mobility is increased by a high-temperature heat treatment.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a polycrystalline silicon thin film transistor (hereinafter referred to as TP).
A substrate for TPT, which is particularly suitable for forming a large number of TPTs on a large-area substrate;

[Conventional technology]

In recent years, research has been progressing on TPT using polycrystalline silicon, which is useful as a drive switch element for liquid crystal display devices and a drive circuit element for contact image sensors.

A quartz substrate has conventionally been used as a substrate for forming TPT using polycrystalline silicon.

Recently, polycrystalline silicon TP can be used even in manufacturing processes at temperatures below 600°C.
It has become possible to create T, and a low-cost glass substrate 2 such as Corning 7059 (product number) manufactured by Corning Corporation has come to be used.

[Problem to be solved by the invention]

However, since the TPT manufacturing process involves repeating heat treatment and mask patterning multiple times, problems arise especially when creating a large number of polycrystalline silicon TPTs on a large substrate at the same time, especially if the substrate has a large coefficient of thermal expansion. will occur.

That is, when patterning and heat treatment are repeated multiple times, the thermally expanded substrate does not return to its original state (2).

The next mask alignment will be performed, and the mask alignment will become inaccurate, resulting in a significant deterioration in product yield.

As shown in Table 1 below, glass substrates have thermal expansion coefficients that are one order of magnitude higher than those of quartz substrates, and are more likely to cause the above-mentioned problems.

On the other hand, if a quartz substrate is used, the above problems are solved, but the high cost of quartz increases the cost of the product, making it particularly unsuitable for large-area substrates. provides a polycrystalline silicon TPT substrate that is low cost, has a small coefficient of thermal expansion, and is heat resistant.

[Means to solve the problem]

In order to achieve the above object, the inventors of the present invention have conducted extensive research,
As a substrate for polycrystalline silicon TPT.

Use a material containing 80 to 99.5% Sigh; it has a small coefficient of thermal expansion similar to the 2-2 quartz substrate.

We have discovered that it is possible to create a product that is heat resistant and at a much lower cost than a quartz substrate.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a cross-sectional structural diagram of the TPT of the present invention, and FIG. 2 is a sectional view of the TPT of the present invention.
It is a manufacturing process explanatory diagram of T.

In the figure, 1 is a substrate made of the material of the present invention, 2 is a polycrystalline silicon film, and 2-1, 2-2 are n+ type regions, which act as a source region and a drain region, respectively. 3 is a gate oxide film, 4 is a gate electrode, 5 is silicon oxide (SiOz)
6 is an aluminum (AJ) wiring layer, 7 is a silicon nitride film, and 8 is a 5i (h film).

In the present invention, a material 2 containing approximately 80 to 99.5% 8i (h), for example, a substrate manufactured by Corning Corporation, product number 7913, is used as a substrate for producing a polycrystalline silicon TPT. The composition is boron oxide (
BzOs), aluminum oxide (klxOs),
Contains barium oxide (Bad).

The materials of the present invention are shown in Table 1 (-coefficient of thermal expansion as shown).

The electron mobility in the polycrystalline silicon layer of TPT is 2.
It is possible to obtain a TPT that is comparable to the case where a quartz substrate is used, and costs about 1/2 of the cost of a quartz substrate.

The mobility is determined by the heat treatment conditions during the solid phase growth of the amorphous silicon layer in the TPT manufacturing process (2) described below, and it is thought that heat treatment at high temperature increases the mobility. Table 2 shows the solid phase growth conditions for each substrate material.

As is clear from Table 2, by using the substrate of the present invention (=2), it is possible to perform heat treatment at high temperatures during in-phase growth, similar to the quartz substrate, thereby increasing the mobility of electrons in the polycrystalline silicon layer. 2. The characteristics of the TPT obtained by the present invention can be improved.

Note that the content of 5iOz in the substrate used in the present invention is as follows.

If it is less than 80%, the coefficient of thermal expansion will be too large,
99.5% or more; otherwise, the cost of the material becomes too expensive.

Next, the manufacturing process of the polycrystalline silicon TPT of the present invention will be explained with reference to FIG.

(I) Board 1 manufactured by Corning Corporation, product number 7913
Above (2) Deposit an amorphous silicon film at a substrate temperature of about 1000X using a low pressure CVD method at a substrate temperature of 560°C.Next, deposit this amorphous silicon film at 600°C in an N293 atmosphere.
After the heat treatment for 0 hour, the polycrystalline silicon film 2 is further heat treated at 950° C. for 1 hour to achieve solid phase growth.

(II) This polycrystalline silicon film 2 (patterned using second photolithography and etched into an island shape (see FIG. 2(a)).

1) Next, a gate oxide film 3 made of 8i (h) is formed to a thickness of about 500X, for example, by sputtering.

Polycrystalline silicon film 4' is deposited by low pressure CVD method to
00-3000X deposit.

Side These two layers are patterned using a second photomask to form the gate electrode 4 (Fig. 2 (1))
reference).

Using the formed gate electrode 4 as a mask, phosphorus (P) ions are implanted by a self-alignment method to form the source region 2-1.
．． A drain region 2-2 is formed.

(Capital) Furthermore, the activation of the implanted P ions was
℃ in a nitrogen atmosphere; 8i (
An interlayer insulating film 5 made of an H film is formed to a thickness of about 1000× (see FIG. 2(C)).

(2) This interlayer insulating film 5 is patterned using a third photomask to form a contact window.

The M layer is formed by vapor deposition or sputtering.

Sinter at approximately 450°C for 30 minutes.

The 61DAJ layer is patterned using a fourth photomask to form the +AJ wiring layer 6 (see FIG. 2(d)).
.

■ Plasma CVD silicon nitride film 7 for hydrogenation
Deposit 1, for example, 2000X using a method (see Figure 2(e)).
.

(3) Next, using the ozone CVD method using tetraethoxysilane (TEO8'), a dense 5iC with few pinholes was formed.
After depositing the h film 8, heat treatment is performed, hydrogenation treatment is performed, and the first
The TPT has a structure as shown in the figure.

As is clear from the manufacturing process of the above example, patterning was performed using a photomask four times to create the polycrystalline silicon TPT (steps II and IV).

(see ■, ■), heat treatment at least six times (step I).

(see (1), (2), and In particular, inconveniences are likely to occur when a large number of TPTs are produced using a large-area substrate, but these problems can be solved by using the substrate of the present invention.

In addition, in the above-mentioned example, in the manufacturing process of polycrystalline silicon TPT, the protective film is made into two layers and the hydrogenation treatment is performed (although two layers were explained, the present invention is not limited to this, and Needless to say, it can be manufactured using other processes, such as a method of performing a chemical treatment and forming an interlayer insulating film made of a silicon oxide film.

〔Effect of the invention〕

As a substrate for manufacturing polycrystalline silicon TPT as in the present invention, a substrate with a high content of Si02 of 80 to 99.5% is used (secondly, because it has a small coefficient of thermal expansion and is heat resistant, it is better to use a substrate than a conventional glass substrate). Mask alignment is easier and more accurate than when using a glass substrate.Therefore, product characteristics and yield can be significantly improved.Furthermore, the electron mobility can also be made higher than when using a glass substrate. Therefore, from this point of view as well, it has high performance.

Moreover, since the cost of the substrate is low, it is approximately 1/□ compared to the conventionally used quartz substrate. It can be manufactured at a cost of

These effects are particularly noticeable when a large-area substrate is used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional structural diagram of the polycrystalline silicon TPT of the present invention. FIG. 2 is an explanatory diagram of the manufacturing process of TPT of the present invention. 0 1...Substrate of the present invention, 2... Polycrystalline silicon film. 2-1.2-2... Source, drain region. 3... Gate oxide film, 4... Gate electrode. 5... Interlayer insulating film, 6... M wiring layer. 7...Silicon nitride film, 8...8i (h[. Patent applicant: TDT-K Co., Ltd., patent attorney, Akira Yamatani (1 other person) Figure 2

Claims (1)

[Claims] As a substrate, 80-99.5% silicon oxide (SiO
A polycrystalline silicon thin film transistor characterized by using a material containing __2).