JPS6390857A - Thin film transistor - Google Patents

Thin film transistor

Info

Publication number
JPS6390857A
JPS6390857A JP23647886A JP23647886A JPS6390857A JP S6390857 A JPS6390857 A JP S6390857A JP 23647886 A JP23647886 A JP 23647886A JP 23647886 A JP23647886 A JP 23647886A JP S6390857 A JPS6390857 A JP S6390857A
Authority
JP
Japan
Prior art keywords
thin film
insulating film
gate insulating
film
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23647886A
Other languages
Japanese (ja)
Other versions
JPH0797640B2 (en
Inventor
Koji Nomura
幸治 野村
Masaharu Terauchi
正治 寺内
Kuni Ogawa
小川 久仁
Atsushi Abe
阿部 惇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23647886A priority Critical patent/JPH0797640B2/en
Publication of JPS6390857A publication Critical patent/JPS6390857A/en
Publication of JPH0797640B2 publication Critical patent/JPH0797640B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain a thin-film transistor whose characteristics are stable for a long period of time and which can be manufactured with good reproducibility, by producing a gate insulation film as a multilayered film consisting of an insulating film provided by a sputtered composite oxide thin film principally composed of aluminium and tantalum and of another insulating film provided by a sputtered thin film of insulator principally composed of silicon. CONSTITUTION:A gate insulation film is a multilayered film consisting of a first gate insulation film 3 provided by a sputtered composite oxide thin film principally composed of aluminium and tantalum, and a second gate insulating film 4 disposed between said first gate insulating film 3 and a semiconductor layer 5 and principally composed of silicon. For example, on an insulating substrate 1 of glass or the like, there are provided a gate electrode 2 of aluminium, a first gate insulating film 3 of Al and Ta composite oxide film formed by the high-frequency magnetron sputtering process, a second gate insulating film 4 of SiO2 also formed by the high-frequency magnetron sputtering process, a semiconductor layer 5 of CdSe, and source and drain electrodes 6 and 7 of aluminium.

Description

【発明の詳細な説明】 産業上の利用分野 この発明は、薄膜トランジスタに関し、特にゲート絶縁
膜と半導体層との界面に起因する薄膜トランジスタ特性
の不安定性が改良された薄膜トランジスタに関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film transistor, and more particularly to a thin film transistor in which instability in thin film transistor characteristics caused by an interface between a gate insulating film and a semiconductor layer is improved.

従来の技術 薄膜トランジスタは、ソース・ドレイン電極間の半導体
の電気伝導度を半導体と接する絶縁体層を介して設けら
れた第3の電極(ゲート電極)に印加する電圧によって
制御するいわゆる電界効果型トランジスタとして知られ
ている。従来薄膜トランジスタは、大面積に渡ってスイ
ッチングアレーを形成し易い点、あるいは材料が安価な
ため低コストになり得るなどの点でイメージセンサある
いは液晶やEL表示装置等のスイッチングアレーを目的
に研究が続けられている。このような薄膜トランジスタ
において、最も重要な点は、素子特性の変動がなく長時
間にわ六って安定に動作することである。
Conventional technology A thin film transistor is a so-called field effect transistor in which the electrical conductivity of a semiconductor between source and drain electrodes is controlled by a voltage applied to a third electrode (gate electrode) provided through an insulating layer in contact with the semiconductor. known as. Conventional thin film transistors have been researched for the purpose of switching arrays for image sensors, liquid crystals, EL display devices, etc. because they are easy to form switching arrays over a large area, and because the materials are cheap, they can be made at low cost. It is being The most important point in such thin film transistors is that they operate stably over a long period of time without fluctuations in device characteristics.

薄膜トランジスタ特性の経時変化の原因としては、半導
体薄膜中あるいは半導体薄膜と絶縁体層との界面あるい
は絶縁体層中にあって電子を捕獲することのできる電荷
トラップによるものと考えられている。この内、絶縁体
層に存在する電荷トラップは他の電荷トラップに比べて
その数が多く、また、絶縁体層中の伝導度が低いため通
常長い緩和時間を必要とすることから、薄膜トランジス
タ特性の長期的な経時変化の主たる要因であると考えら
れている。絶縁体層内部に電荷トラップが多く存在した
り、絶縁体層のリーク電流が大きいと、半導体層と絶縁
体層との界面に形成されたチャンネル中を移動する電子
が絶縁体層中に引き込まれ、電荷トラップに捕獲されて
しまい、実効的なゲート電圧が変化してドレイン電圧が
変化してドレイン電流が変動したりする。以上の点から
安定なトランジスタ特性2有する素子を実現するには、
電荷トラップが少なくリーク電流の少ない薄膜を絶縁体
層として用いることが望ましめ。
The cause of changes in thin film transistor characteristics over time is thought to be due to charge traps that can trap electrons in the semiconductor thin film, at the interface between the semiconductor thin film and the insulator layer, or in the insulator layer. Of these, the number of charge traps that exist in the insulator layer is larger than other charge traps, and because the conductivity in the insulator layer is low, it usually requires a long relaxation time, which affects the characteristics of thin film transistors. It is believed that this is the main cause of long-term changes over time. If there are many charge traps inside the insulator layer or if the leakage current in the insulator layer is large, electrons moving in channels formed at the interface between the semiconductor layer and the insulator layer will be drawn into the insulator layer. , they are captured by a charge trap, and the effective gate voltage changes, the drain voltage changes, and the drain current fluctuates. From the above points, in order to realize an element with stable transistor characteristics 2,
It is desirable to use a thin film with fewer charge traps and less leakage current as the insulator layer.

従来、上記薄膜トランジスタの絶縁体層としては、電子
ビーム蒸着法あるいはスパッタ法で形成したAIOTa
OSiO2,Si3N4等の薄23’     251 膜が用いられていた。
Conventionally, the insulator layer of the above-mentioned thin film transistor is made of AIOTa formed by electron beam evaporation method or sputtering method.
Thin 23' 251 films such as OSiO2 and Si3N4 were used.

発明が解決しようとする問題点 Al2O3やT a 205あるいはそれらの複合絶縁
膜は、高い比誘電率全方するが、一般に他の材料との密
着性が悪ぐ製造工程の途中で物理的にはがれやすく、歩
留シが悪いという欠点があった。また、これらの理由か
ら界面で多くの電荷トラップが発生し、経時変化が大き
いという問題があった。
Problems to be Solved by the Invention Although Al2O3, T a 205, or their composite insulating films have a high dielectric constant, they generally have poor adhesion with other materials and may physically peel off during the manufacturing process. The drawback was that it was easy to use, and the yield was poor. Furthermore, for these reasons, many charge traps are generated at the interface, resulting in a large change over time.

また、S z O2やSi3N4等のシリコンを主成分
とする絶縁膜は、一般に比誘電率が小さく薄膜トランジ
スタの相互コンダクタンス?大きくできないという欠点
があった。
In addition, insulating films whose main component is silicon, such as S z O2 and Si3N4, generally have a small dielectric constant and the mutual conductance of thin film transistors. The drawback was that it could not be made larger.

また、電子ビーム蒸着法により得られる絶縁膜は、高真
空中で蒸着物質が高温に加熱されるため、蒸着時に熱解
離が起こり組成比が化学量論的組成からずれていること
が多く、とくに酸化物の場合には、酸素欠陥ができて、
それが電荷トラップとなるばかりでなくリーク電流が増
加する原因となる。以上のような理由から、従来の薄膜
トランジスタでは経時変化が大きく、相互コンダクタン
スが小さく、再現性に乏しいものしか得られなかった。
In addition, in insulating films obtained by electron beam evaporation, the evaporation material is heated to high temperatures in a high vacuum, so thermal dissociation occurs during evaporation and the composition ratio often deviates from the stoichiometric composition. In the case of oxides, oxygen defects are created,
This not only becomes a charge trap but also causes an increase in leakage current. For the above-mentioned reasons, conventional thin film transistors exhibit large changes over time, low mutual conductance, and poor reproducibility.

そこで、本発明は、以上のような問題点を解決して、長
期にわたり安定した特性を有し、再現性よく製造できる
薄膜トランジスタを提供することを目的としている。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a thin film transistor that has stable characteristics over a long period of time and can be manufactured with good reproducibility.

問題点を解決するための手段 本発明は前記の目的を達成するため、薄膜トランジスタ
において、ゲート絶縁膜が少なくともアルミニウムとタ
ンタルを主成分とする複合酸化物スパッタ薄膜からなる
第1のゲート絶縁膜と前記第1のゲート絶縁膜と前記半
導体層とのmlにあって、少なくともシリコンを主成分
とする絶縁物スパッタ薄膜からなる第2のゲート絶縁膜
との多層膜からなることを特徴としている。
Means for Solving the Problems In order to achieve the above object, the present invention provides a thin film transistor in which the gate insulating film includes a first gate insulating film made of a composite oxide sputtered thin film containing at least aluminum and tantalum as main components; The first gate insulating film and the second gate insulating film are made of an insulating sputtered thin film mainly composed of silicon, and the semiconductor layer is a multilayer film.

作   用 本発明によれば、半導体層に接するゲート絶縁膜として
スパッタにより形成されたシリコンを主成分とする絶縁
物薄膜が用いられており、こ九らの膜は化学量論的組成
からのずれが少なく、したがって欠陥による電荷トラッ
プが少なく、また半導体薄膜及び第1のゲート絶縁膜で
あるアルミニウムとタンタルを主成分とする複合酸化物
スパッタ薄膜の両側に接する薄膜に対して密着性にすぐ
れており界面近傍において欠陥が生成されにくいので、
半導体チャネル中を流れる電子がトラップされにくくな
る。また、多層構造のためピンホール等の欠陥の成長が
途中の界面で断ち切られるためリーク電流が非常に小さ
くなる。また、アルミニウムとタンタルを主成物とする
複合酸化物スパッタ薄膜の比誘電率が大きいため全体と
して容量が犬きくなり、相互コンダクタンスの大きい薄
膜トランジスタとなる。
According to the present invention, an insulating thin film mainly composed of silicon formed by sputtering is used as the gate insulating film in contact with the semiconductor layer, and these films are free from deviations from the stoichiometric composition. Therefore, there are fewer charge traps due to defects, and it has excellent adhesion to the thin films that are in contact with both sides of the semiconductor thin film and the first gate insulating film, a composite oxide sputtered thin film whose main components are aluminum and tantalum. Since defects are less likely to be generated near the interface,
Electrons flowing through the semiconductor channel are less likely to be trapped. Furthermore, due to the multilayer structure, the growth of defects such as pinholes is cut off at intermediate interfaces, so leakage current becomes extremely small. Furthermore, since the composite oxide sputtered thin film mainly composed of aluminum and tantalum has a high dielectric constant, the capacitance as a whole becomes large, resulting in a thin film transistor with high mutual conductance.

以上に述べた作用により本発明の薄膜トランジスタは、
ゲート絶縁膜の構成が、半導体層との界面で電荷トラッ
プが少なく、全体として高い比誘電率を有し、リーク電
流を少なくして因るので、経時変化の小さbものとなる
Due to the above-described effects, the thin film transistor of the present invention has
Since the structure of the gate insulating film has few charge traps at the interface with the semiconductor layer, has a high relative dielectric constant as a whole, and reduces leakage current, it has a small change over time.

実施例 以下、本発明の実施例を添付図面にもとづいて説明する
Embodiments Hereinafter, embodiments of the present invention will be described based on the accompanying drawings.

第1図は本発明の薄膜トランジスタの一実施例を示す断
面図である。
FIG. 1 is a sectional view showing an embodiment of a thin film transistor of the present invention.

ガラス等の絶縁性基板1上に100 n m程度の膜厚
を有するMからなるゲート電極2、さらにそのゲート電
極2を含む絶縁性基板1上に300nm程度の膜厚を有
し、高周波マグネトロンスパッタ法により形成されたA
lとTaとの複合酸化膜からなる第1のゲート絶縁膜3
、さらにその上に30nm程度の膜厚を有し、同様に高
周波マグネトロンスパッタ法により形成された5102
からなる第2のゲート絶縁膜4、この上に50 n m
程度の膜厚を有するCdSeからなる半導体層5、さら
にその上に、数〜数十ミクロンの所定の間隔を隔てて1
00 n m程度の膜厚を有するMからなるソース電極
6及びドレイン電極7から構成されている。
A gate electrode 2 made of M having a film thickness of about 100 nm is formed on an insulating substrate 1 such as glass, and a film thickness of about 300 nm is formed on the insulating substrate 1 including the gate electrode 2, using high-frequency magnetron sputtering. A formed by the law
A first gate insulating film 3 made of a composite oxide film of l and Ta
, and 5102 having a film thickness of about 30 nm thereon, which was also formed by high frequency magnetron sputtering.
A second gate insulating film 4 consisting of
A semiconductor layer 5 made of CdSe having a film thickness of about
It is composed of a source electrode 6 and a drain electrode 7 made of M and having a film thickness of about 0.00 nm.

本発明の薄膜トランジスタの効果を調べるため第1図の
第1のゲート絶縁膜3と第2のゲート絶縁膜4の厚さを
第1表に示す3通シとして、薄膜トランジスタ(I) 
、 (ff) 、(2)を試作した。ここでCI)は上
記で示した本発明の薄膜トランジスタである。
In order to investigate the effect of the thin film transistor of the present invention, the thickness of the first gate insulating film 3 and the second gate insulating film 4 shown in FIG.
, (ff), (2) was prototyped. Here, CI) is the thin film transistor of the present invention shown above.

それぞれのサンプルのチャネル長は1oμm、チャネル
幅は50μmとし友。
The channel length of each sample was 1 μm, and the channel width was 50 μm.

第1表 第2図はゲート電圧を変化させた時のドレイン電流を示
している。図から明らかなように本発明の薄膜トランジ
スタ(I)は、第2のゲート絶縁膜であるS 102が
十分に薄いので(ff)の薄膜トランジスタとほぼ同等
の電気特性が得られ、比誘電率の大きい(εr〜15)
MとTa  との複合酸化物スパッタ薄膜の特長が損わ
れないことを示している。一方@)の薄膜トランジスタ
では、5102の比誘電率が低い(εr〜3.5)ため
大きなドレイン電流を得るためには、大きなゲート電圧
を必要とすることがわかる。
Table 1, Figure 2 shows the drain current when the gate voltage is changed. As is clear from the figure, in the thin film transistor (I) of the present invention, since the second gate insulating film S102 is sufficiently thin, electrical characteristics almost equivalent to those of the thin film transistor (ff) can be obtained, and the dielectric constant is large. (εr~15)
This shows that the features of the composite oxide sputtered thin film of M and Ta are not impaired. On the other hand, it can be seen that in the thin film transistor of @), a large gate voltage is required in order to obtain a large drain current because the dielectric constant of 5102 is low (εr~3.5).

第3図は、第1図でソース電極6とドレイン電極子を共
通電極として、これとゲート電極2との間に電圧全印加
した時のリーク電流を示している。
FIG. 3 shows the leakage current when the source electrode 6 and the drain electrode in FIG. 1 are used as common electrodes and the full voltage is applied between them and the gate electrode 2.

本発明の薄膜トランジスタ(I)では(u)tたば(I
II)の薄膜トランジスタに比べて十分にリーク電流が
小さいことがわかる。これは多層構造のため、スパッタ
時に発生したピンホール等の欠陥が第1のゲート絶縁膜
と第2のゲート絶縁膜との界面で断ち切られる確率が高
くなる息めと考えられる。リーク電流が少ないと絶縁膜
中の電荷トラップに注入される電子の個数も少なくなる
ため、薄膜トランジスタ特性の経時変化を小さくするこ
とができる。
In the thin film transistor (I) of the present invention, (u)t
It can be seen that the leakage current is sufficiently smaller than that of the thin film transistor II). This is considered to be because the multilayer structure increases the probability that defects such as pinholes generated during sputtering will be cut off at the interface between the first gate insulating film and the second gate insulating film. When the leakage current is small, the number of electrons injected into charge traps in the insulating film is also reduced, so that changes over time in thin film transistor characteristics can be reduced.

第4図は(1) 、 (If) 、(7)の薄膜トラン
ジスタについてドレイン電流の経時変化を示したもので
ある。
FIG. 4 shows the change in drain current over time for the thin film transistors (1), (If), and (7).

本発明の薄膜トランジスタ(I)では、経時変化が非常
に少ない。これは、半導体層とゲート絶縁膜との界面近
傍において、非常に密着性がよいため欠陥の発生が少な
く経時変化の主たる原因である電荷トラップの数が非常
に少ないことを意味している。また前述したようにリー
ク電流が少ないため電荷トラップに注入される電子の数
自体が少なくなるためと考えられる。
The thin film transistor (I) of the present invention shows very little change over time. This means that near the interface between the semiconductor layer and the gate insulating film, the adhesion is very good, so there are few defects and the number of charge traps, which is the main cause of aging, is very small. Further, as mentioned above, it is thought that this is because the number of electrons injected into the charge trap is reduced because the leakage current is small.

第1図の第2のゲート絶縁膜として抵抗加熱法や電子ビ
ーム法により作製されたS 102では上記のような特
性は得られずスパッタ薄膜とすることで電荷トラップが
少なくなることがわかる。
It can be seen that the above-mentioned characteristics cannot be obtained with S102, which is produced as the second gate insulating film in FIG. 1 by a resistance heating method or an electron beam method, and charge traps are reduced by forming a sputtered thin film.

第2のゲート絶縁膜の厚さは比誘電率が小さいため、大
きな相互コンダクタンス2得るためには、50 n m
以下であることが望ましい。
The thickness of the second gate insulating film has a small dielectric constant, so in order to obtain a large mutual conductance 2, the thickness of the second gate insulating film is 50 nm.
The following is desirable.

また第2のゲート絶縁膜としてS iO2としたときの
効果は前述した通りであるが、Si3N4としたときに
も同等の特性が得られた。
Further, although the effect when SiO2 is used as the second gate insulating film is as described above, the same characteristics were obtained when Si3N4 is used as the second gate insulating film.

実施例では半導体層としてCdSeを用いた場合につい
て述べたがCdS、CdTeあるL/’1はそれらの固
溶体の場合にも本発明の効果が犬であることがわかった
In the example, the case where CdSe was used as the semiconductor layer was described, but it was found that the effect of the present invention is also effective in the case of solid solutions of CdS and CdTe (L/'1).

発明の効果 以上の説明から明らかなように、本発明の薄膜トランジ
スタでは、ゲート絶縁膜と半導体層との界面において電
荷トラップが少なく、またリーク電流が少ないことから
電荷トラップへの電子の注入そのものがおこりにくいた
め、薄膜トランジスタの電気特性や安定性音大きく改善
することができ、各種表示装置の駆動等に広く利用でき
るものである。
Effects of the Invention As is clear from the above explanation, in the thin film transistor of the present invention, there are few charge traps at the interface between the gate insulating film and the semiconductor layer, and since the leakage current is small, injection of electrons into the charge traps itself occurs. This makes it possible to greatly improve the electrical characteristics and stability of thin film transistors, making them widely applicable to driving various display devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の薄膜トランジスタの一実施例を示す断
面図、第2図は薄膜トランジスタの電気特性を示す図、
第3図はゲート絶縁膜のリーク電流を示す図、第4図は
薄膜トランジスタ特性の経時変化を示す図である。 1・・・・・・絶縁性基板、2・・・・・・ゲート電極
、3・・・・・・第1のゲート絶縁膜(AIとTaとの
複合酸化物スパッタ薄膜)、4・・・・・・第2のゲー
ト絶縁膜(Siの絶縁物スパッタ薄膜)、5・・・・・
・半導体層、6・・・・・・ソース電極、7・・・・・
・ドレイン電極。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名、i
 :z −−’′Xぜ傾云 第3図 (1)−、!9仁・8月 642 刃口 4θ:A(v) 第 4 図
FIG. 1 is a sectional view showing an embodiment of the thin film transistor of the present invention, FIG. 2 is a diagram showing the electrical characteristics of the thin film transistor,
FIG. 3 is a diagram showing leakage current of the gate insulating film, and FIG. 4 is a diagram showing changes in thin film transistor characteristics over time. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Gate electrode, 3... First gate insulating film (sputtered composite oxide thin film of AI and Ta), 4... ...Second gate insulating film (Si insulator sputtered thin film), 5...
- Semiconductor layer, 6... Source electrode, 7...
・Drain electrode. Name of agent: Patent attorney Toshio Nakao and one other person, i
:z −−''Xze tilt Figure 3 (1) −,! 9 Jin/August 642 Blade mouth 4θ:A(v) Fig. 4

Claims (5)

【特許請求の範囲】[Claims] (1)絶縁性基板上に少なくともドレイン電極、ゲート
電極、ソース電極、半導体層およびゲート絶縁膜で構成
され、前記ゲート絶縁膜が少なくともアルミニウムとタ
ンタルを主成分とする複合酸化物スパッタ薄膜からなる
第1のゲート絶縁膜と前記第1のゲート絶縁膜と前記第
1のゲート絶縁膜と前記半導体層との間にあって、少な
くともシリコンを主成分とする絶縁物スパッタ薄膜から
なる第2のゲート絶縁膜との多層膜からなることを特徴
とする薄膜トランジスタ。
(1) A substrate comprising at least a drain electrode, a gate electrode, a source electrode, a semiconductor layer, and a gate insulating film on an insulating substrate, the gate insulating film being a composite oxide sputtered thin film containing at least aluminum and tantalum as main components. a second gate insulating film formed of an insulating sputtered thin film containing at least silicon as a main component, the second gate insulating film being between the first gate insulating film and the first gate insulating film and the first gate insulating film and the semiconductor layer; A thin film transistor characterized by being made of a multilayer film.
(2)第2のゲート絶縁膜の厚さが50nm以下である
ことを特徴とする特許請求の範囲第1項記載の薄膜トラ
ンジスタ。
(2) The thin film transistor according to claim 1, wherein the thickness of the second gate insulating film is 50 nm or less.
(3)第2のゲート絶縁膜が酸化シリコンで構成されて
いることを特徴とする特許請求の範囲第1項記載の薄膜
トランジスタ。
(3) The thin film transistor according to claim 1, wherein the second gate insulating film is made of silicon oxide.
(4)第2のゲート絶縁膜がチッ化シリコンで構成され
ていることを特徴とする特許請求の範囲第1項記載の薄
膜トランジスタ。
(4) The thin film transistor according to claim 1, wherein the second gate insulating film is made of silicon nitride.
(5)半導体層が、CdS、CdSe、CdTe及びそ
れらの固溶体である事を特徴とする特許請求の範囲第1
項記載の薄膜トランジスタ。
(5) Claim 1, characterized in that the semiconductor layer is CdS, CdSe, CdTe, or a solid solution thereof.
The thin film transistor described in Section 1.
JP23647886A 1986-10-03 1986-10-03 Thin film transistor Expired - Lifetime JPH0797640B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23647886A JPH0797640B2 (en) 1986-10-03 1986-10-03 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23647886A JPH0797640B2 (en) 1986-10-03 1986-10-03 Thin film transistor

Publications (2)

Publication Number Publication Date
JPS6390857A true JPS6390857A (en) 1988-04-21
JPH0797640B2 JPH0797640B2 (en) 1995-10-18

Family

ID=17001330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23647886A Expired - Lifetime JPH0797640B2 (en) 1986-10-03 1986-10-03 Thin film transistor

Country Status (1)

Country Link
JP (1) JPH0797640B2 (en)

Also Published As

Publication number Publication date
JPH0797640B2 (en) 1995-10-18

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