JPS63216378A - Thin film transistor - Google Patents

Thin film transistor

Info

Publication number
JPS63216378A
JPS63216378A JP5055987A JP5055987A JPS63216378A JP S63216378 A JPS63216378 A JP S63216378A JP 5055987 A JP5055987 A JP 5055987A JP 5055987 A JP5055987 A JP 5055987A JP S63216378 A JPS63216378 A JP S63216378A
Authority
JP
Japan
Prior art keywords
film
thin film
gate insulating
insulating film
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5055987A
Other languages
Japanese (ja)
Other versions
JPH084144B2 (en
Inventor
Koji Nomura
幸治 野村
Masaharu Terauchi
正治 寺内
Mikihiko Nishitani
幹彦 西谷
Yoichi Harada
洋一 原田
Kuni Ogawa
小川 久仁
Noboru Yoshigami
由上 登
Kenji Kumabe
隈部 建治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic System Solutions Japan Co Ltd
Panasonic Holdings Corp
Original Assignee
Matsushita Graphic Communication Systems Inc
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Graphic Communication Systems Inc, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Graphic Communication Systems Inc
Priority to JP5055987A priority Critical patent/JPH084144B2/en
Publication of JPS63216378A publication Critical patent/JPS63216378A/en
Publication of JPH084144B2 publication Critical patent/JPH084144B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To have stable characteristics for a long period and manufacture a favorably reproducible gate insulating film, by causing its film to be composed of a multilayer film which is constructed by a composite insulating material spatter thin film comprising aluminum and tantalum at least as principal ingredients as well as the composite insulating material spatter thin film comprising tantalum and silicon at least as the principal ingredients. CONSTITUTION:Gate insulating films 3 and 4 in a thin film transistor which are constructed by drain, gate, and source electrodes 7, 2, and 6 respectively and a semiconductor film 5 as well as gate insulating films 3 and 4 at least that are mounted on an insulating substrate 1 are composed of a multilayer film which is constructed by the first gate insulating film 3 consisting of a composite insulating material spatter thin film comprising aluminum and tantalum at least as principal ingredients as well as the second gate film 4 consisting of the composite insulating material spatter thin film that is positioned between the above first gate insulating film 3 and the semiconductor film 5 and comprises tantalum and silicon at least as the principal ingredients. In this way, the gate insulating film has a little charge trap at an interface between its insulating film and the semiconductor film and has a high dielectric constant as a whole and then its leakage current is so limited that the thin film transistor having a little change with elapsed time is obtained.

Description

【発明の詳細な説明】 産業上の利用分野 この発明は、薄膜トランジスタ、特にゲート絶縁膜と半
導体膜との界面に起因する薄膜トランジスタ特性の不安
定性が改良された薄膜トランジスタに関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film transistor, and particularly to a thin film transistor in which instability in thin film transistor characteristics caused by an interface between a gate insulating film and a semiconductor film is improved.

従来の技術 薄膜トランジスタは、ソース・ドレイン電極間の半導体
の電気型導度を半導体と接する絶縁膜を介して設けられ
た第三の電極(ゲート電極)に印加する電圧によって制
御する、いわゆる電界効果型トランジスタとして知られ
ている。従来薄膜トランジスタは、大面積に渡ってスイ
ッチングアレーを形成し易い点、あるいは材料が安価な
ため低コストになり得るなどの点でイメージセンサある
いは液晶やEL表示装置等の駆動回路やスイッチングア
レーを目的に研究が続けられている。このような薄膜ト
ランジスタにおいて、最も重要な点は、素子特性の変動
がなく長時間にわたって安定に動作することである。
Conventional technology Thin film transistors are so-called field effect type transistors in which the electric conductivity of a semiconductor between source and drain electrodes is controlled by a voltage applied to a third electrode (gate electrode) provided through an insulating film in contact with the semiconductor. Also known as a transistor. Conventionally, thin film transistors have been used for driving circuits and switching arrays for image sensors, liquid crystals, EL display devices, etc. because they are easy to form switching arrays over a large area, and because the materials are cheap, they can be made at low cost. Research continues. The most important point in such thin film transistors is that they operate stably over a long period of time without fluctuations in device characteristics.

薄膜トランジスタ特性の経時変化の原因としては、半導
体膜中あるいは半導体膜とゲート絶縁膜との界面あるい
はゲート絶縁膜中にあって電子を捕獲することのできる
電荷トラップによるものと考えられている。この内、ゲ
ート絶縁膜中に存在する電荷トラップは他の電荷トラッ
プに比べてその数が多く、また、絶縁膜中の伝導度が低
いため通常長い緩和時間を必要とすることから、薄膜ト
ランジスタ特性の長期的な経時変化の主たる原因である
と考えられている。絶縁膜中に電荷トラップが多(存在
したり、絶縁膜のリーク電流が大きいと、半導体膜と絶
縁膜との界面に形成されたチャネル中を移動する電子が
絶縁膜中に引き込まれ、電荷トラップに捕獲され、実効
的なゲート電圧が変化してドレイン電流が変動したりす
る。以上の点から安定なトランジスタ特性を有する素子
を実現するには、電荷トラップが少なくリーク電流の少
ない絶縁膜をゲート絶縁膜として用いることが望ましい
The cause of changes in thin film transistor characteristics over time is thought to be due to charge traps that can trap electrons in the semiconductor film, at the interface between the semiconductor film and the gate insulating film, or in the gate insulating film. Of these, the number of charge traps that exist in the gate insulating film is larger than other charge traps, and because the conductivity in the insulating film is low, it usually requires a long relaxation time, which affects the characteristics of thin film transistors. It is thought to be the main cause of long-term changes over time. If there are many charge traps in the insulating film, or if the leakage current in the insulating film is large, electrons moving in channels formed at the interface between the semiconductor film and the insulating film will be drawn into the insulating film, causing charge traps. The effective gate voltage changes and the drain current fluctuates.From the above points, in order to realize a device with stable transistor characteristics, it is necessary to use an insulating film with fewer charge traps and less leakage current at the gate. It is desirable to use it as an insulating film.

従来、上記薄膜トランジスタのゲート絶縁膜としては、
電子ビーム蒸着法あるいはスパッタ法で形成したA12
0G、Ta206.5i02.5iaNa等の薄膜が用
いられていた。
Conventionally, the gate insulating film of the above thin film transistor is
A12 formed by electron beam evaporation method or sputtering method
Thin films such as 0G, Ta206.5i02.5iaNa, etc. were used.

発明が解決しようとする問題点 A l 203やTa205あるいはそれらの複合絶縁
膜は、高い比誘電率を有するが、一般に他の材料との密
着性が悪く製造工程の途中で物理的にはがれやす(、歩
留まりが悪いという欠点があった。また、これらの理由
から界面で多(の電荷トラップが発生し、経時変化が大
きいという問題があった。また、5i02や5iaN4
等のシリコンを主成分とする絶縁膜は、一般に比誘電率
が小さく 4 m トランジスタの相互コンダクタンス
を大きくできないという欠点があった。また、電子ビー
ム蒸着法により得られる絶縁膜は、高真空中で・蒸着物
質が高温に加熱されるため、蒸着時に熱解離が起こり組
成比が化学i論的組成からずれていることが多(、特に
酸化物の場合には、酸素欠陥ができて、それが電荷トラ
ップとなるばかりでなくリーク電流が増加する原因とな
る。以上のような理由から、従来の薄膜トランジスタで
は経時変化が大きく、相互コンダクタンスが小さく、再
現性に乏しいものしか得られなかった。
Problems to be Solved by the Invention Al 203, Ta 205, or their composite insulating films have a high dielectric constant, but they generally have poor adhesion to other materials and are easily peeled off during the manufacturing process ( , had the disadvantage of poor yield. In addition, for these reasons, there was a problem that many charge traps occurred at the interface, and the change over time was large. In addition, 5i02 and 5iaN4
Insulating films whose main component is silicon, such as 4 m , generally have a small dielectric constant and have the disadvantage that the mutual conductance of a 4 m transistor cannot be increased. In addition, insulating films obtained by electron beam evaporation are heated in high vacuum to high temperatures, so thermal dissociation occurs during evaporation and the composition ratio often deviates from the stoichiometric composition ( , especially in the case of oxides, oxygen vacancies are formed, which not only act as charge traps but also cause an increase in leakage current.For the reasons mentioned above, conventional thin film transistors undergo large changes over time and The conductance was small and the reproducibility was poor.

そこで、本発明は、以上のような問題点を解決して、長
期にわたり安定した特性を有し、再現性よく製造できる
薄膜トランジスタを提供することを目的としている。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a thin film transistor that has stable characteristics over a long period of time and can be manufactured with good reproducibility.

問題点を解決するための手段 本発明は前記の目的を達成するため、薄膜トランジスタ
において、ゲート絶縁膜が、少なくともアルミニウムと
タンタルとを主成分とする複合絶縁物スパッタ薄膜から
なる第1のゲート絶縁膜と、前記第1のゲート絶縁膜と
半導体膜との間にあって少なくともタンタルとシリコン
とを主成分とする複合絶縁物スパッタ薄膜からなる第2
のゲート絶縁膜との多層膜とからなることを特徴として
いる。
Means for Solving the Problems In order to achieve the above object, the present invention provides a thin film transistor in which the gate insulating film is a first gate insulating film made of a composite insulating sputtered thin film containing at least aluminum and tantalum as main components. and a second sputtered thin film of a composite insulator which is located between the first gate insulating film and the semiconductor film and whose main components are at least tantalum and silicon.
It is characterized by being composed of a multilayer film including a gate insulating film and a gate insulating film.

作用 本発明によれば、半導体膜に接するゲート絶縁膜として
スパッタ法により形成されたタンタルとシリコンとを主
成分とする絶縁物薄膜が用いられており、これらの膜は
化学量論的組成からのずれが少な(、シたがって欠陥に
よる電荷トラップが少な(、また第1のゲート絶縁膜で
あるアルミニウムとタンタルとを主成分とする複合絶縁
物スパッタ薄膜と一部組成が共通であるため、密着性に
優れており界面近傍において欠陥が生成されにくいので
、半導体チャネル中を流れる電子が]・ラップされに(
くなる。また、第2のゲート絶縁膜であるタンタルとシ
リコンとを主成分とする複合絶縁物スパッタ薄膜は、半
導体膜との密着性に優れている。また、多層構造のため
ピンホール等の欠陥の成長が途中の界面で断ち切られる
ためリーク電流が非常に小さくなる。また、アルミニウ
ムとタンタルとを主成分とする複合絶縁物スパッタ薄膜
と同様にタンタルとシリコンとを主成分とする複合絶縁
物スパッタ薄膜も、比誘電率がシリコンのみを主成分と
する絶縁膜よりも大きいため、全体として容量が大きく
なり、相互コンダクタンスの大きい薄膜トランジスタと
なる。
According to the present invention, an insulating thin film mainly composed of tantalum and silicon formed by sputtering is used as the gate insulating film in contact with the semiconductor film, and these films have a stoichiometric composition. There is little misalignment (therefore, there are fewer charge traps due to defects), and because the composition is partially the same as the first gate insulating film, a composite insulator sputtered thin film whose main components are aluminum and tantalum, it is possible to achieve close contact. Because it has excellent properties and is difficult to generate defects near the interface, the electrons flowing in the semiconductor channel are not wrapped.
It becomes. Further, the second gate insulating film, a composite insulating sputtered thin film mainly composed of tantalum and silicon, has excellent adhesion to the semiconductor film. Furthermore, due to the multilayer structure, the growth of defects such as pinholes is cut off at intermediate interfaces, so leakage current becomes extremely small. In addition, similar to the composite insulator sputter thin film mainly composed of aluminum and tantalum, the composite insulator sputtered thin film mainly composed of tantalum and silicon also has a relative permittivity higher than that of an insulating film mainly composed only of silicon. Since it is large, the overall capacitance is large, resulting in a thin film transistor with large mutual conductance.

以上に述べた作用により本発明の薄膜トランジスタは、
ゲート絶縁膜の構成が、半導体膜との界面で電荷トラッ
プが少なく、全体として高い比誘電率を有し、リーク電
流を少なくしているので、経時変化の小さいものとなる
Due to the above-described effects, the thin film transistor of the present invention has
Since the structure of the gate insulating film has few charge traps at the interface with the semiconductor film, has a high relative dielectric constant as a whole, and reduces leakage current, it has a small change over time.

実施例 以下、本発明の実施例を添付図面にもとすいて説明する
Embodiments Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

第1図は本発明の薄膜]・ランジスタの一実施例を示す
断面図である。
FIG. 1 is a sectional view showing an embodiment of the thin film transistor of the present invention.

ガラス等の絶縁11基板1上に、1100n程度の膜厚
を有するAIからなるゲート電極2が設けられている。
A gate electrode 2 made of AI having a thickness of about 1100 nm is provided on an insulating 11 substrate 1 made of glass or the like.

さらにそのゲート電極2を含む絶縁性基板1上に、30
0 n m程度の膜厚を有し、高周波マグネトロンスパ
ッタ法により形成された、A1とTaとの複合絶縁膜か
らなる第1のゲート絶縁膜3、さらにその上に30nm
程度の膜厚を仔し、同様に高周波マグネトロンスパッタ
法により形成されたT aとSiとの腹合絶縁膜からな
る第2のゲート絶縁膜4が設けられている。この上に5
0nm程度の膜厚を有し、抵抗加熱法により形成された
CdSeからなる半導体膜5、さらにその上に、数〜数
十ミクロンの所定の間隔を隔てて1100n程度の膜厚
を有するAIからなるソース電極6及びドレイン電極7
が設けられている。
Further, on the insulating substrate 1 including the gate electrode 2, 30
A first gate insulating film 3 made of a composite insulating film of A1 and Ta having a film thickness of about 0 nm and formed by high frequency magnetron sputtering, and a 30 nm thick film formed on the first gate insulating film 3
A second gate insulating film 4 is provided which is made of a diagonal insulating film of Ta and Si, which is similarly formed by high-frequency magnetron sputtering and has a thickness of about 100 mL. 5 on top of this
A semiconductor film 5 made of CdSe having a film thickness of about 0 nm and formed by a resistance heating method, and further made of AI having a film thickness of about 1100 nm at predetermined intervals of several to several tens of microns thereon. Source electrode 6 and drain electrode 7
is provided.

複合絶縁膜は、たとえばTaの板の上に多数の穴を有す
るAIの板を重ねたターゲットをスパッタすることによ
り得られる。
The composite insulating film can be obtained, for example, by sputtering a target in which an AI plate having a large number of holes is stacked on a Ta plate.

第2図は第2のゲート絶縁膜中のTa20 sと5i0
2の分子比率を変化させたときの比誘電率を示しており
、本実施例では比誘電率が15となる条件を選んだ。
Figure 2 shows Ta20s and 5i0 in the second gate insulating film.
The graph shows the dielectric constant when the molecular ratio of 2 is changed, and in this example, conditions were selected where the dielectric constant was 15.

本発明の薄膜トランジスタの効果を調べるため第1図の
第1のゲート絶縁膜3と第2のゲート絶縁膜4の厚さを
変えて、第1表に示すように薄膜トランジスタ(A) 
、(B) 、’(C) 、(D>を試作した。また、薄
膜トランジスタ(D)は第2のゲート絶縁膜をSiO2
とした。ここで(A)は上記で示した本発明の薄膜トラ
ンジスタである。
In order to investigate the effect of the thin film transistor of the present invention, the thickness of the first gate insulating film 3 and the second gate insulating film 4 in FIG.
, (B), '(C), and (D> were prototyped. In addition, the thin film transistor (D) has a second gate insulating film made of SiO2.
And so. Here, (A) is the thin film transistor of the present invention shown above.

それぞれのザンブルのチャネル長は10μm1チヤネル
幅は50μmとした。
The channel length of each tumble was 10 μm and the width of one channel was 50 μm.

第1表 第3図はゲート電圧を変化させたときのドレイン電流を
示している。図から明らかなように本発明の薄膜トラン
ジスタ(A)は、第2のゲート絶縁膜であるTaとSi
との複合絶縁膜の比誘電率が比較的大きいため、(B)
の薄膜トランジスタとほぼ同等の電気特性が得られ、比
誘電率の大きいAIとTaとの複合絶縁物スパッタ薄膜
の特徴が損なわれないことを示している。一方(C)や
(D)の薄膜トランジスタでは、A1とTaとの腹合絶
縁膜に比べTaとSiとの複合絶縁膜の比誘電率の方が
小さいため、あるいはTaとSiとの複合絶縁膜に比べ
SiO2の比誘電率の方が小さいために、大きなドレイ
ン電流を得るためには、大きなゲート電圧を必要とする
ことがわかる。
FIG. 3 of Table 1 shows the drain current when the gate voltage is changed. As is clear from the figure, the thin film transistor (A) of the present invention has a second gate insulating film made of Ta and Si.
Since the dielectric constant of the composite insulating film with (B) is relatively large,
This shows that almost the same electrical characteristics as those of the thin film transistor were obtained, and the characteristics of the composite insulator sputtered thin film of AI and Ta, which have a large dielectric constant, are not impaired. On the other hand, in the thin film transistors (C) and (D), the dielectric constant of the composite insulating film of Ta and Si is smaller than that of the dielectric film of A1 and Ta, or the composite insulating film of Ta and Si It can be seen that since the dielectric constant of SiO2 is smaller than that of SiO2, a large gate voltage is required in order to obtain a large drain current.

第4図は、第1図でソース電極6とドレイン電極7を共
通電極として、これとゲート電極2との間に電圧を印加
したときのリーク電流を示している。本発明の薄膜トラ
ンジスタ(A)では(B)または(C)の薄膜トランジ
スタに比べて十分にリーク電流が小さいことがわかる。
FIG. 4 shows the leakage current when a voltage is applied between the source electrode 6 and the drain electrode 7 in FIG. 1 as common electrodes and the gate electrode 2. FIG. It can be seen that the leakage current in the thin film transistor (A) of the present invention is sufficiently smaller than that in the thin film transistor (B) or (C).

これは多層構造のため、スパッタ時に発生したピンホー
ル等の欠陥が第1のゲート絶縁膜と第2のゲート絶縁膜
との界面で断ち切られる確率が高くなるためと考えられ
る。リーク電流が少ないと絶縁膜中の電荷トラップに注
入される電子の個数も少なくなるため、薄膜トランジス
タ特性の経時変化を小さくすることができる。また、(
D)の薄膜トランジスタよりらリーク電流が少ないこと
から、SiO2の単独膜よりもTaとSiとの複合絶縁
膜とした方がよりちみつな膜が形成されることがわかる
This is considered to be because the multilayer structure increases the probability that defects such as pinholes generated during sputtering will be cut off at the interface between the first gate insulating film and the second gate insulating film. When the leakage current is small, the number of electrons injected into charge traps in the insulating film is also reduced, so that changes over time in thin film transistor characteristics can be reduced. Also,(
Since the leakage current is smaller than that of the thin film transistor D), it can be seen that a composite insulating film of Ta and Si forms a more honeyed film than a single film of SiO2.

第5図は(A)、(B)、(C)、(D)の薄膜トラン
ジスタについてドレイン電流の経時変化を示したもので
ある。本発明の薄膜トランジスタ(A)では、経時変化
が非常に少ない。これは、半導体膜とゲート絶縁膜との
界面近傍において、非常に密着性がよいため欠陥の発生
が少なく経時変化の主たる原因である電荷トラップの数
が非常に少ないことを意味している。また、前述したよ
うにリーク電流が少ないため電荷トラップに注入される
電子の数自体が少な(なるためと考えられる。
FIG. 5 shows changes in drain current over time for the thin film transistors (A), (B), (C), and (D). The thin film transistor (A) of the present invention shows very little change over time. This means that near the interface between the semiconductor film and the gate insulating film, the adhesion is very good, so there are few defects and the number of charge traps, which is the main cause of aging, is very small. Further, as described above, since the leakage current is small, the number of electrons injected into the charge trap is small.

第1図のゲート絶縁膜としては抵抗加熱法や電子ビーム
法により作製された絶縁膜では上記のような特性は得ら
れずスパッタ法により作製することで電荷トラップが少
なくなることがわかる。
It can be seen that the gate insulating film shown in FIG. 1 cannot have the above-mentioned characteristics with an insulating film produced by a resistance heating method or an electron beam method, and that charge traps are reduced by producing it by a sputtering method.

第2のゲート絶縁膜がAIとSiとの他にチッ素を含有
すれば、チッ素は可動不純物イオンを捕獲する作用があ
り、不純物イオンの移動による特性の不安定性を改善す
ることができる。
If the second gate insulating film contains nitrogen in addition to AI and Si, nitrogen has the effect of capturing movable impurity ions, and instability of characteristics due to movement of impurity ions can be improved.

第2のゲート絶縁膜の厚さは、比誘電率が小さいため、
大きな相互コンダクタンスを得るためには、50nm以
下であることが望ましい。また、10nm以下では安定
した膜特性が得られなかった。
The thickness of the second gate insulating film has a small dielectric constant, so
In order to obtain a large mutual conductance, the thickness is preferably 50 nm or less. Further, stable film characteristics could not be obtained at a thickness of 10 nm or less.

本実施例では、半導体膜としてCdSeを用いた場合に
ついて述べたが、CdS、CdTeあるいはそれらの固
溶体の場合にも本発明の効果が大であることがわかった
In this example, the case where CdSe was used as the semiconductor film was described, but it was found that the effect of the present invention is also great when using CdS, CdTe, or a solid solution thereof.

発明の効果 本発明の薄膜トランジスタでは、ゲート絶縁膜と半導体
膜との界面において電荷トラップが少なく、また、リー
ク電流が少ないことから電荷トラップへの電子の注入そ
のものが起こりにくいため、薄膜トランジスタの電気特
性や安定性を大きく改善することができる。また、ゲー
ト絶縁膜の比誘電率が全体として太き(なるため、相互
コンダクタンスが太き(各種表示装置の駆動等に広く利
用できるものである。
Effects of the Invention In the thin film transistor of the present invention, there are few charge traps at the interface between the gate insulating film and the semiconductor film, and since the leakage current is small, injection of electrons into the charge traps itself is difficult to occur, which improves the electrical characteristics of the thin film transistor. Stability can be greatly improved. In addition, the relative dielectric constant of the gate insulating film is large as a whole, so the mutual conductance is large (it can be widely used for driving various display devices, etc.).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の薄膜トランジスタの一実施例を示す断
面図、第2図はTaとSiとの複合絶縁膜の組成と比誘
電率との関係を示すグラフ、第3図は薄膜トランジスタ
の電気特性を示すグラフ、第4図はゲート絶縁膜のリー
ク電流を示すグラフ、第5図は薄膜トランジスタ特性の
経時変化を示すグラフである。 l・・・絶縁性基板、2・・・ゲート電極、3・・・第
1のゲート絶縁膜(AtとTaとの複合絶縁物スパッタ
薄膜)、4・・・第2のゲート絶縁膜(TaとSiとの
複合絶縁物スパッタ薄膜)、5・・・半導体膜、6・・
・ソース電極、7・・・ドレイン電極。 代理人の氏名 弁理士 中尾敏男 ほか1名 ゛第1図 第2図 TazO5の分子尾牟(γ、) 第3図 −Io        o        to   
     z。 ケートを圧CV) 第4図
Figure 1 is a cross-sectional view showing one embodiment of the thin film transistor of the present invention, Figure 2 is a graph showing the relationship between the composition and dielectric constant of a composite insulating film of Ta and Si, and Figure 3 is the electrical characteristics of the thin film transistor. FIG. 4 is a graph showing leakage current of the gate insulating film, and FIG. 5 is a graph showing changes in thin film transistor characteristics over time. l... Insulating substrate, 2... Gate electrode, 3... First gate insulating film (sputtered composite insulating film of At and Ta), 4... Second gate insulating film (Ta and Si composite insulator sputtered thin film), 5... semiconductor film, 6...
- Source electrode, 7... drain electrode. Name of agent: Patent attorney Toshio Nakao and one other person Fig. 1 Fig. 2 Molecular tail of TazO5 (γ,) Fig. 3 - Io o to
z. Figure 4

Claims (4)

【特許請求の範囲】[Claims] (1)絶縁性基板上に設けた少なくともドレイン電極、
ゲート電極、ソース電極、半導体膜及びゲート絶縁膜で
構成され、前記ゲート絶縁膜が、少なくともアルミニウ
ムとタンタルとを主成分とする複合絶縁物スパッタ薄膜
からなる第1のゲート絶縁膜と、前記第1のゲート絶縁
膜と前記半導体膜との間にあって少なくともタンタルと
シリコンとを主成分とする複合絶縁物スパッタ薄膜から
なる第2のゲート絶縁膜との多層膜からなることを特徴
とする薄膜トランジスタ。
(1) at least a drain electrode provided on an insulating substrate;
a first gate insulating film composed of a gate electrode, a source electrode, a semiconductor film, and a gate insulating film, the gate insulating film being a composite insulating sputtered thin film containing at least aluminum and tantalum as main components; A thin film transistor comprising a multilayer film including a gate insulating film and a second gate insulating film between the semiconductor film and a second gate insulating film made of a composite insulating sputtered thin film containing at least tantalum and silicon as main components.
(2)第2のゲート絶縁膜が少なくともタンタルとシリ
コンとチッ素とを主成分とする複合絶縁物スパッタ薄膜
からなることを特徴とする特許請求の範囲第1項記載の
薄膜トランジスタ。
(2) The thin film transistor according to claim 1, wherein the second gate insulating film is made of a composite insulating sputtered thin film containing at least tantalum, silicon, and nitrogen as main components.
(3)第2のゲート絶縁膜の厚さが10nm以上50n
m以下であることを特徴とする特許請求の範囲第1項記
載の薄膜トランジスタ。
(3) The thickness of the second gate insulating film is 10 nm or more and 50 nm
2. The thin film transistor according to claim 1, wherein the thickness of the thin film transistor is less than or equal to m.
(4)半導体膜が、CdS、CdSe、CdTe又はそ
れらの固溶体であることを特徴とする特許請求の範囲第
1項記載の薄膜トランジスタ。
(4) The thin film transistor according to claim 1, wherein the semiconductor film is CdS, CdSe, CdTe, or a solid solution thereof.
JP5055987A 1987-03-05 1987-03-05 Thin film transistor Expired - Fee Related JPH084144B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5055987A JPH084144B2 (en) 1987-03-05 1987-03-05 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5055987A JPH084144B2 (en) 1987-03-05 1987-03-05 Thin film transistor

Publications (2)

Publication Number Publication Date
JPS63216378A true JPS63216378A (en) 1988-09-08
JPH084144B2 JPH084144B2 (en) 1996-01-17

Family

ID=12862363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5055987A Expired - Fee Related JPH084144B2 (en) 1987-03-05 1987-03-05 Thin film transistor

Country Status (1)

Country Link
JP (1) JPH084144B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04323871A (en) * 1991-04-23 1992-11-13 Kobe Steel Ltd Material for semiconductor device
US5270229A (en) * 1989-03-07 1993-12-14 Matsushita Electric Industrial Co., Ltd. Thin film semiconductor device and process for producing thereof
US5976641A (en) * 1991-03-07 1999-11-02 Kabushiki Kaisha Kobe Seiko Sho A1 alloy films and melting A1 alloy sputtering targets for depositing A1 alloy films

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270229A (en) * 1989-03-07 1993-12-14 Matsushita Electric Industrial Co., Ltd. Thin film semiconductor device and process for producing thereof
US5976641A (en) * 1991-03-07 1999-11-02 Kabushiki Kaisha Kobe Seiko Sho A1 alloy films and melting A1 alloy sputtering targets for depositing A1 alloy films
US6206985B1 (en) 1991-03-07 2001-03-27 Kabushiki Kaisha Kobe Seiko Sho A1 alloy films and melting A1 alloy sputtering targets for depositing A1 alloy films
JPH04323871A (en) * 1991-04-23 1992-11-13 Kobe Steel Ltd Material for semiconductor device

Also Published As

Publication number Publication date
JPH084144B2 (en) 1996-01-17

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