JPH08335580A - Manufacture of dielectric thin film and manufacture of ferroelectric memory device employing the dielectric thin film - Google Patents

Abstract

PURPOSE: To provide the manufacturing method of a dielectric thin film which shows on excellent performance when it is employed in an MFIS-FET type ferroelectric memory device. CONSTITUTION: The manufacturing method of a dielectric thin film consists of a process in which a silicon oxide thin film is formed on a silicon substrate, a process in which an SrTiO3 thin film is formed on the silicon oxide thin film by a sputtering method with the substrate kept heated and a process in which the heat treatment is applied after the SrTiO3 thin film is formed at a temperature not lower than the substrate heating temperature when the SrTiO3 thin film is formed and not higher than 800 deg.C.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dielectric thin film used for a ferroelectric memory element of a non-volatile memory, and a method of manufacturing a ferroelectric thin film element using the same.

[0002]

2. Description of the Related Art Conventionally, as a dielectric thin film formed on a silicon single crystal substrate, SiO ₂ used for a gate insulating film of a MOS-FET because it is an insulating film with an excellent interface protective film with silicon. A thermal oxide film was typical.

On the other hand, it is a nonvolatile semiconductor memory element using a ferroelectric thin film as a gate insulating film of a MOS-FET.
MFS (Metal Ferroelectric Semiconductor) -FE
A ferroelectric memory element having a T (Field Effect Transistor) structure has been proposed. That is, in the ferroelectric memory element having the MFS-FET structure, as shown in FIG. 8, the ferroelectric film 106 and the gate electrode 107 are formed on the channel region sandwiched between the impurity diffusion layers 104 and 105 on the surface of the silicon substrate 101.
And are sequentially formed. In the ferroelectric memory element having such a structure, depending on the direction and size of the spontaneous polarization of the ferroelectric thin film 106, the electric charges induced in the channel region on the surface of the silicon substrate 101 compensate for the spontaneous polarization. The contents of the memory are read by utilizing the fact that the conductivity of the channel region is modulated. This element has been attracting attention as an excellent memory because it can perform nondestructive reading without destroying the memory contents during reading.

However, an oxide ferroelectric thin film having a perovskite structure such as PZT (lead zirconate titanate), SrBi ₂ Ta ₂ O ₉ and Bi ₄ Ti ₃ O ₁₂ is directly formed on a silicon substrate to form a strong ferroelectric film. It is difficult to realize a dielectric memory device due to the following problems.

It is because the process of forming the ferroelectric thin film includes a high temperature heat treatment process of 500 to 800 ° C.
The constituent elements of the ferroelectric substance and silicon diffuse into each other, causing different phases due to reaction at the interface with the silicon substrate, deterioration of the ferroelectricity, damage at the interface, and the like. Further, in PZT, cracks may even occur due to the difference in thermal expansion coefficient.

In order to solve such a problem, an MFIS (Metal Ferroelectric Insulator Semico) in which a dielectric buffer film is interposed between a silicon substrate and a ferroelectric thin film.
(nductor) -FET structure has been studied, and it is necessary to establish a dielectric thin film applicable to this structure and a method of manufacturing the dielectric thin film on a silicon substrate in order to realize this structure.

At present, various dielectric thin films having such an MFIS-FET structure and various methods for manufacturing the dielectric thin films are being studied, but the dielectric thin films are formed on a silicon substrate while maintaining a clean interface. However, a film forming method in an ultra-high vacuum or a high vacuum is often used. For example, SrT
iO ₃ / SrO, SrTiO ₃ / SrF ₂ , SrTiO ₃ /
It has been reported that a two-layer dielectric buffer film such as CaF ₂ is formed by using a high vacuum deposition method (The 42nd Joint Lecture on Applied Physics 30p-D-4: K.Itani, et al.).

[0008]

However, in the above MFIS-FET structure, SrTiO ₃ / SrF ₂ and SrTiO ₃ using a fluoride thin film on the silicon substrate side are used.
The interface with the silicon substrate can be formed relatively cleanly with a dielectric buffer layer such as / CaF ₂ , but a process of forming an oxide ferroelectric thin film on the dielectric buffer layer at a high temperature of 500 to 800 ° C. In the above, there arises a problem that the interface between the silicon substrate and the dielectric buffer layer is damaged. In addition, SrTiO 3 using an oxide on the silicon substrate side
A dielectric buffer layer such as ₃ / SrO has a problem that a reaction occurs at the interface between silicon and the dielectric buffer layer when the ferroelectric thin film is formed on the dielectric buffer layer by a high temperature process.

These problems are caused by the conventional MFIS-FE.
In the T structure, there have been various factors that deteriorate the characteristics of the memory element.

Therefore, the inventors have proposed to apply the SrTiO ₃ / SiO ₂ dielectric buffer layer as the dielectric buffer layer of the MFIS-FET structure. That is,
The above conventional SrTiO ₃ / SrO, SrTiO ₃ / SrF
_2. The two-layer structure dielectric buffer layer such as SrTiO ₃ / CaF ₂ had a problem at the interface with the silicon substrate, and thus the thermal silicon oxide (SiO ₂ ) film having the best interface protection property with the silicon substrate. S on the silicon substrate side
We focused on the rTiO ₃ / SiO ₂ dielectric buffer layer.

The SrTiO ₃ / SiO ₂ dielectric buffer layer is an insulating film serving as an interface protective film capable of withstanding the high temperature ferroelectric thin film forming process. The ferroelectric thin film has a characteristic of being a base dielectric thin film which can be crystallized. It is considered that it can be expected to be an excellent dielectric buffer layer.

However, in a SrTiO ₃ / SiO ₂ dielectric buffer layer obtained by forming a SiO ₂ thermal oxide film on a silicon substrate and subsequently forming a SrTiO ₃ thin film by a sputtering method while heating the substrate, Sr
There is a positive fixed charge in the TiO ₃ / SiO ₂ thin film, and the flat band voltage V _fb (in the band theory, the valence levels of the silicon substrate and the gate electrode are made equal (the silicon substrate and the gate electrode are made equal to each other. It was found that the voltage applied between the silicon substrate and the gate electrode, which is necessary for making the valence level of (i.e., a flat band), shift in the negative bias direction (negative shift).

This negative shift of V _fb occurs when the threshold voltage V _th (the valence level of the silicon substrate and the valence level of the gate electrode are reversed by the voltage application between the silicon substrate and the gate electrode). The inversion layer causes a shift in the voltage between the silicon substrate and the gate electrode at the time of starting formation, and (a) increases the leakage current between the source and drain when an n-type channel is used (b) When the p-type channel is used, it causes a problem that the threshold value of the operating voltage increases, which is a serious problem for practical use of the ferroelectric memory element having the MFIS-FET structure.

Such a problem is caused by the S method by the sputtering method.
Since the rTiO ₃ thin film is formed, the SiO ₂ thin film is damaged by the plasma of the sputtering gas, and the S
Physical defects such as defects in the rTiO ₃ thin film cause SrT
It is considered that this is due to the presence of positive fixed charges in the iO ₃ / SiO ₂ thin film.

The present invention has been made to solve the above problems, and provides a method for manufacturing a dielectric thin film suitable for use in an MFIS-FET type ferroelectric memory element. To aim.

[0016]

In order to solve the above problems, according to the present invention, a step of forming a silicon oxide thin film on a silicon substrate and SrTiO 3 on the silicon oxide thin film.
A step of forming by sputtering ₃ With thin and heating the substrate after the SrTiO ₃ thin film formation process,
Above the substrate heating temperature during SrTiO ₃ formation and 800 ° C
The method for producing a dielectric thin film comprises the following steps of heat treatment.

Further, in the present invention, in the above-mentioned method for manufacturing a dielectric thin film, the heat treatment step is performed in an oxygen atmosphere.

Further, in the present invention, in the above-mentioned method for producing a dielectric thin film, the heat treatment step is performed in an inert gas atmosphere.

Further, in the present invention, in the above-described method for forming a dielectric thin film, the heat treatment step is performed in a mixed gas atmosphere of oxygen and an inert gas.

Further, according to the present invention, 2 is formed on the surface of the silicon substrate.
Forming one impurity diffusion layer, forming a silicon oxide thin film on the channel region sandwiched between the two impurity diffusion layers on the surface of the silicon substrate, and heating the SrTiO ₃ thin film on the silicon oxide thin film. In the state by a sputtering method, after the SrTiO ₃ thin film forming step, a step of performing a heat treatment at a temperature of the substrate heating temperature at the time of forming the SrTiO ₃ or higher and 800 ° C. or lower, and Sr
A method of manufacturing a ferroelectric memory element comprising the step of forming a ferroelectric thin film on a TiO ₃ thin film.

[0021]

According to the present invention, SrTiO 2 formed by the sputtering method
₃ after formation of a thin film, by heat treatment step, SiO ₂
The damage to the thin film is eliminated, the SrTiO ₃ thin film becomes a crystallized film, and the constituent atoms in the SrTiO ₃ thin film are made to exist from the defect position to the lattice position.
It is considered that the positive fixed charges in the O ₃ / SiO ₂ thin film can be eliminated.

Further, the processing temperature of the heat treatment step of the present invention is a temperature not lower than the substrate heating temperature at the time of forming the SrTiO ₃ thin film by the sputtering method, and a temperature which is possible as a manufacturing process of an element using silicon 800 The effect can be obtained at a processing temperature of ℃ or below.

The heat treatment step of the present invention is preferably performed in an oxygen atmosphere, an inert gas atmosphere, or a mixed gas atmosphere of an inert gas and oxygen.
Here, the inert gas does not mean only a rare gas such as He, Ne, and Ar, but N ₂ in addition to the rare gas.
It means a gas with poor reactivity such as.

By the operation of the present invention as described above, the shifts of V _fb and V _th can be suppressed. Therefore, according to the method for producing a dielectric thin film of the present invention, the MFIS
The characteristics of the dielectric buffer layer between the silicon substrate and the ferroelectric thin film of the FET structure ferroelectric memory element can be greatly improved. Therefore, according to the method for manufacturing a ferroelectric memory element of the present invention, by improving the characteristics of the dielectric buffer layer,
It is possible to realize a MFIS-FET structure ferroelectric memory element having excellent element characteristics.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of an essential part of a sample manufactured by the method for manufacturing a dielectric thin film of the present invention, in which a silicon oxide film 2 and a SrTiO ₃ thin film 3 are sequentially formed on a silicon substrate 1. .

First, the preparation of the sample in this embodiment will be described. The silicon substrate 1 is p-type and has a resistivity of 8
A Si (100) substrate 1 having a thickness of -12 Ωcm was used, and the surface thereof was subjected to dry thermal oxidation to form a silicon oxide film (SiO ₂ thin film) 2 having a thickness of 30 nm. Then, the SrTiO ₃ thin film 3 having a film thickness of 30 nm was formed on the SiO ₂ thin film 2 by the RF-magnetron sputtering method. In forming the SrTiO ₃ thin film at this time, a sintered target of SrTiO ₃ (purity: 4N (99.99%)) was used as a sputtering target, and the film forming chamber was once evacuated to 2 × 10 ⁻⁴ Pa. After that, the substrate heating temperature is 400 ° C., the RF power is 50 W, and the sputter gas is Ar:
O ₂ = mixed gas of 8: 2 (gas pressure in film forming chamber: 2 Pa)
Went as.

In this way, the sample obtained by sequentially forming the SiO ₂ thin film and the SrTiO ₃ thin film on the Si substrate was
It was taken out from the sputtering apparatus used for forming the rTiO ₃ thin film, and heat treatment was performed in an oxygen atmosphere at atmospheric pressure for 30 minutes by a heat treatment apparatus using an infrared lamp. The processing temperature of the heat treatment at this time is 500 ° C., 600 ° C., 700, which is higher than the substrate heating temperature at the time of forming the SrTiO ₃ thin film by the sputtering method and is a temperature that is possible in the element manufacturing process using silicon.
℃ and 800 ℃. Heat treatment was performed at these four types of temperatures to produce four types of samples.

FIG. 2 shows the results of obtaining the shift (negative shift) of V _{fb in} the negative bias direction from the measurement of the CV characteristics for these four types of samples having different heat treatment temperatures. The measurement conditions at this time were Hg as the upper electrode.
(Mercury) -Probe (area ≈ 0.5 mmφ) was used, and the amplitude was 15 mVrms between the upper electrode and the back surface of the Si substrate.
DC bias was applied to a sine wave of 0 kHz up to −10 to +10 V (bias sweep rate ΔV = 500 mV / se.
c. ), Was measured.

The vertical axis of FIG. 2 shows the negative shift (V) of V _fb . According to FIG. 2, the negative shift of V _fb before the heat treatment step of this example (as-depo) was −5.4 V, but the heat treatment temperature 50
-1.4V for a sample at 0 ° C, -1.8V for a sample at a heat treatment temperature of 600 ° C, -1.7V for a sample at a heat treatment temperature of 700 ° C, and -1.5V for a sample at a heat treatment temperature of 500 ° C. It can be seen that the negative shift of V _fb is greatly reduced and can be improved.

Next, the observation results by X-ray diffraction of four types of samples prepared in the above-mentioned examples and having different heat treatment temperatures will be described. When X-ray diffraction of the as-depo sample before the heat treatment step of this example was observed, it was an amorphous thin film showing no diffraction peak, but in the sample subjected to the heat treatment step, the SrTiO ₃ thin film (11
The diffraction peaks of (0) and (200) were shown, and it was found that the SrTiO ₃ thin film was crystallized. At this time, Sr in four types of samples with different heat treatment temperatures of this example
The observation results of the X-ray diffraction peak intensities of (110) and (200) of the TiO ₃ thin film are shown in FIG.

The vertical axis of FIG. 3 shows the diffraction peak intensity (CPS). Looking at this FIG. 3, there is no diffraction peak before the heat treatment step (without annealing), but due to the heat treatment step. Crystallized, the (110) diffraction peak intensity is highest in the samples at the heat treatment temperatures of 700 ° C. and 800 ° C., and the (200) diffraction peak intensity is the highest in the sample at the heat treatment temperature of 800 ° C. . From this, according to the heat treatment step of the present embodiment,
Heat treatment temperatures of 500 ° C, 600 ° C, 700 ° C, and 80
It can be seen that the SrTiO ₃ thin film can be crystallized in any of the samples at 0 ° C., and particularly the sample at the heat treatment temperature of 800 ° C. can promote the crystallization most.

Further, when the dielectric constant of the sample of this example was measured, amorphous SrTiO 3 before the heat treatment step after the SrTiO ₃ thin film forming step by the sputtering method was performed.
_{3 The} thin film had a thickness of 20 to 30, while the sample subjected to the heat treatment step had a rise to 70 to 75. From this, in the MFIS-FET structure, the larger the dielectric constant of the dielectric buffer layer is, the easier the voltage is applied to the ferroelectric thin film, and therefore the better characteristics are shown for use in this structure. all right.

Further, the Sr of the sample produced in this embodiment is
Since the surface of the TiO ₃ thin film was dense and flat,
It was confirmed that it was a good one that could be finely processed at the time of actual device fabrication.

Next, as a second embodiment, of the conditions of the heat treatment process of the first embodiment, only the gas atmosphere is O 2
_An N ₂ atmosphere that is an inert gas instead of the ₂ atmosphere will be described.

In the second embodiment, the heat treatment process after forming the SrTiO ₃ thin film was performed in an N ₂ atmosphere, and the other sample preparation conditions were the same as those in the first embodiment to prepare a sample. Then, with respect to the sample manufactured here, the negative shift of V _fb by the measurement of the CV characteristics and the observation of X-ray diffraction were performed in the same manner as in the first example, and the same as in the first example. Results were obtained. Of these, SrT
4 and 5 show the results of the evaluation of the negative shift of V _fb by the measurement of the CV characteristics and the observation of the X-ray diffraction for the sample in which the treatment temperature in the heat treatment step after forming the iO ₃ thin film was 800 ° C., respectively. Shown in. 4 and 5
For comparison, the data of the sample having the heat treatment temperature of the first example of 800 ° C. is also shown in FIG.

From FIG. 4, the negative shift of V _fb is -0.6 in the sample subjected to the heat treatment in the N ₂ atmosphere.
V, which was 0.9 V, and the negative shift of V _fb was further reduced by 0.9 V as compared with the heat treatment step in the O ₂ atmosphere of the first embodiment, and the negative shift of V _fb was remarkably improved. It became a result. Also, from FIG.
Although the diffraction peak intensity is smaller than that of the second embodiment, it can be seen that the SrTiO ₃ thin film can be crystallized also in the second embodiment.

When the dielectric constant of the sample of the second embodiment was measured, an increase in the dielectric constant due to the heat treatment step was observed as in the first embodiment. The surface of the SrTiO ₃ thin film of the sample manufactured in the second embodiment was also dense and flat, as in the case of the first embodiment.

Next, as a third embodiment, of the conditions of the heat treatment step of the first embodiment, only the gas atmosphere is
A description will be given of the case of using a mixed gas atmosphere of an inert gas N ₂ and O ₂ instead of the O ₂ atmosphere. In the third example, the heat treatment process after forming the SrTiO ₃ thin film was performed in a mixed gas atmosphere of O ₂ and N _2, and other sample production conditions were the same as those in the first example to produce a sample. However, here, the mixing ratio of O ₂ and N ₂ in the mixed gas is O ₂ :
Three types of N ₂ = 8: 2, 5: 5, 2: 8 were examined. Then, at any mixing ratio, as in the first and second embodiments, when the negative shift of V _fb was evaluated by the measurement of the CV characteristics and the X-ray diffraction was observed, V _{fb was obtained.} Negative shift of SrTiO ₃
Crystallization of the thin film was confirmed as in the first and second examples.

When the dielectric constant of the sample of the third embodiment was measured, an increase in the dielectric constant due to the heat treatment step was observed, as in the first and second embodiments. The surface of the SrTiO ₃ thin film of the sample manufactured in the third embodiment was also dense and flat, as in the first and second embodiments.

In the second and third embodiments,
N ₂ was used as the inert gas, but in addition to this, Ar,
He or the like can also be used. However, when it is used for actual device production, considering the production cost, N ₂ , A
r is preferred.

In the first to third embodiments, the heat treatment step after the SrTiO ₃ thin film forming step by the sputtering method was performed for 30 minutes, but the effect of the present invention can be obtained in 1 minute or more. Can be confirmed, and the processing time of these examples is not limited.

In the above first to third embodiments, S
Although the p-type is used as the i-substrate, it may be n-type. Although the thickness of the silicon oxide film is 30 nm and the thickness of the SrTiO ₃ thin film is 30 nm, the thickness of the silicon oxide film is 5 to 50 nm, and the thickness of the SrTi ₃ thin film is not limited to these.
The thickness of the O ₃ thin film is preferably 10 to 150 nm.

Then, a ferroelectric thin film is formed on the SrTiO ₃ thin film produced under the same conditions as in the above-mentioned embodiment to form MFI.
A fourth embodiment in which a ferroelectric memory element having an S-FET structure is manufactured will be described with reference to FIG.

FIG. 6 is a cross-sectional view of the essential part showing the basic structure of the ferroelectric memory element manufactured in the fourth embodiment.
Two impurity diffusion layers 1 are formed on the surface of the (100) substrate 11.
A SiO ₂ thin film 1 is formed on the channel region sandwiched between 4 and 15.
2 is arranged, and SrTiO _{3 is} deposited on the SiO ₂ thin film 12.
The film 13 is arranged, and the ferroelectric thin film 16 and the gate electrode 17 are sequentially arranged on the SrTiO ₃ thin film 13.

In the fabrication of the element in this embodiment, S
After the n ⁺ impurity diffusion layers 14 and 15 to be the source region and the drain region are formed on the surface of the i substrate 11 by the ion implantation method, Si is formed in the same manner as in the first to third embodiments.
A SiO ₂ thin film 12 is formed on the substrate 11 by dry thermal oxidation.
(Film thickness of 30 nm) was formed into Sr by RF sputtering method.
A TiO ₃ thin film 13 (thickness 30 nm) was sequentially formed. Then, the same heat treatment process as in the first to third embodiments was performed.

Then, in this embodiment, the ferroelectric thin film 1 is used.
6, S which is one of the Bi-based layered structure ferroelectric materials
A thin film of rBi ₂ Ta ₂ O ₉ was formed by using the sol-gel method. The conditions for heat treatment during film formation by the sol-gel method are preferably a heat treatment temperature of 700 to 800 ° C. and a treatment time of 10 minutes to 60 minutes. In this example, the heat treatment temperature is 800 ° C. for 30 minutes. Then, a SrBi ₂ Ta ₂ O ₉ thin film having a film thickness of 200 nm was formed.
Then, a Pt electrode was formed as the gate electrode 17 by the sputtering method. After that, a mask is made with a resist and an SiO ₂ thin film 12, S
rTiO ₃ thin film 13, ferroelectric thin film (SrBi ₂ Ta ₂ O ₉
The thin film) 16 and the gate electrode (Pt electrode) 17 except for the channel portion are removed, and MFSFE as shown in FIG.
The fabrication of the T structure ferroelectric memory element was completed.

In the ferroelectric memory element of the present example produced in this way, SrTi formed by the sputtering method was used.
The heat treatment process after the O ₃ thin film formation was performed in a N ₂ atmosphere at a heat treatment temperature of 800 ° C. for a treatment time of 30 minutes.
The high frequency C-V characteristic was measured. High frequency C at this time
The measurement condition of the −V characteristic is that the gate electrode area is 2 × 10 ⁻³ c
m ^2, and the frequency 1MHz, the sweep of the gate voltage is -10V
To + 10V and -10V to + 10V.

FIG. 7 shows the measurement results of the high frequency C-V characteristics, where the horizontal axis is the gate voltage (V) applied between the gate electrode and the silicon substrate, and the vertical axis is the gate electrode-. It is the capacitance (pF) between silicon substrates. According to FIG. 7, the ferroelectric memory element of this example has a good hysteresis curve with a memory window of about 3V. Further, it has been confirmed that when the present invention is applied to a ferroelectric memory element, such as a reduction in leakage current and a reduction in operating voltage by suppressing the negative shift of V _fb , good characteristics as a memory element can be obtained.

The ferroelectric thin film material and the electrode material are not limited to those in the above embodiments. For example, as the ferroelectric material, PZT (lead zirconate titanate) or Bi type layered structure ferroelectric material is used. Ferroelectric materials such as Here, the Bi-based layered structure ferroelectric substance means the above-mentioned SrB.
In addition to i ₂ Ta ₂ O ₉ , typical ones include Bi ₄ Ti ₃ 0 ₁₂ but other than this, SrBi ₂ Nb ₂ O ₉ and BaBi ₂ N are also available.
b ₂ O ₉ , BaBi ₂ Ta ₂ O ₉ , Pb ₂ Bi ₂ Nb ₂ O ₉ , P
bBi ₂ Ta ₂ O ₉ , SrBi ₄ Ti ₄ O ₁₅ , BaBi ₄ Ti
₄ O ₁₅ , PbBi ₄ Ti ₄ O ₁₅ , Na _0.5 Bi _4.5 Ti
₄ O ₁₅ , K _0.5 Bi _4.5 Ti ₄ O ₁₅ , Sr ₂ Bi ₄ Ti
₅ O ₁₈ , Ba ₂ Bi ₄ Ti ₅ O ₁₈ , Pb ₂ Bi ₄ Ti ₅ O _{18 and the} like. These Bi-based layered structure ferroelectric materials have a dielectric constant of about 200 or less, which is smaller than that of PZT. When a ferroelectric thin film having such a small dielectric constant is used in the MFIS-FET structure, a voltage is easily applied to the ferroelectric thin film when a voltage is applied to the gate electrode, so that lower voltage driving becomes possible. . Further, as the method for forming the ferroelectric thin film, besides the sol-gel method, a sputtering method, a MOCVD method, or the like can be used, and the method is not limited to the above embodiment.

The first embodiment is also applied to the fourth embodiment.
As in the third to third embodiments, the type of Si substrate, the thickness of the silicon oxide film, the thickness of the SrTiO ₃ thin film, etc. are not limited to those in this embodiment.

[0051]

As described above, according to the method for producing a dielectric thin film of the present invention, damage to the SiO ₂ thin film can be eliminated and the SrTiO ₃ thin film can be crystallized. Therefore, SrTiO ₃ / SiO ₂ The fixed charges existing in the thin film can be eliminated, and the shifts of the flat band voltage V _fb and the threshold voltage V _th can be well suppressed. Furthermore, since the SrTiO ₃ thin film can be crystallized and the dielectric constant can be increased, it is possible to easily apply a voltage to the dielectric thin film when applied to a ferroelectric memory element.

Further, according to the method of manufacturing a ferroelectric memory element of the present invention, the element characteristics are excellent, the low voltage driving is possible, and the leakage current can be reduced. Can be realized ,.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a sample manufactured by a method for manufacturing a dielectric thin film according to an embodiment of the present invention.

FIG. 2 is a diagram showing the results of _obtaining the negative shift of V _fb from the measurement of the CV characteristics of the sample manufactured in the first example.

FIG. 3 is a sample SrTiO 3 produced in the first embodiment.
It is a figure which shows the observation result of the X-ray-diffraction peak intensity of ₃ thin films.

FIG. 4 is a diagram showing the results of _obtaining the negative shift of V _fb from the measurement of the CV characteristics of the sample manufactured in the second example.

FIG. 5 is a sample SrTiO 3 produced in the second embodiment.
It is a figure which shows the observation result of the X-ray-diffraction peak intensity of ₃ thin films.

FIG. 6 is a cross-sectional view of an essential part of a ferroelectric memory element having an MSIF-FET structure manufactured in a fourth example.

FIG. 7 is a diagram showing measurement results of high frequency CV characteristics of a ferroelectric memory element having an MSIF-FET structure manufactured in a fourth example.

FIG. 8 is a cross-sectional view of a main part of a conventional ferroelectric memory element having an MSF-FET structure.

[Explanation of symbols]

1, 11 Silicon substrate 2, 12 SiO ₂ thin film _3, 13 SrTiO ₃ thin film 14, 15 Impurity diffusion layer 16 Ferroelectric thin film 17 Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/43 H01L 29/62 G 21/8247 29/78 371 29/788 29/792

Claims (5)

[Claims] 1. A step of forming a silicon oxide thin film on a silicon substrate, a step of forming a SrTiO ₃ thin film on the silicon oxide thin film by a sputtering method with the substrate being heated, and after the SrTiO ₃ thin film forming step, A method of manufacturing a dielectric thin film, which comprises a step of performing a heat treatment at a temperature not lower than a substrate heating temperature and not higher than 800 ° C. at the time of forming SrTiO ₃ . 2. The method for producing a dielectric thin film according to claim 1, wherein the heat treatment step is performed in an oxygen atmosphere. 3. The method for producing a dielectric thin film according to claim 1, wherein the heat treatment step is performed in an inert gas atmosphere. 4. The method for producing a dielectric thin film according to claim 1, wherein the heat treatment step is performed in a mixed gas atmosphere of oxygen and an inert gas. 5. A step of forming two impurity diffusion layers on the surface of a silicon substrate, a step of forming a silicon oxide thin film on a channel region sandwiched between the two impurity diffusion layers of the surface of the silicon substrate, and the silicon oxide. A step of forming a SrTiO ₃ thin film on the thin film by a sputtering method in a state where the substrate is heated, and a step of performing a heat treatment after the SrTiO ₃ thin film forming step at a temperature of the substrate heating temperature at the time of forming the SrTiO ₃ or more and 800 ° C. or less, And a step of forming a ferroelectric thin film on the SrTiO ₃ thin film.