JPS63115350A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPS63115350A
JPS63115350A JP26225986A JP26225986A JPS63115350A JP S63115350 A JPS63115350 A JP S63115350A JP 26225986 A JP26225986 A JP 26225986A JP 26225986 A JP26225986 A JP 26225986A JP S63115350 A JPS63115350 A JP S63115350A
Authority
JP
Japan
Prior art keywords
impurity
leads
substance layers
resin
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26225986A
Other languages
Japanese (ja)
Inventor
Yasuo Nakane
中根 康夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP26225986A priority Critical patent/JPS63115350A/en
Publication of JPS63115350A publication Critical patent/JPS63115350A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent an impurity from intruding in the interior of the title device, such as to a chip through wires, by a method wherein the impurity which has intruded once in a sealing resin is trapped in third substance layers located before wire-bonding positions. CONSTITUTION:Third substance layers 5 easily to react with an impurity are each applied between inner lead parts 3 and wire-bonding parts 4 out of parts to be sealed with the resin 2 of leads 1. These third substance layers 5 have only to be ones easy to react faster with an impurity than with the materials being used for the leads 1 and so on. For example, in the leads 1 using an Fe-Ni alloy as its material and in the case of an impurity consisting of water containing Na<+> ions and water containing Cl ions, a layer consisting of a substance of an ionization tendency higher than that of the Fe-Ni alloy is applied on the leads 1. Thereby, Na<+> and Cl<-> which came intruding react, a compound is produced in these third substance layers 5 and the Na<+> and Cl<-> are prevented from intruding inside more beyond these third substance layers 5. Moreover, the positions to be applied are so contrived as to be not the whole leads 1 in the sealing resin 2 and as to never come into contact to wires 6 at wire- bonding positions 4.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、外部から侵入した不純物により、半導体素子
が劣化するのを防ぐための樹脂封止型半導体装置に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a resin-sealed semiconductor device for preventing semiconductor elements from deteriorating due to impurities entering from the outside.

従来の技術 従来のパッケージ内不純物侵入防止対策を施したものの
例を第2図a、bの開封平面図、断面図に示す。この例
では、リード1のワイヤボンド部4に金メッキ7を行い
、リード1と封止樹脂2の密着性を良くすることにより
、リード1と封止樹脂2の界面を伝って不純物が侵入す
るのを訪いだ。
BACKGROUND OF THE INVENTION An example of a conventional package in which measures are taken to prevent impurities from entering the package is shown in the unsealed plan view and cross-sectional view of FIGS. 2a and 2b. In this example, gold plating 7 is applied to the wire bond part 4 of the lead 1 to improve the adhesion between the lead 1 and the sealing resin 2, thereby preventing impurities from entering through the interface between the lead 1 and the sealing resin 2. I visited.

発明が解決しようとする問題点 従来の技術のように、外部からの不純物の侵入を防ぐた
めに、リードと封止樹脂の密着性を良くする方法では、
−度侵入した不純物に対する処置が考慮されていないた
め、侵入した不純物による汚染、腐食等を防ぐことがで
きない。
Problems to be Solved by the Invention In conventional techniques, methods of improving the adhesion between the leads and the sealing resin in order to prevent impurities from entering from the outside,
- Because no consideration is given to measures against impurities that have entered the system, it is not possible to prevent contamination, corrosion, etc. caused by the impurities that have entered.

問題点を解決するための手段 本発明は、上記問題点を解決するため、インナーリード
の一部表面に第3物質層を設け、外部がら侵入した不純
物をこの第3物質層と反応させて安定な化合物に変えて
、それ以上内部に侵入しないようにするものである。
Means for Solving the Problems In order to solve the above problems, the present invention provides a third material layer on a part of the surface of the inner lead, and stabilizes impurities that have entered from the outside by reacting with the third material layer. This is to prevent it from entering the interior any further by changing it to a chemical compound.

作用 本発明により、リード線を伝っての外部からの不純物の
侵入を、第3物質層によって有効に防ぐだけでなく、−
度侵入した不純物が、さらに内部に侵入するのを防ぐこ
とができる。
According to the present invention, the third material layer not only effectively prevents impurities from entering from the outside through the lead wires, but also -
It is possible to prevent impurities that have already entered the interior from further entering the interior.

実施例 第1図aおよびbは、本発明の樹脂封止型半導体装置の
実施例の開封状態の平面図および断面図を示す。リード
1の樹脂2により封止される部分のうちインナーリード
部3からワイヤボンド部4までの間に不純物の反応しや
すい第3物質層5を塗布する。
Embodiment FIGS. 1a and 1b show a plan view and a cross-sectional view of an embodiment of the resin-sealed semiconductor device of the present invention in an unsealed state. A third material layer 5 that is easily reacted with impurities is applied between the inner lead portion 3 and the wire bond portion 4 of the portion of the lead 1 to be sealed with the resin 2 .

この第3物質層5は、リード1等に使われている材料よ
りも不純物と反応しやすいものであればよく、たとえば
、Fe−Ni合金を材料とするり−ド1でNa+イオン
を含む水や、Ceイオンを含む水からの不純物の場合、
Fe−Niよりもイオン化傾向の高いZnやMgをFe
−Niリード1に塗布することにより、侵入してきたN
a+、Ce−はZn。
This third material layer 5 may be made of any material that reacts more easily with impurities than the material used for the lead 1 etc. For example, if the lead 1 is made of Fe-Ni alloy, water containing Na+ ions is used. In the case of impurities from water containing Ce ions,
Zn and Mg, which have a higher ionization tendency than Fe-Ni, are
-By coating Ni lead 1, the intruded N
a+ and Ce- are Zn.

Mgと反応して、この第3物質層S中で化合物を生成す
るこのため、この第3物質層5よりも内部にNa”、 
C(1−が侵入するのを防ぐことができる。
Reacts with Mg to produce a compound in this third material layer S. Therefore, Na'',
C(1- can be prevented from entering.

また、塗布する位置は、封止樹脂2内のり−ド1全体で
なく、ワイヤボンド4位置より先端のり一ド1には塗布
せず、ワイヤポンド4位置でワイヤ6と接触することの
ないようにする。
Also, the position to be applied is not on the entire glue 1 in the sealing resin 2, but on the tip of the glue 1 from the wire bond 4 position, so that it does not come into contact with the wire 6 at the wire bond 4 position. do.

なお、図面ではリード1の表裏に塗布しているが、表だ
けの塗布でもよい。
Although the drawing shows the coating applied to the front and back sides of the lead 1, the coating may be applied only to the front side.

発明の効果 以上述べてきたように、本発明の方法によれば、−度封
止樹脂内に侵入した不純物をワイヤボンド位置の前にあ
る第3物質層にトラップすることができ、さらに、その
不純物がワイヤからチップへと内部に侵入することも防
ぐことができる。
Effects of the Invention As described above, according to the method of the present invention, impurities that have penetrated into the sealing resin can be trapped in the third material layer in front of the wire bonding position, and It is also possible to prevent impurities from entering the chip from the wire.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aおよびbは本発明実施例装置の開封平面図およ
び断面図、第2図a、bは従来例装置の開封状態の平面
図、断面図である。 1・・・・・・リード、2・・・・・・封止樹脂、3・
・・・・・インナーリード部、4・・・・・・ワイヤボ
ンド部、5・・・・・・第3物質層、6・・・・・・ワ
イヤ。 代理人の氏名 弁理士 中尾敏男 ほか1名イー−−1
ハト” C−一一フイγ 第2図
1A and 1B are an unsealed plan view and a sectional view of the device according to the present invention, and FIGS. 2A and 2B are a plan view and a sectional view of the conventional device in an unsealed state. 1...Lead, 2...Sealing resin, 3.
... Inner lead part, 4 ... Wire bond part, 5 ... Third material layer, 6 ... Wire. Name of agent: Patent attorney Toshio Nakao and 1 other person E-1
Pigeon” C-11F γ Figure 2

Claims (1)

【特許請求の範囲】[Claims] パッケージ内のインナーリードの一部表面上に、外部か
らの侵入不純物と反応しやすい第3物質層を設けたこと
を特徴とする樹脂封止型半導体装置。
A resin-sealed semiconductor device characterized in that a third material layer that easily reacts with impurities entering from the outside is provided on a part of the surface of an inner lead in a package.
JP26225986A 1986-11-04 1986-11-04 Resin-sealed semiconductor device Pending JPS63115350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26225986A JPS63115350A (en) 1986-11-04 1986-11-04 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26225986A JPS63115350A (en) 1986-11-04 1986-11-04 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS63115350A true JPS63115350A (en) 1988-05-19

Family

ID=17373293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26225986A Pending JPS63115350A (en) 1986-11-04 1986-11-04 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS63115350A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9573501B2 (en) 2012-04-20 2017-02-21 Johnson Controls Technology Company Vehicle seat

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915993A (en) * 1972-06-07 1974-02-12
JPS61152048A (en) * 1984-12-26 1986-07-10 Akita Denshi Kk Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915993A (en) * 1972-06-07 1974-02-12
JPS61152048A (en) * 1984-12-26 1986-07-10 Akita Denshi Kk Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9573501B2 (en) 2012-04-20 2017-02-21 Johnson Controls Technology Company Vehicle seat

Similar Documents

Publication Publication Date Title
US5530284A (en) Semiconductor leadframe structure compatible with differing bond wire materials
JPS58207657A (en) Manufacture of semiconductor device
JPH08116016A (en) Lead frame and semiconductor device
JPS63115350A (en) Resin-sealed semiconductor device
JPH0691125B2 (en) Semiconductor device
JPS6437043A (en) Resin-sealed semiconductor device
JPS62296528A (en) Resin-sealed semiconductor device
JPS6035552A (en) Semiconductor device
JPH03105950A (en) Package of semiconductor integrated circuit
JPS62183150A (en) Semiconductor device
JPS61244053A (en) Lead frame
JPH0418698B2 (en)
JPS6221250A (en) Resin-sealed semiconductor device and manufacture thereof
JPH04155949A (en) Resin-sealed semiconductor device
JPH01191456A (en) Semiconductor device
JPS59144159A (en) Plastic-sealed ic
JPH0526760Y2 (en)
JPS61168948A (en) Leadframe for semiconductor device and semiconductor device using same
JPH02172265A (en) Resin seal type semiconductor device
JP2532821B2 (en) Semiconductor device
JPH03169057A (en) Semiconductor device
KR200295664Y1 (en) Stack semiconductor package
JPS57155737A (en) Package structure of semiconductor element
JPH0498861A (en) Resin sealed type semiconductor device
JPH01204460A (en) Lead frame for semiconductor device