JPS6221250A - Resin-sealed semiconductor device and manufacture thereof - Google Patents
Resin-sealed semiconductor device and manufacture thereofInfo
- Publication number
- JPS6221250A JPS6221250A JP60160257A JP16025785A JPS6221250A JP S6221250 A JPS6221250 A JP S6221250A JP 60160257 A JP60160257 A JP 60160257A JP 16025785 A JP16025785 A JP 16025785A JP S6221250 A JPS6221250 A JP S6221250A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead frame
- wire
- chip
- molded body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特にガラス蓋部を有する樹脂封止
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a resin-sealed semiconductor device having a glass lid.
線照射により半導体チップに記憶されたメモリ内容を消
去することができる半導体装置のパッケージにおいては
、パッケージの一部に透明窓を設ける必要があり、通常
そのパッケージ構造は第１０図、第１１図に示すように
窓部な有するセラミックパッケージ２０を使用しガラス
板２１を窓部にＢめ合わせてガラス封止する構造を有す
る。上記ＥＰ−ＲＯＭパッケージの一例が（株）日立製
作所発行「昭和５９年９月日立ＩＣメモリデータブック
」の１３ページに記載されている。なお、第１０図、第
１１図において、２２はＥＰ−ＲＯＭ半導体チップ、２
３はリードである。In a semiconductor device package in which the memory contents stored in the semiconductor chip can be erased by radiation irradiation, it is necessary to provide a transparent window in a part of the package, and the package structure is usually shown in Figs. 10 and 11. As shown, it has a structure in which a ceramic package 20 having a window portion is used, a glass plate 21 is aligned with the window portion B, and the glass is sealed. An example of the above EP-ROM package is described on page 13 of "Hitachi IC Memory Data Book, September 1980" published by Hitachi, Ltd. In addition, in FIGS. 10 and 11, 22 is an EP-ROM semiconductor chip;
3 is the lead.
上記窓つきセラミックパッケージは、耐湿性は極めて良
いものの高価であり、低コスト化の要求が強い。高価で
ある理由は、前記ガラス板２２であるサファイヤガラス
自体が高価であること及びセラミックにガラス板２２を
はめ込む作業工費が高価であることによる。Although the windowed ceramic package has excellent moisture resistance, it is expensive, and there is a strong demand for cost reduction. The reason why it is expensive is that the sapphire glass itself that is the glass plate 22 is expensive, and the work cost for fitting the glass plate 22 into ceramic is expensive.
本発明者は、上記事実に鑑み本発明をなした。The present inventor made the present invention in view of the above facts.
本発明は上記した問題点を解決するためになされたもの
である。本発明の一つの目的は低価格で提供できるＥＰ
−ＲＯＭパッケージを提供することにある。The present invention has been made to solve the above-mentioned problems. One object of the present invention is to provide an EP that can be provided at a low price.
-Providing ROM packages.
本発明の他の一つの目的は、ＥＰ−ＲＯＭ用パッケージ
のプラスチック化を実現することである。Another object of the present invention is to realize a plastic package for EP-ROM.
本発明の前記ならびにその他の目的と新規な特徴は本明
細書の記述及び添付図面からあきらかになるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ＥＰ−ＲＯＭ半導体チップをリードフレーム
上に接着し、上記チップ上側で開口しリードフレームを
包含するケース状の樹脂成形体を形成し、この樹脂成形
体の開口部に透明ガラス蓋部を溶着又は接着した樹脂封
止形のパッケージであって、在来のセラミックパッケー
ジに比して低価格のＥＰ−ＲＯＭパッケージを提供する
ものである。That is, an EP-ROM semiconductor chip is bonded onto a lead frame, a case-shaped resin molded body is formed that opens above the chip and encloses the lead frame, and a transparent glass lid is welded to the opening of this resin molded body. Alternatively, the EP-ROM package is a bonded resin-sealed package, which is lower in price than a conventional ceramic package.
第１図乃至第９図は本発明の一実施例を示し、樹脂封止
形ＥＰ−ＲＯＭ半導体装置とその組立工程断面図（一部
平面図）により示すものである。FIGS. 1 to 9 show one embodiment of the present invention, and are illustrated by cross-sectional views (partial plan views) of a resin-sealed EP-ROM semiconductor device and its assembly process.
以下各工程にそって詳述する。Each step will be explained in detail below.
＋１１ リードフレーム上にＥＰ−ＲＯＭ半導体チッ
プを接続する。（＄１図）
丁なゎち、ウニ、−からＸ方向にスクライビングして分
割したＳｉ半半導体チップ上リード２とタブ３からなる
リードフレームのタブ３上に高温でこすりつける（ヌク
ラブ）ことにより生成したＡｕＳｉ共晶を介してチップ
ボンディングを行う。+11 Connect the EP-ROM semiconductor chip on the lead frame. (Figure $1) By scribing and dividing the Si semi-semiconductor chip in the X direction from the top and bottom and rubbing it at high temperature on the tab 3 of the lead frame consisting of the lead 2 and tab 3. Chip bonding is performed via the generated AuSi eutectic.
次いでチップ表面に露出するＡＪ３電極（パッド）とリ
ードフレームの各リード２との間をＡ２ワイヤ４により
ワイヤボンディングする。Next, wire bonding is performed using A2 wires 4 between the AJ3 electrode (pad) exposed on the chip surface and each lead 2 of the lead frame.
（２） このあと、リードフレーム側を陽極としてＡ
ｌの陽極醸化を行なってＡｌワイヤ４表面にアルミナ（
Ａ Ｅ ｔ Ｏｓ ）の絶縁保護膜６を形成する。(2) After this, use A with the lead frame side as the anode.
Alumina (
An insulating protective film 6 of A E t Os ) is formed.
第２図において、５はＡｌ電極（ポンディングパッド）
、７はノ弓シベーシヲン膜たとえばＳｉｎ。In Figure 2, 5 is an Al electrode (ponding pad)
, 7 is a no-yubishi base film, for example, Sin.
膜である。It is a membrane.
（３）リードフレーム（２，３）の下面に絶縁物の板８
、たとえばガラス板又は高融点合成樹脂板を接着する。(3) Insulating plate 8 on the bottom surface of the lead frame (2, 3)
For example, a glass plate or a high melting point synthetic resin plate is bonded.
（第３図）このときの絶縁物板８はワイヤボンディング
領域ａよりも広い面積をもつものとする０リードフレー
ムへの絶縁物板８の接着は絶縁熱硬化性の接着剤たとえ
ばエポキシ樹脂を用い、加熱することにより安定接合さ
せる。(Figure 3) At this time, the insulator plate 8 shall have a larger area than the wire bonding area a.0 The insulator plate 8 is bonded to the lead frame using an insulating thermosetting adhesive such as an epoxy resin. , Stable bonding is achieved by heating.
（４） 金型（上型９．下型１０）内に上記リードフ
レームを装填しレジン（樹脂）１１のモールドを行って
第１次樹脂成形体１３を形成する。このとき使用する金
型の上型９はチップ１とワイヤボンディング領域ａを囲
む筒状部１２を有し、この筒状部１２先端をリードフレ
ーム２上に押し当てて隙間なく接触させ、チップとワイ
ヤボンディング領域にはレジン１１が入りこまないよう
にしてレジンを注入硬化させる。（第４図）
（５）金型から取り出した第１次樹脂成形体（仮封正体
）１３は第５図及び第６図（平面図）Ｋ示すように、チ
ップ１とワイヤボンディング領域ａの上側が開口するケ
ース状のものとなる。樹脂成形後、外側に突出するり一
ド表面の人！酸化物は酸洗い等により取り除く。(4) The lead frame is loaded into a mold (upper mold 9, lower mold 10) and molded with resin 11 to form a primary resin molded body 13. The upper die 9 of the mold used at this time has a cylindrical part 12 that surrounds the chip 1 and the wire bonding area a. The resin is injected and hardened while preventing the resin 11 from entering the wire bonding area. (Fig. 4) (5) The primary resin molded body (temporary sealing body) 13 taken out from the mold is located between the chip 1 and the wire bonding area a, as shown in FIGS. It is case-like with an open top. After resin molding, the curved surface protrudes outward! Oxides are removed by pickling, etc.
（６）上記樹脂成形体１３の開口部に安価な透明ガラス
板】４又は透明樹脂板をはめこみ、溶着又は接着剤を用
いて接着封止する。（第７図）（７）再び金型内１５．
１６に第１次樹脂成形体１３を入れレジン１７でモール
ドを行って第２次樹脂成形体１９を形成する。この場合
に使用する金型の上型】５は第８図に示すように上記透
明板１４に対向する突出部１８を有し、透明板面１４に
隙間なく接触させてレジン１７が透明板１４に付着しな
いようにする。しかし、第２次樹脂成形体１９は透明板
１４と第１次樹脂成形体１３との隣接する部分を充分に
埋めこんで覆うよ５に形成される。(6) An inexpensive transparent glass plate [4] or a transparent resin plate is fitted into the opening of the resin molded body 13 and sealed by welding or using an adhesive. (Figure 7) (7) Inside the mold again 15.
The first resin molded body 13 is placed in a tube 16 and molded with resin 17 to form a second resin molded body 19 . The upper die 5 used in this case has a protrusion 18 facing the transparent plate 14 as shown in FIG. Avoid adhesion to However, the second resin molded body 19 is formed so as to sufficiently embed and cover the adjacent portions of the transparent plate 14 and the first resin molded body 13.
（８）第２次樹脂成形体１９を金型から取出し、リード
フレームの突出部分でリード間を接続するダム部を切り
取ってリード間を電気的に分離する。(8) Take out the secondary resin molded body 19 from the mold, and cut out the dam portion that connects the leads at the protruding portion of the lead frame to electrically isolate the leads.
第９図は完成した樹脂封止形ＥＰ−ＲＯＭ半導体装置の
断面図を示す。FIG. 9 shows a sectional view of the completed resin-sealed EP-ROM semiconductor device.
以上実施例で述べた本発明によれば下記のように効果が
得られる。According to the present invention described in the embodiments above, the following effects can be obtained.
（１）パッケージは２重の樹脂成形体により形成されて
いるため充分にパッケージの耐湿性を保持でき、高耐湿
性樹脂封止半導体装置が提供できる０ｆ２１ ＡＡｔ
極電極及びＡＡワイヤ部分は’ｅｍ性酸化Ｋ （Ａｉｔ
Ｏｓ ）で覆われていることにより、水の進入があっ
てもＡｌｘ ＯｓでＡノワイヤが保護されるため、Ａ！
ワイヤの耐湿性を向上できる。(1) Since the package is formed of a double resin molded body, the moisture resistance of the package can be sufficiently maintained, and a highly moisture resistant resin-sealed semiconductor device can be provided.
The electrode and AA wire parts are made of 'em oxidized K (Ait
Os), even if water enters, the A wire is protected by Alx Os, so A!
The moisture resistance of the wire can be improved.
（３）セラミックを使用することなく、樹脂封止でＥＰ
−ＲＯＭパッケージを形成し、かつ安価なガラス板を使
用するため、材料費、製造コストが安価となるとともに
、その樹脂封止半導体装置は高耐湿性であり、安価でか
つ高信頼の樹脂半導体装置を提供できる。(3) EP with resin sealing without using ceramics
- Since the ROM package is formed and an inexpensive glass plate is used, material costs and manufacturing costs are low, and the resin-sealed semiconductor device has high moisture resistance, making it an inexpensive and highly reliable resin semiconductor device. can be provided.
以上発明者によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなくその主旨を逸脱しない範囲で種々変更可能で
あることは言うまでもない。Although the invention made by the inventor has been specifically explained above based on the examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the spirit thereof.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＥＰ−ＲＯＭパッケ
ージ技術に適用した場合について説明したが、それに限
定されるものではない。In the above description, the invention made by the present inventor has been mainly applied to the EP-ROM packaging technology, which is the background field of application, but the invention is not limited thereto.
本発明は少なくとも透明窓を有する半導体装置の樹脂封
止技術に適用できる。The present invention can be applied to at least resin sealing technology for semiconductor devices having transparent windows.
第１図乃至第９図は本発明の一実施例を示すＥＰ−ＲＯ
Ｍパッケージ製造プロセスにおける工程図であって、こ
のうち、第１図、第３図〜第５図、第７図〜第９図は断
面図、第２図は一部拡大断面図、第６図は第５図に対応
する平面図である。
＠１０図は従来のＥＦＲＯＭパッケージの形状を示す斜
面図、
第１１図は第１０図の縦断面図である。
１・・・半導体チップ、２・・・リード、３・・・タブ
、４・・・ワイヤ、５・・・Ａｌｘ極、６・・・人！酸
化膜、７・・・バクシベイシコン膜、８・・・絶縁板、
９，１０・・・金型、１１・・・レジン、１２・・・筒
状部、１３・・・第１樹脂成形体、１４・・・透明板、
１５．１６・・・金型、１７・・・レジン、１８・・・
突出部、１９・・・第２樹脂成形体、２０・・・セラミ
ックパッケージ、２１・・・ガラ゛・１．！１．ノ′
第 １ 図
第 ２ 図
第 ３ 図
ａ、
第 ４ 図
第 ５ 図
α
グ ／３
第 ６ 図
第 ７ 図
／、）’ Ｉ１７
第 ８ 図
第 ９ 図
第１０図FIG. 1 to FIG. 9 are EP-RO diagrams showing one embodiment of the present invention.
FIG. 1, FIG. 3 to FIG. 5, and FIG. 7 to FIG. 9 are sectional views, FIG. 2 is a partially enlarged sectional view, and FIG. is a plan view corresponding to FIG. 5; @Figure 10 is a perspective view showing the shape of a conventional EFROM package, and Figure 11 is a longitudinal sectional view of Figure 10. 1... Semiconductor chip, 2... Lead, 3... Tab, 4... Wire, 5... Alx pole, 6... Person! Oxide film, 7... Bakshibasicon film, 8... Insulating plate,
9, 10... Mold, 11... Resin, 12... Cylindrical part, 13... First resin molded body, 14... Transparent plate,
15.16...Mold, 17...Resin, 18...
Projection portion, 19... Second resin molded body, 20... Ceramic package, 21... Glass 1. ! 1.ノ' Figure 1 Figure 2 Figure 3 a, Figure 4 Figure 5 Figure α /3 Figure 6 Figure 7/, )' I17 Figure 8 Figure 9 Figure 10
Claims (1)
ップの電極とリードフレームとを電気的に接続するワイ
ヤとを具備し、前記半導体チップ周縁に位置するリード
フレームとワイヤとの接続部で形つくられる領域内が開
口し、リードフレーム裏面を包含する樹脂封止体と、上
記開口部上側で上記樹脂封止体と密封する透明蓋部とか
らなることを特徴とする樹脂封止半導体装置。 ２、リードフレーム上に半導体チップを接続した後、前
記半導体チップの電極とリードフレームとをワイヤで接
続する工程、上記リードフレームとワイヤとの接続点で
囲まれ、内部に前記チップを含む領域上が開口するよう
に、かつ、前記リードフレーム裏面を含む第１の樹脂成
形体を形成する工程、上記チップ上側で樹脂成形体の開
口部に透明板を溶着又は接着して封止を行う工程、上記
透明板の上面を露出し、透明板と第１の樹脂成形体との
接合部を少なくとも覆うように第２の樹脂成形体を形成
する工程とからなる樹脂封止半導体装置の製造方法。 ３、上記第１の樹脂成形体を形成する際にリードフレー
ムの下面に絶縁板を接合させた状態で行う特許請求の範
囲第２項に記載の樹脂封止半導体装置の製造方法。[Claims] 1. A semiconductor chip, a lead frame, and a wire that electrically connects an electrode of the semiconductor chip and the lead frame, the lead frame and the wire being located at the periphery of the semiconductor chip. A resin seal comprising a resin seal with an opening in the area formed by the connection portion and encompassing the back surface of the lead frame, and a transparent lid portion that seals with the resin seal above the opening. Stop semiconductor device. 2. After connecting the semiconductor chip on the lead frame, the step of connecting the electrode of the semiconductor chip and the lead frame with a wire, on the area surrounded by the connection point of the lead frame and the wire and containing the chip inside a step of forming a first resin molded body including the back surface of the lead frame so as to be open; a step of sealing by welding or gluing a transparent plate to the opening of the resin molding above the chip; A method for manufacturing a resin-sealed semiconductor device, comprising the steps of exposing the upper surface of the transparent plate and forming a second resin molded body so as to cover at least a joint between the transparent plate and the first resin molded body. 3. The method for manufacturing a resin-sealed semiconductor device according to claim 2, which is carried out in a state in which an insulating plate is bonded to the lower surface of the lead frame when forming the first resin molded body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60160257A JPS6221250A (en) | 1985-07-22 | 1985-07-22 | Resin-sealed semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60160257A JPS6221250A (en) | 1985-07-22 | 1985-07-22 | Resin-sealed semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6221250A true JPS6221250A (en) | 1987-01-29 |
Family
ID=15711093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60160257A Pending JPS6221250A (en) | 1985-07-22 | 1985-07-22 | Resin-sealed semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6221250A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4974052A (en) * | 1988-10-14 | 1990-11-27 | Mitsubishi Denki Kabushiki Kaisha | Plastic packaged semiconductor device |
| US5106785A (en) * | 1989-01-16 | 1992-04-21 | Siemens Aktiengesellschaft | Method for encapsulating electronic components or assemblies using a thermoplastic encapsulant |
| US6274927B1 (en) * | 1999-06-03 | 2001-08-14 | Amkor Technology, Inc. | Plastic package for an optical integrated circuit device and method of making |
-
1985
- 1985-07-22 JP JP60160257A patent/JPS6221250A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4974052A (en) * | 1988-10-14 | 1990-11-27 | Mitsubishi Denki Kabushiki Kaisha | Plastic packaged semiconductor device |
| US5106785A (en) * | 1989-01-16 | 1992-04-21 | Siemens Aktiengesellschaft | Method for encapsulating electronic components or assemblies using a thermoplastic encapsulant |
| US5376824A (en) * | 1989-01-16 | 1994-12-27 | Siemens Aktiengesellschaft | Method and an encapsulation for encapsulating electrical or electronic components or assemblies |
| US6274927B1 (en) * | 1999-06-03 | 2001-08-14 | Amkor Technology, Inc. | Plastic package for an optical integrated circuit device and method of making |
| US6420204B2 (en) | 1999-06-03 | 2002-07-16 | Amkor Technology, Inc. | Method of making a plastic package for an optical integrated circuit device |
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