JPS6130057A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6130057A JPS6130057A JP15190384A JP15190384A JPS6130057A JP S6130057 A JPS6130057 A JP S6130057A JP 15190384 A JP15190384 A JP 15190384A JP 15190384 A JP15190384 A JP 15190384A JP S6130057 A JPS6130057 A JP S6130057A
- Authority
- JP
- Japan
- Prior art keywords
- seal ring
- semiconductor device
- metal
- chip
- package body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体チップを収納するチップ収納凹部を
有したパッケージ本体とこのパッケージ本体のチップ収
納凹部を密封する蓋体とを備えた半導体装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device including a package body having a chip storage recess for storing a semiconductor chip, and a lid body for sealing the chip storage recess of the package body. It is something.
第１図は例えば〔日本マイクロエレクトロニクス協会編
１９８１年１月２５日発行’ＩＣ化実装技術。Figure 1 shows, for example, ``IC Mounting Technology'' edited by Japan Microelectronics Association, published January 25, 1981.
−Ｐ１Ｂ７図６．８ （ｅ） ）に示されているような
この種の中空プラスチックタイプの半導体装置であシ、
図１ζおいて（１）及び＜２） １．を薄い金属板から
なるリードフレームのリード及びダイパッド、（３）は
このダイパッド＜２） 、ｔ：にハンダ等によって付着
され、リード（１）とはボンディングワイヤ（４）を介
して電気的に接続される半導体チップ、（６）はリード
（１）及びダイパッド（２Ｊと一体成形され、半：８体
チップ（３）が収納される収納部（６）を有した樹脂か
らなるパッケージ本体、（７）はこのパラ・ケージ本体
（５）に樹脂接着剤（８）を用いて接着された蓋体であ
る。-P1B7 This kind of hollow plastic type semiconductor device as shown in Figure 6.8 (e))
(1) and <2) in Figure 1ζ 1. is the lead and die pad of the lead frame made of a thin metal plate, (3) is attached to this die pad <2), t: by solder, etc., and is electrically connected to the lead (1) via a bonding wire (4). The semiconductor chip (6) is integrally molded with the leads (1) and the die pad (2J), and the package body (7) is made of resin and has a housing part (6) in which the half-eight chip (3) is housed. ) is a lid that is adhered to the para-cage body (5) using a resin adhesive (8).
このように構成された半導体装置に於ては、樹脂からな
るパッケージ本体（５）と蓋体（７）とを樹脂接着剤（
８）にて接着゛しているため、耐湿性等の面がら性に問
題を有するものであった。In the semiconductor device configured in this way, the package body (5) and the lid body (7) made of resin are bonded together using a resin adhesive (
8), there were problems with surface properties such as moisture resistance.
この発明は上記した点に鑑みてなされたものであシ、半
導体チップを収納するチップ収納凹部を有する樹脂から
なるパッケージ本体と、このパッケージ本体のチップ収
納凹部を密封する蓋体とを備えたものにおいて、パッケ
ージ本体のチップ収納凹部開口端全周に亘って少なくと
も表面が露出して埋込まれたシールリングを設けるとと
もに蓋体のシールリング対向面を少なくとも金属面とし
て、この金属面とシールリングとを金属接合するように
し、パッケージ本体におけるチップ収納凹部の密封性を
高めるとと−に耐湿性等に対し信頼性に富む半導体装置
を提案するものである。The present invention has been made in view of the above points, and includes a package body made of resin having a chip storage recess for storing a semiconductor chip, and a lid body that seals the chip storage recess of the package body. A seal ring is provided with at least the surface exposed and embedded over the entire circumference of the open end of the chip storage recess of the package body, and the surface of the lid body facing the seal ring is at least a metal surface, and the metal surface and the seal ring are connected to each other. The present invention proposes a semiconductor device that is highly reliable in terms of moisture resistance and the like, by metal-bonding the chips and improving the sealing performance of the chip-accommodating recess in the package body.
以下にこの発明の一実施例を第２図及び第８図に基づい
て説明すると、図において、ｅ）は薄い金属板のリード
（１１）及びグイバット（ロ）よりなシ、グイバット（
ロ）がリード（２）に対し窪んだ形状のリードフレーム
、幹はリードフレーム■及びレールリング（２）と一体
成形され、半導体チップ（３）を収納するテップ収納部
（６）を有した熱硬化性樹脂に無機質充てん材を混合し
た樹脂からなるパッケージ本体で、チップ収納凹部（６
）の底面（Ｓａ） Ｓつまレダイパットａη載置面、が
リードＯすの載置面（９ｂ）より低く形成されているも
のである。ａａは上記チップ収納凹部（６）に於ける開
口端全周に頁って表面が露出して埋込まれ、パッケージ
本体口の接合部分とｒＪる裏面に粗い凹凸を有する金Ｆ
ｌ製のレールリングで、パッケージ本体いを形成する際
に一体的醗ζ成形されるものである。Ｑ（ｌはこのシー
ルリング６場にろう材四により接着されたコバール等の
金属からひる蓋体であるー
次にこの杼に構成された半導体装置の製造方法を説明す
る。まず、リードフレーム■及びシールリングＧ３を一
体醗ζしてパッケージ本体（ロ）を形成し、次に半導体
チップ（３）をダイパッド←℃に装着した後、半導体チ
ップ（３）の所望の電極・と、リード叫とのワイヤボン
ドを行う。その後高温状態にて溶けているろう材、例え
ば２１０″Ｃ程度で溶けている半田を用いて、パッケー
ジ本体（ロ）に埋込まれたシールリング（至）の露出表
面と蓋体α４におけるＪ：Ｅ露出表面に対向する面とを
接合し、を記チップ収納凹部（６）を密封させ、完成さ
せるものである。この時ろう材（ト）が高温状態１とな
るものの、シールリング（至）が金属であるため溶解す
ることはなく、シかも、樹脂からなるパッケージ本体（
ロ）に対してもシールリング謁が温度に対し緩和作用を
果たすため、パッケージ本体口における温度の影響もほ
とんどないものである。An embodiment of the present invention will be explained below based on FIG. 2 and FIG.
(b) is a lead frame with a recessed shape relative to the lead (2); the trunk is integrally molded with the lead frame (■) and the rail ring (2); The package body is made of resin that is a mixture of hardening resin and inorganic filler, and has a chip storage recess (6
) The bottom surface (Sa) of the lead die pad aη mounting surface is formed lower than the mounting surface (9b) of the lead O. aa is a gold F which is embedded around the entire circumference of the opening end of the chip storage recess (6) with its surface exposed and has rough irregularities on the back surface where it connects to the opening of the package body.
This rail ring is made of aluminum and is integrally molded when forming the package body. Q (l is a lid made of metal such as Kovar that is bonded to this seal ring 6 with a brazing filler metal 4.Next, we will explain the manufacturing method of the semiconductor device configured in this shuttle.First, the lead frame and the seal ring G3 are integrally assembled to form the package body (b), and then the semiconductor chip (3) is attached to the die pad ←°C, and then the desired electrodes and lead screams of the semiconductor chip (3) are attached. Then, using a brazing material melted at high temperature, for example, solder melted at about 210"C, bond the exposed surface of the seal ring (to) embedded in the package body (b). The surface opposite to the J:E exposed surface of the lid body α4 is joined, and the chip storage recess (6) is sealed to complete the process. Since the seal ring is made of metal, it will not melt, and the package body made of resin (
Regarding (b), the seal ring has a moderating effect on temperature, so there is almost no effect of temperature on the package body opening.
従って、上記の様に構成された半導体装置にあってはシ
ールリング（至）がパッケージ本体＠に埋込まれ、この
シールリング（至）と蓋体（ロ）とをろう材（至）にて
接合しているため、第１図に示した樹脂接着材にて接合
したものに対しチップ収納凹部（６）の密封構造は高め
られ、かつ良好な耐湿性が得られるものである。Therefore, in the semiconductor device configured as described above, the seal ring (1) is embedded in the package body @, and the seal ring (1) and the lid body (2) are connected using a brazing material (2). Since they are bonded together, the sealing structure of the chip storage recess (6) is improved compared to that shown in FIG. 1 which is bonded with a resin adhesive, and good moisture resistance can be obtained.
第４因はこの発明の他の実施例を示すものであシ、上記
第２図に示したものに対し、シールリνグ（至）におけ
るチップ収納凹部（６）開口端表面の一部をパッケージ
本体口で覆うようにしたものである。The fourth factor shows another embodiment of the present invention, and in contrast to the one shown in FIG. It is designed to be covered by the mouth of the main body.
このよう１こすればシールリング（至）の固定強度は高
まシ更にはチップ収納凹部（６）の密封性も高まるもの
である。In this way, by rubbing once, the fixing strength of the seal ring (to) is increased, and the sealing performance of the chip storage recess (6) is also improved.
なお、を記実施例に於ては金属の蓋体０＜とシールリン
グ０３との接合をろう材−を用いて行ったが、蓋体Ｑ４
１とシールリング（２）とを電気抵抗溶接によって直接
付着しても良くその際には、シールリング（至）及び蓋
体ａくを橘成する金属に電気抵抗溶接の可能なものを用
いれば良い。In addition, in the embodiment described above, the metal lid Q4 was joined to the seal ring 03 using a brazing material.
1 and the seal ring (2) may be directly attached by electric resistance welding. In that case, if the metal forming the seal ring (to) and the lid body a is capable of electric resistance welding. good.
また、Ｊ：紀実施例に於ては、蓋体α◆を金属からなる
ものとしたがシールリング（２）の露出表面に対向する
面にメタライズが施さすｔた透光性のガラスあるいはシ
ールリング（至）の露出表面に対向する面にメタライズ
が施された樹脂からなるものでも良く、要は蓋体α◆と
じて、シールリング斡の無比表面に対向する面が少なく
とも金属面となっているものであわば同様の効果を奏す
るものである。In addition, in the J: period embodiment, the lid body α◆ was made of metal, but the surface opposite to the exposed surface of the seal ring (2) was made of transparent glass or a seal with metallization applied to it. It may also be made of a resin with metallization applied to the surface facing the exposed surface of the ring (to), and the point is that at least the surface facing the unrivaled surface of the seal ring □ is a metal surface as well as the lid body α◆. There are similar effects, so to speak.
この発明は以と説明した通り、半導体チップが収納され
るチップ収納凹部を有した樹脂からなるパッケージ本体
と一体、このパッケージ本体のチップ収納凹部を密封す
る蓋体とを備えたものにおいて、パッケージ本体のチッ
プ収納凹部開口端全周に亘って少なくとも表面が露出し
て埋込まれたシールリングを設け、かつ蓋体におけるシ
ールリングの露出表面と対向する面を金属面とし、この
金属面とシールリングの露出表面とを金属接合したので
、パッケージ本体におけるチップ収納凹部の密封性が向
ｔするとともにパッケージ本体と蓋体との接合部におけ
る耐湿性も向ｔするという効果を有するものである。As explained below, the present invention includes a package body made of resin having a chip storage recess in which a semiconductor chip is stored, and a lid body that seals the chip storage recess of the package body. A seal ring is provided with at least the surface exposed and embedded over the entire circumference of the opening end of the chip storage recess, and the surface of the lid body facing the exposed surface of the seal ring is a metal surface, and this metal surface and the seal ring are provided. Since the exposed surface of the package body is metal-bonded, the sealing performance of the chip storage recess in the package body is improved, and the moisture resistance of the joint between the package body and the lid body is also improved.
第１図は、従来の半導体装置を示す断面図、第る。
図に於て、（３）は半導体チップ、（６）はチップ収納
凹部、口はパッケージ本体、（至）はシールリング、α
◆は蓋体である。
なお各図中同一符号は同一または相当部分を示すものと
する。
−代理人 大岩増雄
第１図
第２図
第３図
第４図
手続補正書（自発）
ｌ、事件の表示 特願昭 ５９−１５１９０８号３
、補正をする者
代表者片由仁へ部
４、代理人
５、補正の対象
（１）明細書の発明の詳細な説明の欄。
６、補正の内容
（１）明細書中筒８頁第８行に「パッケージ本体と一体
、」とあるのを「パッケージ本体と、」と訂正する。
以上FIG. 1 is a sectional view showing a conventional semiconductor device. In the figure, (3) is the semiconductor chip, (6) is the chip storage recess, the mouth is the package body, (to) is the seal ring, α
◆ is the lid body. Note that the same reference numerals in each figure indicate the same or corresponding parts. - Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 4 Procedural amendment (voluntary) l, Indication of case Patent application No. 151908/1989 3
, To the representative of the person making the amendment, Kata Yuhito Part 4, Agent 5, Subject of amendment (1) Column for detailed explanation of the invention in the specification. 6. Contents of the amendment (1) In the eighth line of page 8 of the middle cylinder of the specification, the phrase "integrated with the package body" is corrected to "with the package body."that's all
Claims (8)
た樹脂からなるパッケージ本体と、上記チップ収納凹部
に於ける開口端全周にわたつて少なくとも表面が露出し
て埋込まれた金属からなるシールリング、このシールリ
ングの露出した表面に対向した面が少なくとも金属面か
らなり、この金属面と上記シールリングの露出表面とが
金属接合された蓋体とを備えた半導体装置。(1) A package body made of resin having a chip storage recess in which a semiconductor chip is stored, and a seal made of metal embedded with at least the surface exposed over the entire circumference of the open end of the chip storage recess. 1. A semiconductor device comprising a ring, a lid body in which the surface facing the exposed surface of the seal ring is at least made of a metal surface, and the metal surface and the exposed surface of the seal ring are metal-bonded.
る裏面が凹凸形成されているものである特許請求の範囲
第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the seal ring has an uneven back surface that becomes a bonding surface with the package body.
徴とする特許請求の範囲第１項または第２項記載の半導
体装置。(3) The semiconductor device according to claim 1 or 2, wherein the package body is made of thermosetting resin.
許請求の範囲第１項ないし第３項のいずれかに記載の半
導体装置。(4) The semiconductor device according to any one of claims 1 to 3, wherein the metal bonding is brazing.
リード載置面より低く形成されていることを特徴とする
特許請求の範囲第１項ないし第４項のいずれかに記載の
半導体装置。(5) The semiconductor device according to any one of claims 1 to 4, wherein the bottom surface of the storage recess is formed lower than the lead mounting surface of the integrally molded lead frame.
能な金属であることを特徴とする特許請求の範囲第１項
ないし第８項のいずれかに記載の半導体装置。(6) The semiconductor device according to any one of claims 1 to 8, wherein the lid and the seal ring are made of metal that can be electrically resistance welded to each other.
タライズされた樹脂からなることを特徴とする特許請求
の範囲第１項ないし第５項のいずれかに記載の半導体装
置。(7) The semiconductor device according to any one of claims 1 to 5, wherein the lid body is made of a resin whose surface facing the exposed surface of the seal ring is metalized.
タライズされたガラスからなることを特徴とする特許請
求の範囲第１項ないし第５項のいずれかに記載の半導体
装置。(8) The semiconductor device according to any one of claims 1 to 5, wherein the lid body is made of glass whose surface facing the exposed surface of the seal ring is metalized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15190384A JPS6130057A (en) | 1984-07-20 | 1984-07-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15190384A JPS6130057A (en) | 1984-07-20 | 1984-07-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6130057A true JPS6130057A (en) | 1986-02-12 |
Family
ID=15528707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15190384A Pending JPS6130057A (en) | 1984-07-20 | 1984-07-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6130057A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0928025A2 (en) * | 1997-12-27 | 1999-07-07 | TDK Corporation | Wiring board and process for the production thereof |
| JP2006121278A (en) * | 2004-10-20 | 2006-05-11 | Matsushita Electric Ind Co Ltd | Antenna system and communication system using the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5832435A (en) * | 1981-08-20 | 1983-02-25 | Nec Corp | Semiconductor device |
-
1984
- 1984-07-20 JP JP15190384A patent/JPS6130057A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5832435A (en) * | 1981-08-20 | 1983-02-25 | Nec Corp | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0928025A2 (en) * | 1997-12-27 | 1999-07-07 | TDK Corporation | Wiring board and process for the production thereof |
| EP0928025A3 (en) * | 1997-12-27 | 2000-04-12 | TDK Corporation | Wiring board and process for the production thereof |
| US6204454B1 (en) | 1997-12-27 | 2001-03-20 | Tdk Corporation | Wiring board and process for the production thereof |
| JP2006121278A (en) * | 2004-10-20 | 2006-05-11 | Matsushita Electric Ind Co Ltd | Antenna system and communication system using the same |
| JP4631388B2 (en) * | 2004-10-20 | 2011-02-16 | パナソニック株式会社 | Antenna device and communication system using the same |
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