JPS6222455B2 - - Google Patents
Info
- Publication number
- JPS6222455B2 JPS6222455B2 JP7437479A JP7437479A JPS6222455B2 JP S6222455 B2 JPS6222455 B2 JP S6222455B2 JP 7437479 A JP7437479 A JP 7437479A JP 7437479 A JP7437479 A JP 7437479A JP S6222455 B2 JPS6222455 B2 JP S6222455B2
- Authority
- JP
- Japan
- Prior art keywords
- cap
- frame
- seam
- glass
- window frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000011521 glass Substances 0.000 claims description 16
- 229910000833 kovar Inorganic materials 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000919 ceramic Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 238000007789 sealing Methods 0.000 description 8
- 239000004020 conductor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置にかかりとくに紫外線消去
型EPROMの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of an ultraviolet erasable EPROM.
紫外線消去型EPROMに使用される半導体装置
用容器（以下パツケージと呼ぶ）としては、セラ
ミツク基板に半導体素子（以下チツプと呼ぶ）を
固着する素子固着部（以下マウント部と呼ぶ）と
素子電極を外部に取り出すための導体とをメタラ
イズパターン（以下ボンデイングパツド部と呼
ぶ）により施しセラミツク基板外側に外部リード
をろう付けし、ボンデイングパツド部周辺上部に
はシールリングろう付けされている。そしてこの
パツケージに、チツプを固着した後金属細線でチ
ツプ電極とボンデイングパツド部を結線した後に
薄い金属板を絞り加工した穴部に紫外線透過硝子
を封着したキヤツプをシームウエールド封止した
ものである。 A semiconductor device container (hereinafter referred to as a package) used in an ultraviolet erasable EPROM consists of an element fixing part (hereinafter referred to as a mount part) that secures a semiconductor element (hereinafter referred to as a chip) to a ceramic substrate, and an external part for attaching the element electrodes. A metallized pattern (hereinafter referred to as the bonding pad section) is used to provide a conductor for taking out the ceramic substrate, external leads are brazed to the outside of the ceramic substrate, and a seal ring is brazed to the upper part of the periphery of the bonding pad section. After fixing the chip to this package, the chip electrodes and bonding pads are connected using thin metal wires, and then a cap is seam-welded and sealed with ultraviolet-transparent glass in the hole made by drawing a thin metal plate. It is.
従来のパツケージについて第１図の平面図と第
２図の断面図を用いて説明する。セラミツク基板
１ａにチツプ２ａを固着するマウント部３ａと素
子電極（図示せず）を外部に取り出すための導体
をメタライズパターンにより施しボンデイングパ
ツド部４ａとする。前記メタライズパターンは、
セラミツクの中間層を通つて基板外側に導出させ
外部リード５ａをろう付けしたものである。この
パツケージのマウンド部３ａにチツプ２ａを固着
した後にAl線又はAu線６ａでチツプ電極とボン
デイングパツド部４ａとを結線する。次にボンデ
イングパツド部４ａ周辺上部にろう付けされたシ
ールフレーム７ａ上には窓枠状のキヤツプ８ａが
シームウエールド封止されている。この窓枠状キ
ヤツプ８ａはコバール材を第２図の如き形状に絞
り加工した後に紫外線透過硝子商品名コーニング
コード番号9741，９ａをキヤツプ８ａに封着し
Niメツキを３〜４μ程度の厚さにメツキしたも
のである。しかしながら、このパツケージの構造
は、シームウエルド封止時の発熱により硝子が割
れることもあり、更には熱的、機械的環境試験に
対して気密性の劣化及び硝子の破壊の発生すると
いう欠点があつた。 A conventional package will be explained using a plan view in FIG. 1 and a sectional view in FIG. 2. A mount portion 3a for fixing the chip 2a to the ceramic substrate 1a and a conductor for taking out the element electrodes (not shown) are formed by a metallized pattern to form a bonding pad portion 4a. The metallization pattern is
External leads 5a are led out to the outside of the substrate through a ceramic intermediate layer and brazed to them. After the chip 2a is fixed to the mound part 3a of this package, the chip electrode and the bonding pad part 4a are connected with an Al wire or an Au wire 6a. Next, a window frame-shaped cap 8a is sealed by seam welding on a seal frame 7a which is brazed to the upper part of the periphery of the bonding pad portion 4a. This window frame-shaped cap 8a is made by drawing Kovar material into the shape shown in Figure 2, and then sealing ultraviolet transmitting glass (trade name: Corning code number 9741, 9a) to the cap 8a.
It is plated with Ni to a thickness of about 3 to 4 microns. However, this package structure has the disadvantage that the glass may crack due to the heat generated during seam weld sealing, and furthermore, the airtightness deteriorates and the glass breaks during thermal and mechanical environmental tests. Ta.
本発明は上記欠点を除去し、高信頼性、低価格
量産のある紫外線消去型EPROMを提供すること
を目的とする。 It is an object of the present invention to eliminate the above-mentioned drawbacks and provide an ultraviolet erasable EPROM that is highly reliable and mass-produced at low cost.
本発明はセラミツク基板上のシールフレームに
硝子封着した窓枠状金属キヤツプをシームウエル
ド封止する半導体装置において、絞り加工した曲
面と角穴を設けた薄いコバール金属板と充分厚い
コバール金属枠とを一体化した該枠体に紫外線透
過硝子を封着した窓枠状キヤツプをシームウエル
ド封止した事を特徴とする半導体装置である。 The present invention relates to a semiconductor device that seam-weld-seals a window frame-shaped metal cap that is sealed with glass to a seal frame on a ceramic substrate. This semiconductor device is characterized in that a window frame-shaped cap is seam-welded and sealed with ultraviolet-transparent glass on the frame body.
これにより本発明はシームウエルド構造を有し
しかも紫外線透過硝子封着部に外力が加らない構
造とする。 As a result, the present invention has a seam-weld structure and has a structure in which no external force is applied to the ultraviolet-transmissive glass sealed portion.
次に本発明を実施例により説明する。第３図は
本発明の平面図、第４図、第５図、第６図はそれ
ぞれ第１、第２、第３の実施例の断面図である。 Next, the present invention will be explained by examples. FIG. 3 is a plan view of the present invention, and FIGS. 4, 5, and 6 are sectional views of the first, second, and third embodiments, respectively.
セラミツク基板１ｂにチツプ２ｂを固着するマ
ウンド部３ｂと素子電極（図示せず）を外部リー
ドに取り出す為の導体をメタライズパターンによ
り施しボンデイングパツド４ｂとする。 A mound portion 3b for fixing the chip 2b to the ceramic substrate 1b and a conductor for taking out the element electrodes (not shown) to external leads are formed by a metallized pattern to form a bonding pad 4b.
前記メタライズパターンは、セラミツクの中間
層を通つて基板外側に導出させ外部リード５ａを
ろう付けしたものである。又、ボンデイングパツ
ド部４ｂの上部周辺にシールフレーム７ｂがろう
付けされている。このパツケージのマウンド部３
ｂにAu−Si、又はAu−Al等のろう材１４ｂを介
在させて固着した後にAl線又はAu線６ｂでチツ
プ電極とボンデイングパツド部４ｂとを結線す
る。次に気密封止するキヤツプ８ｂはコバール材
から成る中央に角穴をあけ絞り加工した成形キヤ
ツプ９ｂと紫外線透過硝子コーニングコード番号
9741，１０ｄと該硝子１０ｂを封着するコバール
金属枠１１ｂから構成されている。通常成形キヤ
ツプ９ｂは0.1〜0.2mmの厚さのコバール板を絞り
加工し中央部に角穴をあける。コバール金属枠１
１ｂは0.8〜1.0mm程度の厚さで内径が成形キヤツ
プ９ｂの穴径と一致するようにする。又、該枠１
１ｂの外径は成形キヤツプ９ｂの絞り径と一致す
るようにする。前記キヤツプ９ｂの絞り部にコバ
ール金属枠１１ｂをはめ合せて内径部分１２ｂを
抵抗溶接する。次に一体化したキヤツプのコバー
ル金属枠１１ｂの内壁面１３ｂで前記紫外線透過
硝子コーニング番号9741，１０ｂを封着するこれ
を充分除歪してからNiメツキを２〜３μ程度の
厚さにメツキする。このキヤツプ８ｂのコバール
金属枠１１ｂの外径とシールフレーム７ｂの内径
が嵌合するように設計しておくことによつて位置
決めに簡単に行えシームウエルド封止が作業よく
行える。一般的にこのタイプのパツケージの寸法
はセラミツク巾15.24ミリ、マウント径８ミリ、
シールフレーム内径10ミリ、外径12.7ミリである
から硝子封着部の径は７ミリ×７ミリ程度の大き
さが得られる。 The metallized pattern is led out to the outside of the substrate through the ceramic intermediate layer, and external leads 5a are brazed thereto. Further, a seal frame 7b is brazed around the upper portion of the bonding pad portion 4b. Mound part 3 of this package
After fixing the solder material 14b such as Au-Si or Au-Al to the bonding pad 4b, the chip electrode and the bonding pad portion 4b are connected with the Al wire or the Au wire 6b. Next, the cap 8b to be hermetically sealed is a molded cap 9b made of Kovar material with a square hole punched in the center and drawn, and an ultraviolet transparent glass Corning code number.
9741, 10d and a Kovar metal frame 11b that seals the glass 10b. The normally molded cap 9b is made by drawing a Kovar plate with a thickness of 0.1 to 0.2 mm and punching a square hole in the center. Kovar metal frame 1
1b has a thickness of about 0.8 to 1.0 mm, and its inner diameter is made to match the hole diameter of the molded cap 9b. Also, the frame 1
The outer diameter of 1b is made to match the drawing diameter of molded cap 9b. The Kovar metal frame 11b is fitted into the constricted portion of the cap 9b, and the inner diameter portion 12b is resistance welded. Next, the UV-transparent glass Corning No. 9741, 10b is sealed on the inner wall surface 13b of the Kovar metal frame 11b of the integrated cap. After this is sufficiently strained, Ni plating is plated to a thickness of about 2 to 3 μm. . By designing the cap 8b so that the outer diameter of the Kovar metal frame 11b and the inner diameter of the seal frame 7b fit together, positioning can be easily performed and seam weld sealing can be performed efficiently. Generally, the dimensions of this type of package are ceramic width 15.24 mm, mount diameter 8 mm,
Since the seal frame has an inner diameter of 10 mm and an outer diameter of 12.7 mm, the diameter of the glass sealing portion can be approximately 7 mm x 7 mm.
第２の実施例として第５図を示し説明する。パ
ツケージ本体は第１実施例、第５図と同じあるの
で省略し、キヤツプ周辺のみについて説明する。
キヤツプ８Ｃの製造方法も全く第１の実施例の第
４図と同じであるが、若干寸法の違いだけであり
シームウエルドするときの位置決め方法が成形キ
ヤツプ９ｃの絞り部１５ｃを使用してシームウエ
ルドするだけの違いである。 A second embodiment will be described with reference to FIG. 5. The package body is the same as in the first embodiment and FIG. 5, so it will be omitted and only the surroundings of the cap will be explained.
The manufacturing method for the cap 8C is exactly the same as that shown in FIG. 4 of the first embodiment, but the only difference is the dimensions, and the positioning method when seam welding is performed by seam welding using the constricted part 15c of the molded cap 9c. The only difference is that
第６図は第３実施例の断面図である。本実施例
もパツケージ本体は第５図と同じであるので省略
し、キヤツプ８ｄ周辺のみについて説明する。成
形キヤツプ９ｄは位置決め用の絞り部１５ｄと応
力吸収の為の絞り部１６ｄを設けたもので成形キ
ヤツプ９ｄとコバール金属枠１１ｄの接合、硝子
封着メツキ方法は前述と全く同じである。このキ
ヤツプ８ｄの絞り部１５ｄをシールフレーム７ｄ
の内径に位置合せして通常のシームウエルド封止
をすると本発明の半導体装置が完成する。 FIG. 6 is a sectional view of the third embodiment. Since the package body of this embodiment is the same as that shown in FIG. 5, the description thereof will be omitted, and only the vicinity of the cap 8d will be described. The molded cap 9d is provided with a constricted portion 15d for positioning and a constricted portion 16d for stress absorption, and the method of joining the molded cap 9d and the Kovar metal frame 11d and plating the glass for sealing is exactly the same as described above. The constricted portion 15d of this cap 8d is sealed to the frame 7d.
The semiconductor device of the present invention is completed by aligning it with the inner diameter and performing normal seam weld sealing.
以上の様に本発明の構造は硝子封着部のコバー
ル金属枠を従来よりも数倍ないし10倍厚くするこ
とができるので、熱的、機械的応力を成形キヤツ
プが吸収しコバール金属枠には塑成変形を発生さ
せないために充分な気密性が確保できる。もちろ
んコバール金属枠はリング状でも、もちろん可能
である。以上のようにシームウエルド封止方法で
ある為製造歩留りが良く、原価が安く、高信頼性
である紫外線消去型EPROM半導体装置を提供す
るものである。 As described above, in the structure of the present invention, the Kovar metal frame of the glass sealing part can be made several times to ten times thicker than the conventional one, so the molded cap absorbs thermal and mechanical stress, and the Kovar metal frame Sufficient airtightness can be ensured to prevent plastic deformation. Of course, the Kovar metal frame can also be made into a ring shape. As described above, since the seam weld sealing method is used, the manufacturing yield is high, the cost is low, and an ultraviolet erasable EPROM semiconductor device with high reliability is provided.
第１図および第２図はそれぞれ従来の半導体装
置を示す平面図および断面図である。第３図は本
発明の実施例を示す平面図であり、第４図、第５
図および第６図はそれぞれ第３図のＡ−A′部に
おける第１、第２および第３の実施例を示す断面
図である。
尚、図において、１ａ，１ｂ，１ｃ，１ｄ……
セラミツク基板、２ａ，２ｂ，２ｃ，２ｄ……半
導体素子、３ａ，３ｂ，３ｃ，３ｄ……半導体素
子固着部、４ａ，４ｂ，４ｃ，４ｄ……ボンデイ
ングパツド部、５ａ，５ｂ，５ｃ，５ｄ……外部
リード、６ａ，６ｂ，６ｃ，６ｄ……Au又はAl
線、７ａ，７ｂ，７ｃ，７ｄ……シールフレー
ム、８ａ，８ｂ，８ｃ，８ｄ……キヤツプ、９
ａ，９ｂ，９ｃ，９ｄ……成形キヤツプ、１０
ｂ，１０ｃ，１０ｄ……紫外線透過硝子、１１
ｂ，１１ｃ，１１ｄ……コバール金属枠、１２
ｂ，１２ｃ，１２ｄ……内径部、１３ｂ，１３
ｃ，１３ｄ……内壁面、１４ｂ，１４ｃ，１４ｄ
……ろう材、１５ｃ，１５ｄ……位置決め絞り
部、１６ｄ……応力吸収用絞り部である。
FIG. 1 and FIG. 2 are a plan view and a cross-sectional view, respectively, showing a conventional semiconductor device. FIG. 3 is a plan view showing an embodiment of the present invention, and FIG.
This figure and FIG. 6 are sectional views showing the first, second and third embodiments, respectively, taken along the line A-A' in FIG. In addition, in the figure, 1a, 1b, 1c, 1d...
Ceramic substrate, 2a, 2b, 2c, 2d...Semiconductor element, 3a, 3b, 3c, 3d...Semiconductor element fixing part, 4a, 4b, 4c, 4d...Bonding pad part, 5a, 5b, 5c, 5d ...External lead, 6a, 6b, 6c, 6d...Au or Al
Line, 7a, 7b, 7c, 7d... Seal frame, 8a, 8b, 8c, 8d... Cap, 9
a, 9b, 9c, 9d...molded cap, 10
b, 10c, 10d...UV-transparent glass, 11
b, 11c, 11d... Kovar metal frame, 12
b, 12c, 12d...Inner diameter part, 13b, 13
c, 13d...Inner wall surface, 14b, 14c, 14d
. . . brazing filler metal, 15c, 15d: positioning constriction portion, 16d: stress absorbing constriction portion.
Claims (1)
着した窓枠状金属キヤツプをシームウエルド封止
する半導体装置において、絞り加工された曲げ部
と中央部に角穴を設けた薄いコバール金属キヤツ
プに対して厚さの厚い窓枠状金属を前記キヤツプ
の曲げ部中央にはめ合されて一体化し、かつ前記
窓枠状金属の内壁面に紫外線透過硝子を封着した
窓枠状キヤツプをシームウエルド封止したことを
特徴とする半導体装置。1 In a semiconductor device that seam-weld-seals a window frame-shaped metal cap sealed with glass to a seal frame on a ceramic substrate, the thickness of the thin Kovar metal cap is A window frame-shaped cap is seam-welded, in which a thick window frame-shaped metal is fitted into the center of the bent part of the cap and integrated, and ultraviolet-transparent glass is sealed to the inner wall surface of the window frame-shaped metal. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7437479A JPS55166939A (en) | 1979-06-13 | 1979-06-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7437479A JPS55166939A (en) | 1979-06-13 | 1979-06-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55166939A JPS55166939A (en) | 1980-12-26 |
| JPS6222455B2 true JPS6222455B2 (en) | 1987-05-18 |
Family
ID=13545323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7437479A Granted JPS55166939A (en) | 1979-06-13 | 1979-06-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55166939A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6894853B2 (en) | 2002-05-10 | 2005-05-17 | Texas Instruments Incorporated | Stress relieved frame |
| JP2006145610A (en) * | 2004-11-16 | 2006-06-08 | Shinko Electric Ind Co Ltd | Package for housing optical component |
-
1979
- 1979-06-13 JP JP7437479A patent/JPS55166939A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55166939A (en) | 1980-12-26 |
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| JP2543661Y2 (en) | Microwave transistor |