JPS6112048A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6112048A JPS6112048A JP13235684A JP13235684A JPS6112048A JP S6112048 A JPS6112048 A JP S6112048A JP 13235684 A JP13235684 A JP 13235684A JP 13235684 A JP13235684 A JP 13235684A JP S6112048 A JPS6112048 A JP S6112048A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- semiconductor device
- glass
- chip
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000005388 borosilicate glass Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 229910000833 kovar Inorganic materials 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 239000011521 glass Substances 0.000 abstract description 20
- 238000007789 sealing Methods 0.000 abstract description 15
- 239000000463 material Substances 0.000 abstract description 4
- 238000005219 brazing Methods 0.000 abstract description 3
- 229910015365 Au—Si Inorganic materials 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 241000981595 Zoysia japonica Species 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 238000002834 transmittance Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910017398 Au—Ni Inorganic materials 0.000 description 1
- 239000004859 Copal Substances 0.000 description 1
- 241000782205 Guibourtia conjugata Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
（１） 発明の属する技術分野
本発明は半導体装置にかかり、とくにＣＯＤあるいは柴
外線消去型ＥＰＲＯＭに使用される半導体装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a semiconductor device, and particularly to a semiconductor device used in a COD or a line erasable EPROM.
（２） 従来技術の説明
従来、ＣＣＤあるいは柴外線消去型班πＮの分野に使用
される一般的な半導体装置用容器（以下パッケージと呼
ぶ）としては、セラミック基板に半導体素子（以下チッ
プと呼ぶ）ｔｌ−固着するチップ固着部とチップ電極を
外部に取り出す為の導体管メタライズパターンにより形
成し、セラミック基板側面に金属リードを四つ付けした
ものである。(2) Description of the prior art Conventionally, a general semiconductor device container (hereinafter referred to as a package) used in the field of CCD or cylindrical line erasure type πN has a semiconductor element (hereinafter referred to as a chip) mounted on a ceramic substrate. It is formed by a chip fixing part to be fixed and a conductor tube metallized pattern for taking out the chip electrode to the outside, and four metal leads are attached to the side surface of the ceramic substrate.
この構造のパッケージのチップ固着部に共晶合金により
チッ１を固着した後、金属細線でチップ電極とメタライ
ズパターンと全結線し、キャップ封止してハーメチック
シールとする０こｑハーメチック封止するキャップ構造
は、セラミック基板の中央に円形の窓を設けこの窓に合
わせた柴外線透。After fixing the chip 1 to the chip fixing part of the package with this structure using a eutectic alloy, all the wires are connected to the chip electrodes and the metallized pattern using thin metal wires, and the cap is sealed to form a hermetic seal. The structure consists of a circular window in the center of the ceramic substrate, and a Shiba Gai line transparent that matches this window.
過硝子會うめ込み一着し、このセラミック基板外周部と
パッケージとの間を低融点硝子にて封止するものであり
この方法は一般に７リツトシールと呼ばれている方法で
るる０又、従来の別の実施例について第１図、第２図金
柑いて説明する。セラミック基板１にチップ２を搭載す
るチップ固着部３とチップ電極（図示せず）を外部に取
り出す為の導体ｔ−メタライズパターンにより施しボン
ディングパッド４とする。前記メタライズパターンは。This method is generally called 7-lit sealing, and is used to seal the gap between the outer periphery of the ceramic substrate and the package using a low-melting point glass. Another embodiment will be explained with reference to FIGS. 1 and 2. A bonding pad 4 is formed by a conductor T-metalized pattern for taking out a chip fixing part 3 for mounting a chip 2 on a ceramic substrate 1 and a chip electrode (not shown) to the outside. The metallization pattern is.
セラミックの中間層全通って基板外側に導出させ外部リ
ード５をろう付けしたものである。このパッケージのチ
ップ固着部３にチップ全固着した後にＭ線又はＡｕＭ線
でチップ電極とボンティングパッド４と結線する。次に
ボンディングバット周辺にろう付けされたシールフレー
ム７上には窓枠上のキャップ８がシームウェルド封止さ
れている。External leads 5 are brazed to the entire ceramic intermediate layer and led out to the outside of the substrate. After the entire chip is fixed to the chip fixing portion 3 of this package, the chip electrodes and the bonding pads 4 are connected with M wires or AuM wires. Next, a cap 8 on the window frame is seam welded onto the seal frame 7 which is brazed around the bonding butt.
この窓枠状キャップは、コバール材を第１図、第２図の
如き形状に絞り加工した後に柴外線透過硝子商品名コー
ニングコード”９７４１（熱膨張係数３９ＸＩＯ）９’
ｉキヤツプ８に封着しＮｉメッキ全３〜４μ程度の厚さ
にメッキしたものである。然しなからこのパッケージ構
造は次の欠点がある０まず。This window frame-shaped cap is made by drawing Kovar material into the shape shown in Figs.
It is sealed to the i-cap 8 and plated with Ni to a total thickness of about 3 to 4 μm. However, this package structure has the following drawbacks.
前者のフリットシール方法は、封着作業において最適温
度（４５０℃で１０〜１５分加熱）で封着した場合にチ
ップの拡散プロセス上危険な温度に近い為に電気的特性
が封着前と比較すると変動し選別歩留フも悪かった。こ
れ全改良する為に封着の最適温度を若干下げて作業する
と上述した電気的特性変動がなくなり選別歩留りも向上
するが、封着作業において硝子のセラミックへの濡れ性
が悪くリーク試験歩留りが低下すると共に機械的衝撃に
弱くなることもわかっている。又、後者のシームウェル
ド方法は封着時に高温にさらされることもなく電気的特
性変動もない信頼性の高いパッケージング方法であるこ
とは周知の事実である。しかし。In the former frit sealing method, when sealing is performed at the optimal temperature (heating at 450°C for 10 to 15 minutes), the electrical characteristics are close to the temperature that is dangerous for the chip diffusion process, so the electrical characteristics are lower than before sealing. This caused fluctuations and the sorting yield was poor. In order to completely improve this, if the optimum temperature for sealing is lowered slightly, the above-mentioned electrical property fluctuations will disappear and the sorting yield will improve, but the wettability of the glass to the ceramic during the sealing work will be poor and the leak test yield will decrease. It is also known that it becomes more susceptible to mechanical shock. Furthermore, it is a well-known fact that the latter seam welding method is a highly reliable packaging method that is not exposed to high temperatures during sealing and does not cause changes in electrical characteristics. but.
柴外線透過型パッケージの場合は、キャップ部からのリ
ーク、硝子の柴外線の透過率の悪さからＥＦＲＯＭの消
去時間が掛かりすぎる。窓部が円形でらる几めに大型チ
ップの搭載に制約あるいに、チップコーナ一部の光量不
足等の問題がありかならずしも満足できる状態ではなか
つ友。In the case of a transmissive type package, it takes too much time to erase the EFROM due to leakage from the cap and poor transmissivity of the glass. Due to the circular shape of the window, it is difficult to mount a large chip, and there are problems such as insufficient light in some corners of the chip, so the condition is not always satisfactory.
〔３ン 発明の目的
、本発明は、上述した欠点を除去し高信頼性、高歩留、
低価格の半導体装置たとえばＥＰＲＯＭあるいはＣＣＤ
用半導体装ｆｉｉｔ−提供するものである。[3] Purpose of the invention The present invention eliminates the above-mentioned drawbacks and achieves high reliability, high yield,
Low-cost semiconductor devices such as EPROM or CCD
Semiconductor equipment fiit-provided.
（４） 発明の構成
本発ｆＩＡはシームウェルド封止構造金有し、コバー
−ルキャップに深い２′Ｒ絞りを設は柴外線透過硝子と
しては熱膨張係数５〜Ｂ ｘ ｘｏ７ｃでかつ＃９７４
１よりも柴外線透過率の良好なコーニングコード＃７９
００． ”７９１０． ＃７９１１． ＃７９１０．
＃７９１２等の９６％硅酸硝子、 ＃７９１３のバイ
コール硝子、 ＃７９４０の石英硝子等を用いコバール
の熱膨張係数４７ Ｘ １０．６を緩和するために２０
〜３０Ｘ１０−７／℃の硼硅酸硝子全コバールキャップ
と前述の硝子の間に介在させて封着すると共に窓形状を
角型形状九したことケ特徴とする。通常このコバールキ
ャップにはａｎ又は無電解Ｎｉメッキを施すことが好ま
しい。(4) Structure of the invention The fIA of the present invention has a seam-weld sealing structure and a cover plate.
- A deep 2'R aperture is installed on the cap, and the thermal expansion coefficient is 5~B x xo7c and #974 for external radiation transmitting glass.
Corning code #79 with better Shiba external ray transmittance than 1
00. "7910. #7911. #7910.
96% silicate glass such as #7912, Vycor glass #7913, quartz glass #7940, etc. are used to reduce the coefficient of thermal expansion of Kovar, which is 47 x 10.6.
It is characterized by interposing and sealing between the borosilicate glass full Kovar cap of ˜30×10 −7 /° C. and the above-mentioned glass, and having a rectangular window shape. Usually, it is preferable to apply AN or electroless Ni plating to this Kovar cap.
（５） 原理と作用
従来の柴外線透過硝子”９７４１．よりも透過率が格段
に良い石英板を用いかつ開口部の形状上角型にして消去
時間の短ＡＩヲ計る０又、石英を用いる事によって起る
コバールとの熱膨張による応力緩和即ち応力吸収の為に
コパールキャップ封着構造１２段絞りとしコバールと石
英硝子との間に熱膨張係数が両者の中間である２０〜３
０ Ｘ １０”−’の硼硅酸硝ｔ−ｈさんで封着°した
構造である。(5) Principle and function A quartz plate is used, which has a much better transmittance than the conventional 9741. In order to relieve stress, that is, absorb stress due to thermal expansion between Kovar and quartz glass, a 12-stage diaphragm is used for the copal cap sealing structure, and the coefficient of thermal expansion is between 20 and 3 between Kovar and quartz glass.
It has a structure sealed with 0 x 10''-' borosilicate th.
（６） 実施例
本発明２実施例により説明する。第３図は本発明の半導
体装置の平面図、第４図はその封着部分の部分拡大断面
図でらる。セラミック基板１′にチップ２′ヲ固着する
チップ固着部３′とチップ電極（図示せず）ｔ−外部リ
ードに取り出すための導体をメタライズパターンにより
施しボンティングパッド４′とする。前記メタライズパ
ターンは、セラミック中間層を通りで基板外壁に専用さ
せ外部リード５′會ろう付けしたものである。この構造
の半導体装置のチップ固着部３′に人ｕ −８ｉのろう
材９′全介在させてチップを固着した後にＭ線又はＡｕ
Ｍ線／でチップ電極とボンディングパッド４′とを結線
する。次に気密封止するキャップ８′は、コバールから
成る金属板に２段の深絞り１０’ ｉ設は中央に正方形
の窓を打ち抜く。次に前述した柴外線透過硝子コーニン
クコードＡ７９００．７９１０．７９１１．７９１２
ノ９６チ硅酸硝子、”７９１３のバイコール硝子、 ”
７９４０の石英硝子の丸棒を前記キャップ８′の正方形
の窓の内壁面１１′に合うように４辺を削り落し、その
硝子棒の表面に熱膨張係数２０〜２５×１０−７／℃の
溶融した硼硅酸硝子１２′を浸漬法にエフグレーズし硝
子棒に９すい硝子被膜を付着させる。このグレーズされ
た石英硝子棒ヲ０．５〜１．ＯＨの厚さに輪切りにして
前記金属キャップ８′の窓部内壁面１１′に挿入して酸
化雰囲気炉で１０００℃位の温度で封着する。このキャ
ップの金属部には、Ｓｎ又は無電％Ｎｉメッキを数μｍ
メッキする。この様にしてつくられたキャップを前記パ
ッケージのシールフレーム７′に位置合せしてシームウ
ェルドにより封止すると本発明の半導体装置ができあが
る０（７）発明の効果
以上の様に本発明の構造のキャップ全パッケージに封止
した構造にすると、シームウェルド溶接は、キャップの
８ｎ又はＮ１−ＰがＡｕと合金化する場合Ａｕ−Ｎｉよ
りも低い温度で合金化できるので硝子封着に掛かる熱応
力が小さく更に硝子封着部は。(6) Example The present invention will be explained using a second example. FIG. 3 is a plan view of the semiconductor device of the present invention, and FIG. 4 is a partially enlarged sectional view of the sealed portion thereof. A chip fixing portion 3' for fixing the chip 2' to the ceramic substrate 1' and a conductor for taking out a chip electrode (not shown) to an external lead are formed by a metallized pattern to form a bonding pad 4'. The metallized pattern is formed by passing through the ceramic intermediate layer and soldering the external leads 5' to the outer wall of the substrate. After the chip is fixed in the chip fixing part 3' of the semiconductor device with this structure by completely interposing the brazing material 9' of U-8i, M wire or Au is used.
The chip electrode and the bonding pad 4' are connected with the M wire/. Next, the cap 8' to be hermetically sealed is made by punching a square window in the center of a metal plate made of Kovar in two stages of deep drawing 10'. Next, the aforementioned Shiba external light transmission glass Konink code A7900.7910.7911.7912
No. 96 Tisilicate glass, "7913 Vycor glass,"
A 7940 quartz glass round rod was ground down on four sides to match the inner wall surface 11' of the square window of the cap 8', and the surface of the glass rod was coated with a thermal expansion coefficient of 20 to 25 x 10-7/°C. The molten borosilicate glass 12' is F-glazed by the dipping method to adhere a 9-glass coating to the glass rod. This glazed quartz glass rod is 0.5~1. It is cut into rings with a thickness of OH, inserted into the window inner wall surface 11' of the metal cap 8', and sealed at a temperature of about 1000° C. in an oxidizing atmosphere furnace. The metal part of this cap is plated with Sn or electroless Ni to a thickness of several μm.
Plate. By aligning the cap made in this way with the seal frame 7' of the package and sealing it by seam welding, the semiconductor device of the present invention is completed. If the cap is sealed in the entire package, seam welding can reduce the thermal stress applied to the glass sealing because when the 8n or N1-P of the cap is alloyed with Au, it can be alloyed at a lower temperature than Au-Ni. The glass sealing part is even smaller.
両材料の中間の熱膨張係数の硝子全はさみ、又、石英硝
子の直径方向の伸縮に対してはキャップ封着の２段絞り
加工部によって応力吸収をさせて金属と硝子との破壊を
防止している。The glass full scissors have a coefficient of thermal expansion between those of the two materials, and the two-step drawn part of the cap seal absorbs stress against the expansion and contraction of quartz glass in the diametrical direction, preventing breakage between metal and glass. ing.
更に石英硝子全使用しているので機械的にも強く、柴外
線の透過率も改善されると同時に、窓形状を角形にした
ためチップコーナーにも充分柴外線が当り大型チップの
搭載も可能となり、又、消去時間の短縮にも寄与し本パ
ッケージ？使用したＢＦＲＯＭの使い易さの改善にもつ
ながるものである。Furthermore, since it is made entirely of quartz glass, it is mechanically strong and improves the transmittance of the Shiba-gai line.At the same time, since the window shape is rectangular, the Shiba-gai line hits the chip corners sufficiently, making it possible to mount large chips. This package also contributes to reducing erasing time. This also leads to improvement in the usability of the BFROM used.
この様な点から本発明の半導体装置は、従来から大量に
使用されているセラミックパッケージに安価な上述した
キャップをシームウェルド封止して製造歩留り良く、製
造原価が安価で、高信頼性である柴外線消去型ＥＦＲＯ
Ｍの半導体装置を提供するものである。From these points of view, the semiconductor device of the present invention has a high manufacturing yield, low manufacturing cost, and high reliability by seam-welding the inexpensive cap described above in a ceramic package that has been conventionally used in large quantities. Shiba line erasure type EFRO
The present invention provides a semiconductor device of M.
第１図は、従来の半導体装置の平面図、第２図は第１図
のＡ−に部分断面図、第３図は、本発明の実施例の半導
体装置の平面図、第４図は第３図のＡ−に部分の一部全
拡大して示した断面図である０
１．１′・・・セラミック基板、２．２′・・・半導体
素子（チップ）、３．３′・・・チップ固着部、４．４
′・・・ボンディングパッド、５．５′・・・外部リー
ド、６，６′・・・Ａ４又ｔ！Ａｕ線、７．７’・・・
シールフレーム、８゜８′・・・キャップ、９′・・・
ろう材、１０′・・・深絞り溝、１１′・・・内壁面、
１２′・・・硼硅酸硝子、１３′・・・石英硝子。
第１図
第２図1 is a plan view of a conventional semiconductor device, FIG. 2 is a partial sectional view taken along line A- in FIG. 1, FIG. 3 is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. This is a cross-sectional view showing a part of the part A- in Figure 3 fully enlarged.・Chip fixation part, 4.4
'...Bonding pad, 5.5'...External lead, 6,6'...A4 or t! Au wire, 7.7'...
Seal frame, 8°8'... Cap, 9'...
Brazing metal, 10'...deep drawing groove, 11'...inner wall surface,
12'...borosilicate glass, 13'... quartz glass. Figure 1 Figure 2
Claims (1)
部とを囲んで前記絶縁基板上に固着された金属シールフ
レームを設けた半導体容器に金属キャップをシームウェ
ルド封止した半導体装置において、前記金属キャップは
コバール板の中央に角形状の２段深絞り加工を施した開
口部に熱膨脹係数２０〜３０×１０＾−＾７／℃の硼硅
酸硝子を接着剤として石英硝子を封着した構造を有し、
かつ該コバール板を前記半導体容器にシームウェルド封
止したことを特徴とする半導体装置。In a semiconductor device in which a metal cap is seam-welded sealed to a semiconductor container provided with a metal seal frame fixed on the insulating substrate surrounding a semiconductor element fixing portion and a bonding pad portion on the insulating substrate, the metal cap is made of Kovar. It has a structure in which quartz glass is sealed using borosilicate glass with a coefficient of thermal expansion of 20 to 30 x 10^-^7/°C as an adhesive to the square-shaped two-stage deep-drawn opening in the center of the plate. ,
A semiconductor device characterized in that the Kovar plate is seam-welded sealed in the semiconductor container.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13235684A JPS6112048A (en) | 1984-06-27 | 1984-06-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13235684A JPS6112048A (en) | 1984-06-27 | 1984-06-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6112048A true JPS6112048A (en) | 1986-01-20 |
Family
ID=15079445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13235684A Pending JPS6112048A (en) | 1984-06-27 | 1984-06-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6112048A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7402458B2 (en) * | 2002-05-10 | 2008-07-22 | Texas Instruments Incorporated | Stress relieved flat frame for DMD window |
| JP2009212483A (en) * | 2008-02-29 | 2009-09-17 | Samsung Mobile Display Co Ltd | Flexible substrate, manufacturing method therefor, and thin film transistor using the same |
-
1984
- 1984-06-27 JP JP13235684A patent/JPS6112048A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7402458B2 (en) * | 2002-05-10 | 2008-07-22 | Texas Instruments Incorporated | Stress relieved flat frame for DMD window |
| JP2009212483A (en) * | 2008-02-29 | 2009-09-17 | Samsung Mobile Display Co Ltd | Flexible substrate, manufacturing method therefor, and thin film transistor using the same |
| US8221889B2 (en) | 2008-02-29 | 2012-07-17 | Samsung Mobile Display Co., Ltd. | Flexible substrate, method of fabricating the same, and thin film transistor using the same |
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