JPS60109253A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPS60109253A JPS60109253A JP58216174A JP21617483A JPS60109253A JP S60109253 A JPS60109253 A JP S60109253A JP 58216174 A JP58216174 A JP 58216174A JP 21617483 A JP21617483 A JP 21617483A JP S60109253 A JPS60109253 A JP S60109253A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- solder
- layer
- sealing
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】 〔技術分野］ 本発明は電子装置のパッケージ技術に関する。[Detailed description of the invention] 〔Technical field] The present invention relates to packaging technology for electronic devices.
半導体装置のパッケージ（封止）構造としては、たとえ
ば、１９６８年１１月２５日付゛発行、集積回路ハンド
ブック、２８７〜２９２頁にも記載されているように、
Ｔｏ−５，フラットパック、インライン等があり、その
封止方法には電流による抵抗溶接、低融点合金による鑞
付け、低融点ガラスによる封着および樹脂モールドが知
らｈている。As for the package (sealing) structure of a semiconductor device, for example, as described in "Integrated Circuit Handbook," published on November 25, 1968, pages 287-292,
There are To-5, flat pack, in-line, etc., and known sealing methods include resistance welding using an electric current, brazing with a low melting point alloy, sealing with a low melting point glass, and resin molding.
ところで、前記樹脂モールド品に耐湿性が低く信頼度が
低い。こｉに対してＴｏ−５のようなキャン封止（抵抗
溶接）暮あるいは低融点合金、低融点ガラスによるセラ
ミック六ツケージ品、さらにはシームウェルド（抵抗溶
接）ＶＣよるセラミックパッケージ品は耐湿性が高く信
頼度が高い。By the way, the resin molded product has low moisture resistance and low reliability. On the other hand, ceramic six-cage products made of can-sealed (resistance welded) glass or low-melting point alloys or low-melting point glass, such as To-5, and ceramic packaged products made of seam-welded (resistance welded) VC are not moisture resistant. Highly reliable.
しかし、低融点合金、低融点ガラス、シームウェルドに
よるセラミックパッケージ品けつぎのような欠点がある
ことが本発明者によってあきらかとされた。However, it has been found by the inventor that there are drawbacks such as low melting point alloys, low melting point glasses, and seam-welded ceramic packages.
（１） 低融点合金、低融点ガラスによる封止は、Ａｕ
Ｓｎ、Ａｕ−Ｇｅ からなる低融点合金あるいは低融点
ガラスをあらかじめプリフォームしたものをベースとキ
ャップ間に精度よく重ね合せて封止しなければならない
ことから封止作業が面倒となり、工数の増大を招くばか
りでなく重ね合せずれによる封止不良も発生し易くなる
。(1) Sealing with low melting point alloy and low melting point glass is Au
A preformed low melting point alloy made of Sn, Au-Ge or low melting point glass must be precisely stacked and sealed between the base and the cap, which makes the sealing work troublesome and increases the number of man-hours. Not only this, but also sealing defects due to misalignment are likely to occur.
（２）低融点合金による封止品は高価なＡｕを含む低融
点合金を用いるため、生産コストが高くなる欠点がある
。(2) Since the sealed product using a low melting point alloy uses an expensive low melting point alloy containing Au, there is a drawback that the production cost is high.
（３）低融点ガラスによる封着は低融点ガラスとは言え
ども、軟化点け４００℃前後であることから、作業温度
はたとえば軟化点よりも５０℃高い４５０・℃となる。(3) Although low melting point glass is used for sealing, since its softening point is around 400° C., the working temperature is, for example, 450° C., which is 50° C. higher than the softening point.
この結果、高熱に晒された半導体装置は部分的に熱的損
傷を受け、特性劣化が生じることがある。たとえば、チ
ップのＡＪからなる配線部に接続されるＡｕ線はその接
合部周縁にパープルブレーグと呼ばれるところのＡ ｌ
Ｉ Ａ ｕ ＋ Ａ ＩＡｕ、 ＡＪ Ａｕ２ など
の金属間化合物が生じ易い。この金属間化合物はプラス
側に体積変化を生じ、Ａｕ線とＡｌ配椋部との間にクラ
ックを発生させる断線原因となるが、低融点ガラスによ
る封着時の高熱によって、前記パープルブレーグの発生
が促進されるおそｈがある、
（４） シームウェルドによってキャップとペースとを
封着する構造は、ペース上のメタライズ層にクラックが
入り易く、封着不良が生じ易い。すなわち、シームウェ
ルドは１対の回転電極をパンケージの周辺に沿って一周
させることによって行なわれ、溶接は部分的にかつ連続
して行なわれる。この結果、熱歪が生じ、クラックが発
生１．易くなる。As a result, a semiconductor device exposed to high heat may be partially thermally damaged and its characteristics may deteriorate. For example, an Au wire connected to a wiring section consisting of AJ of a chip has an Al wire called a purple brag on the periphery of the joint.
Intermetallic compounds such as I Au + A IAu and AJ Au2 are likely to occur. This intermetallic compound causes a volume change on the positive side and causes disconnection that causes cracks between the Au wire and the Al distribution part, but the high heat during sealing with low melting point glass causes the purple braid to (4) In a structure in which the cap and the paste are sealed by seam welding, cracks are likely to occur in the metallized layer on the paste, and poor sealing is likely to occur. That is, seam welding is performed by rotating a pair of rotating electrodes around the periphery of the pan cage, and welding is performed partially and continuously. As a result, thermal strain occurs and cracks occur.1. It becomes easier.
本発明の目的は気密性が高い高信頼度の半導体装置を提
供することにある。An object of the present invention is to provide a highly reliable semiconductor device with high airtightness.
本発明の他の目的は生産コストが軽減できる半導体装置
を提供するととＫｌ＞る。Another object of the present invention is to provide a semiconductor device whose production cost can be reduced.
本発明の前記ならびにそのほかの目“的と新双な特徴は
、本明細書の記述および添付図面からあきらかＫなるで
あろう。The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.
本＠において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this @ is as follows.
すなわち、セラミック・パッケージの如く本体と蓋体と
を有するパ１ツケージにおいて、前記蓋体にあらかじめ
半田又は半田を構成する各成分等を被着しておくことに
より、本体と蓋体とを封止するため、前記目的を達成す
ることが出来る。That is, in a package having a main body and a lid, such as a ceramic package, the main body and the lid are sealed by applying solder or each component of the solder to the lid in advance. Therefore, the above objective can be achieved.
第１図（ａｌ〜（ｅ）は本発明の一実施例によるセラミ
ックパッケージ型半導体装置の製造方法を示す断面図で
ある。FIGS. 1A to 1E are cross-sectional views showing a method of manufacturing a ceramic package type semiconductor device according to an embodiment of the present invention.
同図（ａ）Ｋはパッケージの本体となるペース１が示さ
れている。ペース１は常用の多層印刷法あるいは積層法
によって形成されている。ペース１は矩形板状のセラミ
ック板２、このセラミック板２上に重ね合せ形成さｈ＋
矩形枠状のセラミック枠板３を有している。前記セラミ
ック板２の中央上面およびセラミック枠板３の上面には
それぞれＭｏ。(a) K in the same figure shows the pace 1 which is the main body of the package. The paste 1 is formed by a conventional multilayer printing method or lamination method. The pace 1 is formed by overlapping a rectangular ceramic plate 2 on the ceramic plate 2.
It has a ceramic frame plate 3 in the shape of a rectangular frame. Mo is applied to the central upper surface of the ceramic plate 2 and the upper surface of the ceramic frame plate 3, respectively.
Ｍｕ、Ｗ等からなるメタライズ層４，５が形成されてい
る。セラミック板２上のメタライズ層４は半導体素子（
チップ）を固定する固定部分となることから矩形となっ
ている。また、セラミック枠板２上のメタライズ層４は
セラミ、ツク枠板３の内周縁から外周縁に延在する所望
ノ（ターンの帯群力菖らなっている。Metalized layers 4 and 5 made of Mu, W, etc. are formed. The metallized layer 4 on the ceramic plate 2 is a semiconductor element (
It is rectangular because it serves as the fixed part for fixing the chip. Further, the metallized layer 4 on the ceramic frame plate 2 is formed of a band of desired turns extending from the inner circumferential edge to the outer circumferential edge of the ceramic frame plate 3.
一方、前記セラミック枠板２上には細い枠状のセラミッ
クからなる封止枠６がセラミワク枠板２に同芯的に被着
形成されている。１＊、この封止枠６の上面にはＭｏ、
Ｍｕ、Ｗ等からなるメタライズ層７が形成されている。On the other hand, on the ceramic frame plate 2, a narrow frame-shaped sealing frame 6 made of ceramic is formed concentrically and adhered to the ceramic frame plate 2. 1*, Mo on the top surface of this sealing frame 6,
A metallized layer 7 made of Mu, W, etc. is formed.
また、各メタライズ層４．５．７は、その上面［Ｎ１等
からなるメッキ１ｉｉ８が設けられている。このメッキ
層８はＡｕ。Further, each metallized layer 4.5.7 is provided with a plating 1ii8 made of N1 or the like on its upper surface. This plating layer 8 is made of Au.
Ａｇ鍛等がメタライズ層に接合し難いこと、から、接合
性を高めるために設けられている。Since it is difficult for Ag forging etc. to bond to the metallized layer, it is provided to improve bondability.
他方、封止枠６の外側に露出するメタライズ層５上には
リード９の内端がそ４ぞれ電気的に固着されている。す
なわち、リード９はＦｅ−Ｎ１ 系あるいはＦｅ−Ｎｌ
−Ｃｏ系の合金からなっていて、メッキ層８を有するメ
タライズ層５にＡｇ鑞１０を介し、て固着されている。On the other hand, the inner ends of four leads 9 are electrically fixed on the metallized layer 5 exposed outside the sealing frame 6. That is, the lead 9 is Fe-N1 type or Fe-Nl
-Co alloy, and is fixed to the metallized layer 5 having the plating layer 8 via an Ag solder 10.
また、で−ス１はリード固着後にＡｕメッキ処理され、
露出するメタライズ層表面およびリード９０表面にＩｄ
Ａ ｕ層１１が設けられる。In addition, after fixing the leads, De-1 is plated with Au.
Id is applied to the exposed surface of the metallized layer and the surface of the lead 90.
An Au layer 11 is provided.
つぎに、同図（ｂ）に示すように、セラミック板２の中
央のメタライズ層４部分にチップ１２がＡｕ−８１０共
晶によって接合される。また、チップ１２の各電極とセ
ラミック枠板３上のメタライズ層５０内端部分とは、ｉ
からなるワイヤ１３で接続される。その後、このペース
ｌの封止枠６上には蓋体であるキャップ１４が重ね合わ
される。Next, as shown in FIG. 2B, the chip 12 is bonded to the central metallized layer 4 portion of the ceramic plate 2 using Au-810 eutectic. Moreover, each electrode of the chip 12 and the inner end portion of the metallized layer 50 on the ceramic frame plate 3 are i
It is connected by a wire 13 consisting of. Thereafter, a cap 14 serving as a lid is superimposed on the sealing frame 6 of this paste l.
キ４ ”／プ１４ｔｉＦｅ−Ｎｉ、Ｆｅ−Ｎ１−Ｃｏ系
の合金板からなり、特に限定はされないが、封止枠６と
重ならない中央部分はワイヤ１３との接触を嫌って上部
に窪むように形成されている。また、キャップ１４の表
面には下地層１５がＰｂ９表層１６がａｎからなる二層
メッキ層が形成されている。下地層１５および表層１６
の厚さ比は加熱し。It is made of a Fe-Ni, Fe-N1-Co alloy plate, and is not particularly limited, but the central portion that does not overlap with the sealing frame 6 is recessed in the upper part to avoid contact with the wire 13. In addition, a two-layer plating layer is formed on the surface of the cap 14, in which the base layer 15 is made of Pb and the surface layer 16 is made of an.
The thickness ratio is heated.
て両層が溶は合い、半田を構成した際、所望の半田組成
となるように適宜選択すればよい。また、Ｐ ｂ ｉｊ
Ｓ ｎに比較して酸化し易いため、下層としである。The solder composition may be appropriately selected so that both layers melt together and form a desired solder composition. Also, P b ij
Since Sn is more easily oxidized than Sn, it is used as the lower layer.
つぎに、キャップ１４を載せたベース１は２３０〜３８
０℃程度の温度下で封着処理される。封着温度は半田組
成によって１８３〜３２７℃の間で変化する溶融温度よ
りもたとえば５０’Ｃ程度高い温度となる。この結果、
キャップ１４ｉｉペース１の封止枠６に半田１７を介し
て接着さね、テンプ１２等は同図（ｃ）に示されるよう
に、気密的に封止される。Next, the base 1 on which the cap 14 is placed is 230 to 38
The sealing process is performed at a temperature of about 0°C. The sealing temperature is, for example, about 50'C higher than the melting temperature, which varies between 183 and 327C depending on the solder composition. As a result,
The cap 14ii is adhered to the sealing frame 6 of the pace 1 via the solder 17, and the balance wheel 12 and the like are hermetically sealed, as shown in FIG. 3(c).
（１）ベース１およびキャップ１４は気密性の 好な半
田１７で封止されるため、半導体装置の高耐湿性が維持
でき高信頼度変化が図れる。(1) Since the base 1 and the cap 14 are sealed with the solder 17 having good airtightness, the high moisture resistance of the semiconductor device can be maintained and high reliability changes can be achieved.
（２）ベース１およびキャップ１４は封止温度が２３０
〜３８０℃程度と、ガラス封着の４５０°Ｃ程度に比較
して低いことから、半導体装置は封止時にパープルプレ
ーグの発生等の熱的槓傷を受け難くなり、信頼度の向上
および歩留向上が図れる。(2) The base 1 and cap 14 have a sealing temperature of 230
~380°C, which is lower than the 450°C for glass sealing, makes semiconductor devices less susceptible to thermal damage such as purple plaque during sealing, improving reliability and yield. Improvements can be made.
（３）半田組成はキャップ表面に設ける下地層および表
層の厚さ制御ｒ（よって極１めて正確に形成さｔする。(3) The solder composition controls the thickness of the base layer and surface layer provided on the cap surface (thus, they can be formed extremely accurately).
この結果、二層メッキ層のりフローは確実に行なわれ、
正確な封止ができる。As a result, the two-layer plating layer glue flow is ensured,
Accurate sealing is possible.
（４）ベース１およびキャブ１４はＡｕに比較して充分
安価な牛田で封着されるため、封止コスト（パッケージ
コスト）は安価となる。(4) Since the base 1 and the cab 14 are sealed with Ushida, which is sufficiently cheaper than Au, the sealing cost (packaging cost) is low.
（５）ベース１およびキャップ１４は相互の重ね合わせ
、および加熱によって封着さ名、Ａｕ−８ｎ。(5) The base 1 and the cap 14 are sealed by overlapping each other and heating, Au-8n.
Ａｕ Ｇｅ からなる低融点合金あるいは低融点ガラス
のようなプリフォームをベースおよびキャップ間に位置
決め介在させる必要もなりところから、作業も簡単で工
数の低減が図れるばかりか、ベース１とキャ／ブ１４と
のす４る率も少なくなり、封止不良低減が図れる。Since it is not necessary to position and interpose a preform such as a low melting point alloy made of AuGe or low melting point glass between the base and the cap, the work is not only easy and reduces the number of man-hours, but also the base 1 and the cab 14. The rate of leakage is also reduced, and it is possible to reduce sealing defects.
（６）上記（１）〜（５）により、安価な半田によって
簡単かつ歩留よ〈封止できることから、半導体装置のコ
スト低減化という相乗効果が得られる。(6) According to (1) to (5) above, since sealing can be performed easily and with low yield using inexpensive solder, a synergistic effect of reducing the cost of the semiconductor device can be obtained.
以上本発明者によってなされた発明を実施例にもとすき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above using examples, the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
たとλ−ば、キャップにおける二層メッキは下地層が半
田で表層がＳｎであっても前記実施例同様な効果が得ら
れる。特に封着前の牛田の酸化が防げ、封着が確実に行
なわわる。また、ベースとキャップの封着はあらかじめ
キャップの表面に設けておいた一層の半田層で行なうよ
うにしても前記実施例と同様な効果が得られる。また、
牛田としてはセラミックに直接接着可能な半田が開発さ
れているが、このような半田を用いてベースとキャップ
の封着な行なっても前記実施例と同様な効果が得られる
。For example, in the two-layer plating on the cap, even if the base layer is solder and the surface layer is Sn, the same effect as in the above embodiment can be obtained. In particular, oxidation of Ushida before sealing can be prevented, and sealing can be performed reliably. Further, even if the base and the cap are sealed together using a single layer of solder previously provided on the surface of the cap, the same effect as in the above embodiment can be obtained. Also,
Ushida has developed a solder that can be directly bonded to ceramic, and even if the base and cap are sealed using such solder, the same effect as in the above embodiment can be obtained.
また、他の実施例としては、第２図で示すようにチップ
１２は高融点半田１８でＮｉメッキ層８を表面に設けた
メタライズ層４に固定し、キャップ１４はキャップ表面
にあらかじめ被着させておイタ低融点半田１９のリフロ
ーによちてベース１の封止枠６に固定するようにしても
、気密封止。In another embodiment, as shown in FIG. 2, the chip 12 is fixed to the metallized layer 4 having the Ni plating layer 8 on the surface with a high melting point solder 18, and the cap 14 is attached to the surface of the cap in advance. Even if it is fixed to the sealing frame 6 of the base 1 by reflowing the low melting point solder 19, airtight sealing can be achieved.
低コスト封止が達成できる。また、この実施例は、高価
なＡｕはワイヤ１３を１接続するメタライズ層５部分に
しか設けられていないことから、さらに低コスト化が可
能となる。Low-cost sealing can be achieved. Further, in this embodiment, since expensive Au is provided only in the portion of the metallized layer 5 that connects one wire 13, further cost reduction is possible.
第３図は本発明を光通信用発光装置に適用した断面圀で
ある。′この例では、本体である金属製のステム２０の
開口部分が蓋体である金属製のキャップ２１で被われ半
田２２によって固着さおでいる。すなわち、ステム２０
の上面にはリング状の突堤２３が設けられている。また
、この突堤２３に囲まハる窪み部分はさらに深く窪んで
いる。また、窪み底の中央には円形の突出した台座２４
が設けら４ていて、この台座２４上Ｋｕサブマウント２
５を介して半導体レーザ素子２６が固定されている。ま
た、ステム２０の側壁にはそれぞねファイバーガイド２
７．モニタファイバーガイド２８が貫通状態で気密的に
固定されている。ファイバーガイド２７はその中心に光
ファイバー２９を有している。光フアイバー２９０内端
は半導体レーザ素子２６の一方の出射面に対面し、出射
面から発光されるレーザ光を取り込むようになっている
。また、モニタファイバーガイド２８はその中心にモニ
タ用光ファイバー３０を有している。FIG. 3 is a cross-sectional view of the present invention applied to a light emitting device for optical communication. ' In this example, the opening portion of the metal stem 20 that is the main body is covered with a metal cap 21 that is the lid body and fixed with solder 22 . That is, stem 20
A ring-shaped jetty 23 is provided on the upper surface. Further, the hollow portion surrounded by the jetty 23 is even deeper. In addition, a circular protruding pedestal 24 is placed in the center of the bottom of the recess.
A Ku submount 2 is provided on the pedestal 24.
A semiconductor laser element 26 is fixed via 5. In addition, fiber guides 2 are provided on the side walls of the stem 20, respectively.
7. A monitor fiber guide 28 is hermetically fixed in a penetrating state. The fiber guide 27 has an optical fiber 29 in its center. The inner end of the optical fiber 290 faces one emission surface of the semiconductor laser element 26, and is designed to take in the laser light emitted from the emission surface. Further, the monitor fiber guide 28 has a monitor optical fiber 30 at its center.
モニタ用光ファイバー３０の内端は半導体レーザ素子２
６の他方の出射面に対面し、出射面から発光されるレー
ザ光を取り込むようになっている。The inner end of the monitoring optical fiber 30 is connected to the semiconductor laser element 2.
6, and is designed to take in the laser light emitted from the output surface.
また、キャップ２１はステム２０の突堤２３に半田２２
によって固着されている。半田２２はキャップ２１の表
面に直接被着させる方法によって形成してもよく、また
、第１図（ａｌ〜（ｃｌで示すようにｐｂとＳｎまたは
半田とＳｎの二層メッキ層のりフローによって形成して
もよい。なお、半田をＳｎ層で被う構造は酸化し難いＳ
ｎが半田層を被うことから、半田表面が酸化されず、良
好な封着ができる効果もある。In addition, the cap 21 is attached to the jetty 23 of the stem 20 with solder 22.
is fixed by. The solder 22 may be formed by directly applying it to the surface of the cap 21, or it may be formed by a two-layer plating layer of PB and Sn or solder and Sn as shown in FIGS. Note that the structure in which the solder is covered with an Sn layer is made of S, which is difficult to oxidize.
Since n covers the solder layer, the solder surface is not oxidized and good sealing can be achieved.
この実施例は前記実施例と同様に半田を用いて封着を行
なうことから、気密封止、低コスト化が達成できる。In this embodiment, since the sealing is performed using solder as in the previous embodiment, airtight sealing and cost reduction can be achieved.
以上の説明では主とし７て本発明者によってなされた発
明をその背景となった利用分野である半導体装置製造技
術に適用し５跣場合について説明したが、それに限定さ
れるものではなく、たとえば、他の電子部品の気密パッ
ケージにも適用できる。In the above explanation, the invention made by the present inventor was mainly applied to the semiconductor device manufacturing technology, which is the background field of application. It can also be applied to airtight packaging of other electronic components.
第１図（ａｔ〜（ｃｌは本発明の一実施例によるセラミ
ックパッケージ型半導体装置の製造方法を示す断面図、
第２図は他の実施例によるセラミックパッケージ型の半
導体装置の断面図、
第３図は他の実施例による光通信用発光装置を示す断面
図である。
１・・・ベース、２・・・セラミック板、３・・・セラ
ミック枠板、４．訃・・メタライズ層、６・・・封止枠
、７・・・メタライズ層、８・・・メッキ層、９・・・
リード、１０・・・Ａｇ鑞、１１・・・Ａｕ層、１２・
・・チップ、１３・・・ワイヤ、１４・・・キャップ、
１５・・・下地層、１６・・・表層、１７・・・半田、
１８・・・高融点半田、１９・・・低融点半田、２０・
・・ステム、２１・・・キャップ、２２・・・半田、２
３・・・突堤、２４・・・台座、２５・・・サブマウン
ト１．２６・・・半導体レーザ素子、２７・・・ファイ
バーガイド、２８・・・モニタファイバーガイド、２９
・・・光ファイバー、３ｏ・・・モニタ用光ファイバー
。
代理人 弁理士 高 橋 明 夫
〆゛ ゝ
第 １ 図
（４）
（Ｃ）
第 ２ 図
第 ３ 図FIG. 1 (at to (cl) is a sectional view showing a method of manufacturing a ceramic package type semiconductor device according to one embodiment of the present invention; FIG. 2 is a sectional view of a ceramic package type semiconductor device according to another embodiment; The figure is a sectional view showing a light emitting device for optical communication according to another embodiment. 1... Base, 2... Ceramic plate, 3... Ceramic frame plate, 4. End... Metallized layer, 6. ... Sealing frame, 7... Metallized layer, 8... Plating layer, 9...
Lead, 10...Ag solder, 11...Au layer, 12.
...Chip, 13...Wire, 14...Cap,
15... Base layer, 16... Surface layer, 17... Solder,
18...High melting point solder, 19...Low melting point solder, 20.
...Stem, 21...Cap, 22...Solder, 2
3... Jetty, 24... Pedestal, 25... Submount 1.26... Semiconductor laser element, 27... Fiber guide, 28... Monitor fiber guide, 29
...Optical fiber, 3o...Optical fiber for monitor. Agent Patent Attorney Akio Takahashi Figure 1 (4) (C) Figure 2 Figure 3
Claims (1)
であって、前記本体と蓋体とは半田によって気密的に接
着されていることを特徴とする電子装置。1. An electronic device having a package consisting of a main body and a lid, wherein the main body and the lid are hermetically bonded with solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58216174A JPS60109253A (en) | 1983-11-18 | 1983-11-18 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58216174A JPS60109253A (en) | 1983-11-18 | 1983-11-18 | Electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60109253A true JPS60109253A (en) | 1985-06-14 |
Family
ID=16684443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58216174A Pending JPS60109253A (en) | 1983-11-18 | 1983-11-18 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60109253A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63240051A (en) * | 1987-03-27 | 1988-10-05 | Nec Corp | Ceramic cap |
| JPH01143241A (en) * | 1987-11-30 | 1989-06-05 | Nec Corp | Manufacture of semiconductor device package |
-
1983
- 1983-11-18 JP JP58216174A patent/JPS60109253A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63240051A (en) * | 1987-03-27 | 1988-10-05 | Nec Corp | Ceramic cap |
| JPH01143241A (en) * | 1987-11-30 | 1989-06-05 | Nec Corp | Manufacture of semiconductor device package |
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