JPS63112896A - Memory initializing device - Google Patents

Abstract

PURPOSE:To obtain a memory initializing device being independent from a function of a processor, by constituting the titled device so that the processor can execute in parallel other processing, while the initialization processing is being executed. CONSTITUTION:First of all, to an initial data setting means 3, an initial data written to a memory 2 by its initialization is set. Thereafter, in a process that a designated address to the memory 2 is updated successively from an initial address determined in advance by a designated address updating means 4, a write command is executed successively from a write command means 5 by a prescribed timing relation to an updating timing of its address. As a result, in accordance with this write command, the initial data which has been set to the initial data setting means 3 is written successively in an updated address of the memory 2. The timing by which the write command is executed from the write command means 5 is set at every updating by the designated address updating means 4, and also, before the next updating of its updating is executed. In such a way, a memory initializing device being independent from a function of a processor can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a
The present invention relates to a writable memory initialization device.

[Prior Art] In equipment that performs various controls while reading data from and writing data to memory based on commands from the processor 4, when starting the equipment, etc. It is common to initialize memory.

This memory initialization is performed using predetermined initial data (generally "o") for the entire memory or a predetermined area.
Conventionally, this type of memory initialization device has been implemented as a processor function. That is, when starting up the device, the processor first initializes the memory and then executes the original processing according to a predetermined program.

[Problems to be Solved by the Invention] In the memory initialization device realized as a function of the processor described above, time is wasted while performing the initialization process.

This is because while the processor is executing initialization processing, the intended processing is in a hold state.

The above-mentioned tendency becomes particularly noticeable when the target is cashico memory, associative memory, etc., which need to be initialized frequently.

Therefore, an object of the present invention is to embody a memory initialization device that is independent of the functions of a processor.

"Means for Solving the Problems" As shown in FIG. The first technical step in solving the above problem in the device is memory 2.
an initial data setting means 3 for setting initial data to be entered into the page; a designated address updating means 4 for sequentially updating a designated address for the memory 2 from a predetermined initial address value in a predetermined order; and this designated address updating means. 4 and a write command means 5 which commands writing to the memory 2 in a predetermined relationship with the update timing.

[Operation] First, initial data to be written to the memory 2 is set in the initial data setting means 3 through the initialization.

Thereafter, in the process of sequentially updating the designated address for the memory 2 from a predetermined initial address by the designated address updating means 4, write commands are sequentially issued from the write command means 5 in a predetermined timing relationship with the update timing of the address. Ru.

Then, in accordance with this write command, the initial data set in the initial data setting means 3 is sequentially written to the updated addresses of the memory 2.

The timing at which a write command is issued from the write command means 5 is after each update in the specified address update means 4 and before the next update after the update.

Further, the initial address value in the specified address updating means 4 is determined in advance according to the range of initialization to be input into the memory 2.

[Example 1 Hereinafter, embodiments of the present invention will be described based on the drawings.

FIG. 2 is a block diagram showing an example of a memory initialization device according to the present invention. This is an example of a 4-bit processing system.

In the same figure, 10 is a C that performs the central function of the processor.
PU, 20 is the target memory, CPU10
is designed to perform comprehensive control of the entire system as well as access control of the memory 20. 12 is an initialization control circuit that controls initialization processing for the memory 20; 14 is an initial data setter in which 4-bit writing data to be written to the memory 20 is set; this initial data setter 14 includes, for example, 4-bit data 'o o o o' is set. 16 is an address counter that counts up sequentially from a predetermined initial address value, and this address counter 16 is activated by the CLR signal from the initialization control circuit 12. “' o o o o
", and the count-up operation is performed in synchronization with the rising edge of the CLOCK signal from the initialization control circuit 12.
8 is an AND circuit that detects a carry ("1111") of the address counter 16 which is sequentially counted up.

15 is a multiplexer (MPXI) that switches the data D to be supplied to the memory 20 to either the initial data DO from the initial data setter 14 or the output data Da from the CPU 10, and this multiplexer 15 is an initialization control circuit. When the SEL[CT double signal from 12 is at H level, the initial data setter 14 side is switched, and when the 5ELECT signal is at L level, it is switched to the CPU 10 side.

17 is also a multiplexer (HPX), and this multiplexer 17 opens the address A to be supplied to the memory 20, and the 5ELE from the initialization control circuit 12
When the CT signal is at H level, the count value As of the address counter 16 is switched so that the output address Aa from the CPU 10 is selected when the same SEL[CT multiplied signal is at L level.

As mentioned above, the initialization control circuit 12 has a function of outputting the C1-R(fi and CI-OCK signals) to the address counter 16, a function of outputting the 5ELECT signal to each multiplexer 15.17, and other functions. It also has a function of outputting a write command signal WRITE to the memory 20 in a predetermined timing relationship with the output timing of the CLOCK signal to the address counter 16.

The timing relationship between the clock signal and the write command signal WRITE is such that, for example, the write command signal WRITE rises at the fall of the CLOCK signal. In addition, the initialization control circuit 12 receives 5 from the CPU 10.
It is activated by the TART signal, and each of the above-mentioned functions becomes substantially effective, while when the output of the AND circuit 18 rises, the write command signal @wRrn is output, and then the functions are substantially stopped.

Next, the operation will be explained according to the timing chart shown in FIG.

For example, when the system is powered on, CPU
outputs a 5TART signal to the initialization control circuit 12. Then, the initialization control circuit 12 raises the CLR signal, which causes the address counter 16 to read 'ooo○
"(=O). At this time, the initial data setter 14 already contains the initial data "' o o o o "
is set.

Here, the initialization control circuit 12 sends the 5ELECT signal to 1''.
When the level is set, the settings are set in the initial data setter 14 by the switching operation of each multi-preference knob 15 and 17.
o o o o'' is supplied to the memory 2o as the data D, and the value As to the column 1 of the address counter 16 is supplied as the address A.

In this state, first, when the write command signal WRITE from the initialization control circuit 12 rises, the count value set in the address counter 16 in the memory 20 is
Initial data DO"0000" is written to the address (address 0) specified by "o o".

Next, when the CLOCK signal rises, the address counter 16 increments to '0001', and at the fall of the CLOCK signal, the write command signal WRI is activated.
When TE rises, the initial data DO"00o" is written to the address (address 1) specified by the counter i-value of the address counter 16 at that time.

Thereafter, the address counter 16 similarly increments each time the CLOCK signal rises, and in the process, when the write command signal WRITE rises at the fall of the C10CK signal, the value is set in the address counter 16 at that point. The above-mentioned initial data Do'"0000 II is sequentially written to the addresses corresponding to the count values. Then, when the count value of the address counter 16 reaches '1111', the output of the AND circuit 18 rises and After recognizing the initialization control circuit 12, it outputs the write command signal WRITE, and then stops outputting the signal to CLOC and lowers the S[1, ECT signal. As a result, the above count value in the memory 20 is set to 111.
The initialization process of the memory 20 ends when the initial data Do "0000" is written to the address (address 15) specified by "1".At this time, from address 0 to address 15 of the memory 20, Initial data DO゛0000 ++
is written and is in an initialized state.

Thereafter, each multiplexer 15, 17 is switched to the CPU 10 side, and the memory 20 is accessed based on the output data l)a from CP-9=Ulo and the output address Aa.

On the other hand, in the initialization process of the memory 20 described above, the CPU 10
is not involved, and during the initialization processing, the CPU 10 performs initialization processing of other systems or other processing that does not target the memory 20. Then, when the initialization control circuit 12 finishes the above processing, it raises an interrupt signal to the CPU 10, and as a result, the CPU 10 interrupts the memory 2.
Recognizes completion of initialization of 0.

In the above embodiment, since a 4-bit counter is used as the address counter 16, 0 to 15 of the memory 20
Although initialization is performed up to the address, if the capacity of the target memory is large, the above embodiment can be applied as is by increasing the number of bits of the address counter 16.

Further, the initial data Do related to initialization is arbitrarily set depending on the system.

In the above embodiment, the initial f-tater setting means, specified address updating means, and lower stage of the re-entering command according to the present invention are specifically implemented as hardware as the initial data setter 14, address counter 16, and initialization control circuit 16. However, it is also possible to implement some or all of the respective functions in software.

[Effects of the Invention] As described above, according to the present invention, it is possible to concretely realize a memory initialization device that is independent of the functions of a processor. As a result, in a system employing the memory initialization device, the processor can perform other processing in parallel while the initialization processing is being executed, and an efficient system can be realized. This effect is particularly great in systems that target cache co-memories, associative memories, etc. that need to be initialized frequently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a block diagram showing an example of a memory initialization device according to the present invention, and FIG. 3 is a block diagram showing an example of initialization processing in the device shown in FIG. This is a timing chart. -11= [Explanation of symbols] 1...Processor 2...Memory 3...Initial data setting means 4...Specified address updating means 5...Write command means 10...CPU 12... Initialization control circuit 14...Initial data setter 15.17...Multiplexer 16...Address counter 18...AND circuit 20...Memory patent applicant Fuji Xerox Co., Ltd.
Patent attorney Tomohiro Nakamura (2 others)

Claims (1)

[Claims] An initialization device for a memory readable and writable by access from a processor, comprising an initial data setting means for setting initial data to be written to the memory, and a specified address for the memory in a predetermined order from a predetermined initial address value. Therefore, designated address updating means for sequentially updating;
A memory initialization device characterized by comprising a write command means for instructing a memory to write in a predetermined relationship with the update timing of the designated address update means.