JPS63107241A - Error detection system - Google Patents

Abstract

PURPOSE:To shorten a detection time at the same error rate by performing error detection by using stuff indication bits. CONSTITUTION:Pattern generating circuits 102 and 103 generate patterns 112 and 113 corresponding to the presence and absence of stuff. When a pattern 111 detected by a stuff indication pattern detecting circuit 101 is correct, either of comparators 104 and 105 outputs dissidence information 114 or 116, so the output of the comparator which outputs the dissidence information is inhibited by a trailing-stage inhibiting circuit 106 or 107 and neither of pieces of dissidence information 118 and 119 is inputted to pulse generating circuit 108 and 109, so that error pulses 120 and 121 are not generated. When the detected pattern 111 is not correct, both comparators 104 and 105 judge dissidence and error pulses 120 and 121 are inputted to an OR circuit 110 without being inhibited by the inhibiting circuits 106 and 107, so that an error pulse 122 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error detection method in a digital transmission system.

(Prior art) Conventionally, this type of error detection method uses a unique pattern inserted in a high-order group frame to achieve frame synchronization.
(referred to as a frame alignment signal), the receiving side generates its own original frame alignment signal pattern and compares it with the detected pattern to detect errors.

(Problem to be Solved by the Invention) In the conventional error detection method described above, the only bits that are checked for errors are bits provided for frame alignment signals, so the number of bits that can be detected for errors within a unit time is limited. The disadvantage is that the detection time for detecting a given error rate is long.

[Means for solving problems]

The error detection method of the present invention is a digital transmission system that uses an asynchronous digital multiplex conversion value M that uses the stuffing and ink method as a terminal, and detects whether or not stuffing has been performed on the transmitting side inserted in a higher order group frame. meta-1y finding pattern detection means for detecting stuffing indication bits, which are a plurality of bits representing a unique pattern for informing the side, and reproducing the pattern; and original patterns each indicating the presence or absence of stuffing. a first and a second pattern generation means for generating a pattern, and a first for comparing the stuff indication pattern detected by the stuff indication pattern detection means and the pattern generated by the first and second pattern generation means, respectively; It has a second comparing means and a pulse generating means which generates a pulse only when information of pulse mismatch is received from both the first and second comparing means.

The error detection method of the present invention uses the stuff control bits as error checking bits, so if the number of bits is greater than the frame alignment signal bits, it will be faster than the conventional error detection method in a unit time at the same error rate. The number of bits in which errors can be detected increases. Furthermore, if used in conjunction with the conventional method, the number of error detectable bits will increase, and the detection time for the same error rate will be shortened.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the error detection method of the present invention.

A stuffing indication pattern detection circuit 101 detects a stuffing indication pattern 111, which is a unique pattern inserted into a higher-order group frame and used to inform the receiving side whether or not stuffing has been performed on the transmitting side. The pattern generation circuits 102 and 103 each have a pattern + when there is a staff and when there is no staff.
12. +13 is generated. The comparator 104 compares the stuff indication pattern 111 and the pattern 112, and outputs - number information 114 if the pattern is defeated, and mismatch information 115 if the pattern is not defeated. Comparator 105 compares stuff indication pattern 111 and pattern 1
13 are compared, and if the game loses, number information 116@ is output, and if there is no loss, mismatch information 117 is output. Prohibited circuit 1
06 outputs the mismatch information 118 only when the mismatch information 115 is output from the comparator 104 and the one-loss information 116 is not output from the comparator 105. Prohibited circuit 1
07 outputs the mismatch information 119 only when the mismatch information 117 is output from the comparator 105 and the match information 114 is not output from the comparator 104. The pulse generation circuits 108 and 109 have discrepancy information i18 and 11, respectively.
Error pulses 120° and 121° occur only when inputting 9%. OR circuit 110 outputs error pulse 120 or 1
21 is input and output as an error pulse 122.

If the pattern 111 detected by the stuff indication pattern detection circuit 101 is correct, the comparator 104.1
05 is supposed to output the one-loss information 114 or 116, the output of the one that outputs the mismatch information is prohibited by the next-stage prohibition circuit 106 or 107, and the pulse generation circuits 108 and 109 are informed that there is no mismatch. Information 118, +
19 is not input, and error pulses 120 and 121 do not occur. However, if the detected pattern 111 is incorrect (if an error occurs), the comparator 104° comparator 10
5 are determined to be a mismatch, and are not inhibited by the prohibition circuits 106 and 107, and the non-coincidence information 118. +19 is input, error pulse 120
．． 121 is input to the OR circuit 110, and an error pulse 122 is also generated at the output.

(Effects of the Invention) As explained above, the present invention detects errors using stuffing indication bits. When the error rate is the same (here, the effect is that many error detection pulses can be generated).

[Brief explanation of the drawing]

Figure 1 is a block diagram of an embodiment of the error detection method of the present invention. 101...Stuff indication pattern/r-on detection circuit, 102...Pattern generation circuit when there is stuff, 103...・Pattern generation circuit when there is no stuff, 104, 105... Comparator, 106, 107...
...Prohibition circuit, 108.109...Pulse generation circuit, 110...Logic circuit, 111...Detected stuff indication pattern, 112... ...Pattern when the staff is absent, 113...Pattern when there is no staff, 114, + 16...-number information, 115.117...・Undefeated information, 118...
...Failure information that passed through the prohibition circuit 106, 1
19......Failure that passed through the prohibition circuit 107
Loss information, 120, 121.122...Error pulse.

Claims (1)

[Claims] In a digital transmission system using an asynchronous digital multiplex converter using a stuffing method as a terminal, there is provided a system for informing a receiving side whether or not stuffing has been performed on the transmitting side inserted into a higher order group frame. stuffing pattern detection means for detecting stuffing indication bits, which are a plurality of bits representing a unique pattern, and reproducing the pattern; and first and second means for generating original patterns each indicating the presence or absence of stuffing. a pattern generation means, a stuff indication pattern detected by the stuff indication pattern detection means, and the first and second stuff indication patterns;
first and second comparison means that respectively compare the patterns generated by the pattern generation means; and a pulse generation means that generates a pulse only when pulse mismatch information is output from both the first and second comparison means. An error detection method with