JPS63106988A - Memory control system - Google Patents

Abstract

PURPOSE:To easily detect and check a parity data for a horizontal parity adding bit and to easily control the addition by using a spare loop just behind a desired data in a horizontal direction as the horizontal parity adding bit. CONSTITUTION:In a magnetic bubble memory unit consisting of (n+1)-number of bubble chips No.(0)-No.(n), a partial defective loop 13 exists in the minor loop of the bubble chips No.(0)-No.(n). The defective loop is corrected by using the spare loop, but, in this case, the horizontal parity adding bit for the bubble chip in which no defective loop 13 exists is arranged as shown in 6, and it is arranged as shown in 14 for the bubble chip in which the defective loop 13 exists. Thus, the horizontal parity adding bit is arranged on different spare chips for the bubble chip in which the defective loop exists, and the bubble chip in which no defective loop exists, therefore, it is easily possible to detect and check the parity data for the horizontal parity adding bit, and the control of addition is easily attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is constructed using a shift register-like memory element such as a magnetic bubble element or a charge-coupled element as a basic component.
This invention relates to a control method for detecting errors in memory that allows partial writing and partial reading.

[Conventional technology]

Figure 3 shows the conventional configuration of 1 + 1 bubble chip and 0.
This figure shows the configuration of a magnetic bubble memory unit consisting of ~Nl13, where 1 is a minor loop (first information loop) that stores and transfers information, and 2 is a major loop (second information loop) that transfers information to read and write information. (information loop), 5 is a detector for reading information,
4 is a puzzle erase generator for erasing and writing information, and 5 is a vertical parity addition bit added to 1+1 pieces of information from NIO to NI1. Reference numeral 6 denotes a horizontal parity additional bit written for error detection with respect to 1 block information (-=-3) bit of 1 bubble chip written to +- of ≠m from the preliminary minor lobe +(m-3). In FIG. 4, numerals 1 to 4.6 are the same as the components with the same reference numerals in FIG. As shown in Figures 3 and 4, the minor loop ≠0~-4PCm-0) is the one that was planned to be used from the beginning, and the loop ≠<m-3>~
≠ Thin is the preliminary loop, and Nl1O~mx (x≦
fi -2) chips are planned to be used from the beginning, m(x-M) to m(rc-1) are spare chips, N
An is a chip for performing vertical parity checking.

These horizontal parity addition robits 6 and the vertical harness addition bits 5 are +(7) of any bubble chip.
a-2) When a defect occurs in the minor loop or when a defect occurs in the Nan chip, 4p
(m-3), +(m-t).

Minor loop of valve m, or 1IKL (X+, 1) ~
A floor (n-1) chip is used instead.

FIG. 5 shows a magnetic puzzle memory control circuit composed of a plurality of magnetic puzzle memory units shown in FIG. 3, where 7 is the magnetic bubble memory unit shown in FIG. 9 is a horizontal parity check circuit that performs a parity check on a block-by-block basis; 9 is a horizontal harness generation circuit that generates parity bits for any block at the time of writing and reading; and 10 is a vertical parity circuit that performs a parity check on any one information unit during reading. A check circuit 11 is a vertical parity generation circuit that generates a parity bit of an arbitrary information unit during writing and reading, and 12 is a control circuit for controlling the parity check and defective loop information, timing control, etc. for reading and writing information to and from the magnetic bubble memory unit. This is a control circuit that performs control.

In FIG. 5, in the case of reading, a parity bit is generated by one or more horizontal and vertical parity generation circuits 9. One or more parity bits read from the unit 7 are compared in the horizontal and vertical parity checker circuit 8.10, and error detection is performed. control.

In the case of writing, parity bits are generated by one or more horizontal and vertical parity generation circuits 9.11 for the magnetic bubble memory unit 7 that has received an access request, and horizontal parity bit information and vertical parity bit information are added to the information to be written. 'jMF is loaded under the control of the control circuit 12 with parity bit information added.

Said parity check circuit 8.10 and generation circuit 9.
As 11, a general parity check/parity generation circuit having a configuration as illustrated in FIG. 6 is used. Fifth
In the figure, in the case of odd parity]) o t DB
are always fixed at %1, 2% 0, respectively, A to G are data bits, and H is a parity addition bit. In this circuit, when using it as a parity generation circuit,
If II is always set to %O〃, an additional bit will be generated in 0UTO ◎ Data structure of A-G shown in the figure, ie %1〃
If the bits in 01) are even, then 01) TO becomes

On the other hand, when using this circuit as a parity check circuit, input data A to H containing parity pins, monitor 0UTo, compare the result with the set parity information, and perform a parity check. Let's do it.

In the control circuit 12 shown in FIG. 5, setting of even/odd harness, setting of the amount of one block data, counting, etc. are carried out.

[Problem that the invention seeks to solve]

However, in the conventional horizontal parity check method, the horizontal parity addition bit 6 is provided at the end of the backup loop as shown in FIG. 41:(nL-
1) to ne (wind-3) and a defective loop 13 exists, the number of spare loops changes as shown by the shaded area in FIG.

Therefore, it is necessary to detect, check, and add parity data to the horizontal parity addition bit 6 in consideration of the backup loop, which causes the control to become complicated and busy.

It is an object of the present invention to eliminate the problems of the prior art described above, facilitate control over the detection check and addition of parity data to horizontal parity addition bits, and improve horizontal parity processing speed. The purpose is to provide a memory control method.

[Means for solving problems]

The above objective is achieved by using the spare loop immediately after the desired data in the horizontal direction as a horizontal parity additional bit.

[Effect]

The memory control method of the present invention facilitates control over detection, checking, and addition of harness data to the horizontal parity addition bit by using a preliminary loop immediately after desired data in the horizontal direction as the horizontal parity addition bit.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

In FIG. 1, 1 to 6 refer to the same components shown in FIG. 2 with the same reference numerals, and their operations are the same as those described in FIGS. 5 to 7, so their description will be omitted. Here, Figure 1 shows Le +
This figure shows a magnetic bubble memory unit consisting of one bubble, 7''ll&L O~N13.

FIG. 2 is an explanatory diagram showing the concept of the embodiment shown in FIG. 1, and is a plan view showing the minor loop of the magnetic bubble unit. A partial defective loop 15 exists in the minor loop of the loop. At this time, the defective loop is corrected using the backup loop +(--3) to -17pm, but in this case, the horizontal parity additional bit is The arrangement is shown as 6 in the figure, and the magnetic bubble chip N[L3 in which the defective loop 13 exists has the arrangement shown as 14 in the figure. In this way, horizontal parity addition bits are generally arranged in different spare chips for bubble chips with defective loops and bubble chips without defective loops. As a result, the horizontal parity additional bits are read out at different timings.

〔Effect of the invention〕

According to the present invention, the detection, checking, and addition of parity data to horizontal parity addition bits can be easily controlled compared to conventional methods, and when an error is detected in a certain information unit, it is possible to easily control which bit has an error. Errors can be detected immediately, and since the backup loop is effectively used to perform the horizontal parity check, errors can be detected without increasing the number of errors and with a faster access time than before.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a magnetic bubble unit showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the concept of the embodiment shown in FIG. 1, and FIG. 3 is a memory unit of a conventional magnetic bubble memory device. Figure 4 is one of the units in Figure 3.
FIG. 5 is a diagram showing an example of the configuration of a circuit that implements a conventional memory control method. FIG. 6 is a circuit diagram showing an example of a conventional parity check and parity generation circuit. This figure is an explanatory diagram showing the concept of the conventional embodiment shown in FIG. 3. Description of symbols 1...Minor loop, 2...Major loop, 3-way detector, 4...Bubble elimination generator, 5...Vertical parity addition robit), <S, 14...Horizontal parity addition robit, 7...Magnetic bubble memory unit, 8.
...Horizontal parity check circuit, 9...Horizontal parity generation circuit 110...Vertical parity check circuit, 11
... Vertical parity generation circuit, 12 ... Control circuit, 1
3...Defect loop 栴 l 庬謬 2 囌 3 庬萓 fig. 41□J1-2 Shun 42 Town Hatsuto 5 zu 栴 6 说 7 fig.

Claims (1)

[Claims] 1. A plurality of first information loops made of shift register-like memories and a second information loop made of shift register-like memories that read and write information to and from the first information loops are made into one structural unit, A memory consisting of a memory unit composed of a plurality of constituent units, and capable of partially writing and partially reading variable-length data whose unit information is a plurality of bits that are read or written at the same timing from each constituent unit of the memory unit. In the apparatus, vertical check bits are provided for error detection in each unit of information, and horizontal check bits are provided for error detection in information in which bits at the same position are each set as one block for a plurality of unit information. A memory control method that is provided in each block and detects errors at different timings.