JPS63104394A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPS63104394A JPS63104394A JP24830386A JP24830386A JPS63104394A JP S63104394 A JPS63104394 A JP S63104394A JP 24830386 A JP24830386 A JP 24830386A JP 24830386 A JP24830386 A JP 24830386A JP S63104394 A JPS63104394 A JP S63104394A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- power supply
- circuit
- lsi
- supply terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、複数の回路が実装された回路基板で、特に１
つの回路を単独で動作させる回路基板に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit board on which a plurality of circuits are mounted, particularly one
This invention relates to a circuit board that allows two circuits to operate independently.
従来、複数の回路が実装された回路基板は、各回路に供
給される電源が同一種の場合には、１つの電源供給端子
から電源を供給している。Conventionally, in a circuit board on which a plurality of circuits are mounted, power is supplied from one power supply terminal when the same type of power is supplied to each circuit.
複数の回路が実装されている回路基板で１つの回路を検
査する場合、例えば、第２図は従来の回路基板の一例の
ブロック図であるが、大規模集積回路（ＬＳＩ）１５．
集積回路（ＩＣ）１３．電子回路１２．１４が実装され
た回路基板１１でＬＳ１１５をインサーキット方式にて
検査する場合、ＬＳ１１５を活性状態にするため電源供
給端子１６より電源を供給するのでＩＣｌ３．電子回路
１２．１４も活性状態となる。このとき信号路１８ａ、
１８ｂ、 １８ｃに信号が流れるので被試験ＬＳ１１
５へのまわりごみの影客を防止するガーディング作業が
複雑になり、ノイズの発生や信号のフィードバック・ル
ープの形成を完全に防止できないため、ＬＳ１１５の検
査が安定してできないという欠点がある。When testing a single circuit on a circuit board on which multiple circuits are mounted, for example, as shown in FIG. 2, which is a block diagram of an example of a conventional circuit board, a large-scale integrated circuit (LSI) 15.
Integrated circuit (IC)13. When testing the LS115 using the in-circuit method on the circuit board 11 on which the electronic circuits 12 and 14 are mounted, power is supplied from the power supply terminal 16 to activate the LS115, so ICl3. Electronic circuits 12.14 are also activated. At this time, the signal path 18a,
Since the signal flows to 18b and 18c, the LS11 under test
The guarding work to prevent surrounding debris from entering the LS115 is complicated, and the generation of noise and the formation of signal feedback loops cannot be completely prevented, so the LS115 cannot be inspected stably.
さらに、インサーキットテストの手法であるパルスイン
ジェクション（米国特許第３８７０９５３号）により被
試験ＬＳ１１５の前段に接続されたＩＣｌ３が破壊され
るという欠点がある。Furthermore, there is a drawback that the ICl3 connected to the front stage of the LS 115 under test is destroyed by pulse injection (US Pat. No. 3,870,953), which is an in-circuit test method.
本発明はこれらの欠点を除去し、安定してＬＳＩの検査
ができる回路基板を提供することにある。The object of the present invention is to eliminate these drawbacks and provide a circuit board that allows stable LSI testing.
本発明は複数の回路が実装された回路基板において、
１つの回路を単独で動作させる電源を供給する第１の電
源供給端子と、
他の回路を動作させる電源を供給する第２の電源供給端
子とを有することを特徴としている。The present invention provides a circuit board on which a plurality of circuits are mounted, a first power supply terminal that supplies power to operate one circuit independently, and a second power supply terminal that supplies power to operate other circuits. It is characterized by having the following.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明による一実施例を示すブロック図である
。この回路基板は、第１の電源供給端子７と、第２の電
源供給端子６とで構成される。FIG. 1 is a block diagram showing an embodiment according to the present invention. This circuit board is composed of a first power supply terminal 7 and a second power supply terminal 6.
回路基板１には、複数の回路である電子回路２゜４とＩ
Ｃ３とＬＳＩ５とが実装されている。The circuit board 1 has a plurality of electronic circuits 2゜4 and I
C3 and LSI5 are implemented.
電源供給端子７は、電源供給路９を介してＬＳＩ５と接
続される。電源供給端子６は、電源供給路１０を介して
電子回路２，４とＩＣ３とに接続される。ＩＣ３は信号
路８ｃを介してＬＳＩ５と接続され、電子回路２は信号
路８ａを介してＬＳＩ５と接続され、電子回路４は信号
路８ｂを介してＬＳＩ５と接続される。The power supply terminal 7 is connected to the LSI 5 via a power supply path 9. The power supply terminal 6 is connected to the electronic circuits 2 and 4 and the IC 3 via a power supply path 10. IC3 is connected to LSI 5 via signal path 8c, electronic circuit 2 is connected to LSI 5 via signal path 8a, and electronic circuit 4 is connected to LSI 5 via signal path 8b.
次に本実施例の動作を説明する。なお本実施例では、回
路基板に実装されたＬＳＩ５を実装された状態で検査す
る場合について説明する。１つの回路であるＬＳＩ５を
検査する場合、ＬＳＩ５のみを活性化しなければならな
いので、電源供給端子７に電源を接続し、この電源は電
源供給路９を介してＬＳＩ５に印加される。電源供給端
子６には電源が接続されないので、電子回路２，４とＩ
Ｃ３は活性化されず、信号路８ａ、 ８ｂ、 ８ｃには
電子回路２．４とＩＣ３とからの信号が流れることはな
く、信号路８ａ、 ８ｂ、 ８ｃはオープン状態となる
。Next, the operation of this embodiment will be explained. In this embodiment, a case where an LSI 5 mounted on a circuit board is inspected in a mounted state will be described. When testing one circuit, LSI 5, it is necessary to activate only LSI 5, so a power supply is connected to power supply terminal 7, and this power is applied to LSI 5 via power supply path 9. Since no power is connected to the power supply terminal 6, the electronic circuits 2, 4 and I
C3 is not activated, and the signals from the electronic circuit 2.4 and IC3 do not flow through the signal paths 8a, 8b, 8c, and the signal paths 8a, 8b, 8c are in an open state.
この状態で、ＬＳＩ５の信号路８ａ、 ８ｃに外部から
任意の信号を印加し、ＬＳＩ５から出力された信号を信
号路８ｂで観測することによりＬＳＩ５を活性化した状
態で検査できる。このとき、信号路８ａ。In this state, by applying arbitrary signals from the outside to the signal paths 8a and 8c of the LSI 5 and observing the signal output from the LSI 5 on the signal path 8b, the LSI 5 can be inspected in an activated state. At this time, the signal path 8a.
８ｃに外部から任意の信号を印加するので電子回路２と
ＩＣ３とにこの信号が印加されるが、電子回路２とＩＣ
３は活性化されてないので、印加された信号が電子回路
２とＩＣ３に影響を与えることはない。Since an arbitrary signal is applied to 8c from the outside, this signal is applied to the electronic circuit 2 and the IC3.
3 is not activated, the applied signal does not affect the electronic circuit 2 and IC3.
本実施例では、回路基板の１辺に設けられた１つの電源
供給端子を使用したが、電源供給端子はこれに限定され
ることはなく、端子の数が複数個でも適用される。また
端子として回路基板のプリントコンタクト等の適用も可
能である。In this embodiment, one power supply terminal provided on one side of the circuit board is used, but the power supply terminal is not limited to this, and a plurality of terminals may be used. It is also possible to use printed contacts on circuit boards as terminals.
以上説明したように、複数の回路が実装された回路基板
に、１つの回路を単独で動作させる電源を供給する電源
供給端子を設けることにより、例えば、ＬＳＩを回路基
板内に実装した状態で、このＬＳＩの検査を行うことが
でき、他の回路は活性化されないので、ノイズの発生や
信号のフィードバンク・ループの形成を防止する効果が
あり、さらにインサーキットテストの手法であるパルス
インジェクションを用いないのでＬＳＩの前段に接続さ
れたＩＣの破壊を防ぐ効果がある。As explained above, by providing a power supply terminal for supplying power to operate one circuit independently on a circuit board on which a plurality of circuits are mounted, for example, when an LSI is mounted on the circuit board, This LSI test can be performed without activating other circuits, which has the effect of preventing the generation of noise and the formation of signal feedbank loops.Furthermore, it uses pulse injection, which is an in-circuit test method. This has the effect of preventing damage to the IC connected to the front stage of the LSI.
第１回は、本発明による一実施例を示すブロック図、
第２図は、従来の回路基板の電源供給を示すブロック図
である。The first part is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing the power supply of a conventional circuit board.
Claims (1)
の回路を単独で動作させる電源を供給する第１の電源供
給端子と、 他の回路を動作させる電源を供給する第２の電源供給端
子とを有することを特徴とする回路基板。(1) In a circuit board on which multiple circuits are mounted, a first power supply terminal supplies power to operate one circuit independently, and a second power supply terminal supplies power to operate other circuits. A circuit board comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24830386A JPS63104394A (en) | 1986-10-21 | 1986-10-21 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24830386A JPS63104394A (en) | 1986-10-21 | 1986-10-21 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63104394A true JPS63104394A (en) | 1988-05-09 |
Family
ID=17176067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24830386A Pending JPS63104394A (en) | 1986-10-21 | 1986-10-21 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63104394A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8567710B2 (en) | 2007-09-18 | 2013-10-29 | Aero Asahi Corporation | Cable protection device |
-
1986
- 1986-10-21 JP JP24830386A patent/JPS63104394A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8567710B2 (en) | 2007-09-18 | 2013-10-29 | Aero Asahi Corporation | Cable protection device |
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