JPS63103974A - Logic analyzer - Google Patents

Abstract

PURPOSE:To perform long-time measurement by expanding and reproducing pulse waveform information stored in a memory part by continuance stored in a clock memory part. CONSTITUTION:A comparison part 11 compares the pulse waveform information A of a measurement bus 1 with the trigger point of a trigger bus 2 and supplies a trigger signal B to an input control part 12 through a signal line 22 when they coincide with each other. The control part 12 instructs the storage of a counted value by the signal B to a clock memory 14 through a clock write line 24, and the memory 14 stores the counted value inputted through a clock bus 3. Further, the control part 12 instructs the reproduction of the information A to the reproduction part 15 through a reproduction instruction line 25 and the reproduction part 15 instructs the read of the information A to the memory 13 through a control line 26 and also instructs the read of the continuance of the information A to the memory 14 through a lead line 21. The memory 13 outputs the information A to the bus 4 by the instruction and the memory 14 outputs the continuance of the information A to a bus 5. The reproduction part 15 expands the information A of the bus 4 by the continuance of the bus 5 and outputs the result to a bus 6, so that long-time measuring operation is performed with small memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a logic analyzer for observing pulse waveform states of logic circuits.

(Prior Art) Conventionally, this type of logic analyzer is equipped with a memory for storing pulse waveform information at a measurement point.When measurement is started, the pulse waveform information at a measurement point is stored in this memory at measurement period intervals. It is designed to store waveform information. When more pulse waveform information than the memory capacity is given, the old pulse waveform information exceeding the memory capacity is discarded, and the latest pulse waveform information is always stored for the memory capacity.

On the other hand, in addition to the measurement period lζ in which the pulse waveform is stored in advance before starting the measurement, a trigger point is set to stop the measurement when a certain special event appears in the pulse waveform at the measurement point. When the pulse waveform information of the third trigger point appears, the logic analyzer stops measurement and outputs the stored pulse waveform information to the outside.

(Problem to be Solved by the Invention) Conventional logic analyzers have the configuration described above, so even if the pulse waveform can be observed at most, it is difficult to observe the pulse waveform only for a period of time within the range of the measurement period and memory capacity, starting from the trigger point. I couldn't do it. Therefore, when the cause of the pulse waveform state at the trigger point is a pulse waveform state outside the observation range, it is not possible to MIll the cause pulse waveform state. And if you want to observe the pulse waveform that is the cause, you have to either increase the measurement cycle and observe the measured value, or you have to add a large amount of memory and observe the pulse waveform. was there.

The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to provide a logic analyzer that can perform long-term measurements with a small memory capacity without reducing the accuracy of the measurement cycle.

[Means for solving problems]

In order to achieve the above object, the logic analyzer of the present invention has a memory unit that stores pulse waveform information at a measurement point, and compares the stored pulse waveform information with pulse waveform information measured in a previous measurement cycle. a comparison section, an input control section that detects the duration of the same pulse waveform information based on the comparison result, a clock memory section that stores the duration detected by the input control section, and a pulse stored in the memory section. and a reproducing section that reproduces the waveform information by enlarging it by the duration stored in the clock memory section.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a logic analyzer according to this embodiment.

In the drawing, 13 is a memory section that stores pulse waveform information at a measurement point, and 11 is a comparison section that compares the pulse waveform information stored in the memory section 13 with the pulse waveform information measured in the previous measurement cycle. It consists of a circuit, a comparison circuit, and various gates. Reference numeral 12 denotes an input control section that detects the duration of the same pulse waveform information based on the comparison result in the comparison section 11, and is composed of a counter and various logics. Reference numeral 14 denotes a clock memory section that stores the duration detected in input control section [2].

In addition to the above-mentioned functions, the input control section 2 also controls each section. In the figure, reference numeral 15 denotes a reproducing unit that enlarges the pulse waveform information stored in the memory unit 13 by the duration stored in the clock memory unit 14 and reproduces the pulse waveform information.

Next, the operation will be explained.

When measurement is started, a sampling clock is applied to the input control section 12 through the measurement period line 21. Input control unit 2 increments the counter value by 1 when a sampling clock is applied, and instructs the comparison unit 11 to latch the pulse waveform information through the comparison unit control line 28, and stores the pulse waveform information through the write control line 23. is instructed to the memory unit 13. When instructed to latch the pulse waveform information, the comparator 11 latches the pulse waveform information given through the measurement bus 1 to the latch circuit. Furthermore, when memory section 13 is instructed to store pulse waveform information, it stores pulse waveform information that can be viewed through measurement bus 1. When this memory section 13 is given pulse waveform information in excess of the memory capacity, it discards old pulse waveform information in excess of the memory capacity and always stores the latest pulse waveform information in an amount equal to the memory capacity.

When the re-hisampling clock is applied to the input control section 12, the input control section 12 sends a comparison instruction to the comparison section 11 through the comparison section control line 2B.

When a comparison instruction is given, the comparison section 11 compares the pulse waveform information of the latch circuit with the pulse waveform information given through the measurement bus 1. If the comparison results are equal, a count up (M number) is applied, and if the comparison results are not equal, a reset signal is applied to the input control section 12 through the comparison signal line 22.

When the input control section 12 receives the count-up signal, it increments the input value by +1. When a reset signal is applied, the counter value is output to the clock bus 3, the clock memory section 14 is instructed to store the counter value through the clock write line 24, and the pulse waveform information is latched to the comparison section 11 through the comparison section control line 2B. After instructing the memory unit 13 to store the pulse waveform information through the write control line 23, the counter value is set to 1.

When instructed to store a counter value, the clock memory section 14 stores the counter value applied throughout the clock bus 3. When the comparator 11 is instructed to latch pulse waveform information, it latches the pulse waveform information given through the measurement path 1 to the latch circuit. When memory section 3 is instructed to store pulse waveform information, it stores pulse waveform information given through measurement path 1. This series of operations is repeated every time a complete clock pulse is seen, so information is stored in the memory section 13 only when the pulse waveform changes, and the state of the clock pulse waveform changes in the clock memory section 14i. I remember the times when I didn't.

On the other hand, the comparison section 11 compares the pulse waveform information given through the measurement path 1 and the trigger point given through the trigger path 2, and when they match, gives a trigger signal to the input control section 12 through the comparison signal line 22. When the input control section 12 receives a trigger letter, it outputs the counter value to the clock output 3, instructs the clock memory section 14 to store the counter value through the clock write line 24, and outputs the pulse waveform to the reproducing section 15 through the reproduction instruction line 25. Instructs to play information. Clock memory unit 4 stores the counter value given through clock path 3 when storage of the counter value is instructed. When the reproduction unit 15 is instructed to reproduce the pulse waveform information, it gives a read instruction to the memory unit 13 through the read control line 26 in order to read out the pulse waveform information, and in order to read out the continuous time of this pulse waveform information. A read instruction is given to the clock memory unit 14 through the time lead line 27. When the memory unit 13 receives a read instruction, it outputs pulse waveform information to the reproduction path 4. When the clock memory section 14 is given a read instruction, it outputs the duration of the pulse waveform to the time path S. The reproduction section 5 enlarges the pulse waveform information given through the reproduction path 4 by the duration given through the time path S and outputs it to the output path 6.

(Effects of the Invention) As explained above, according to the present invention, pulse waveform information can be compressed and stored, so long-term measurements can be performed with a small memory capacity without reducing the accuracy of the measurement cycle. There is. In particular, this method is effective for observing path waveforms in which the pulse waveform does not change for a long time and the path waveform changes only for short periods of time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a logic analyzer according to an embodiment of the present invention. l...Measurement bus 2...Trigger path 3...Clock path 4...Reproduction path S...Time path 6...Output path 11...Comparison section 12...Input control section 13. e.memory section 14.e.clock memory section 15...reproduction section 21...measurement cycle line 22...comparison signal line 23-fist/write control line 2411...clock write line 25...reproduction instruction Line 26...Read control line 2)...Time lead line 28...Comparison control signal line

Claims (1)

[Claims] a memory unit that stores pulse waveform information at a measurement point; a comparison unit that compares the stored pulse waveform information with pulse waveform information measured in a previous measurement cycle; an input control section that detects the duration of the pulse waveform, a clock memory section that stores the duration time detected by the input control section, and a clock memory section that stores the pulse waveform information stored in the memory section for the duration time that the clock memory section stores. A logic analyzer characterized by comprising a playback section that enlarges and plays back.